mirror of https://gitee.com/openkylin/linux.git
163 lines
4.6 KiB
C
163 lines
4.6 KiB
C
/*
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* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
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#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_PERIPH0 3
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#define CLK_C0CPUX 12
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#define CLK_C1CPUX 13
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#define CLK_OUT_A 27
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#define CLK_OUT_B 28
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#define CLK_NAND0_0 29
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#define CLK_NAND0_1 30
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#define CLK_NAND1_0 31
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#define CLK_NAND1_1 32
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#define CLK_MMC0 33
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#define CLK_MMC0_SAMPLE 34
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#define CLK_MMC0_OUTPUT 35
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#define CLK_MMC1 36
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#define CLK_MMC1_SAMPLE 37
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#define CLK_MMC1_OUTPUT 38
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#define CLK_MMC2 39
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#define CLK_MMC2_SAMPLE 40
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#define CLK_MMC2_OUTPUT 41
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#define CLK_MMC3 42
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#define CLK_MMC3_SAMPLE 43
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#define CLK_MMC3_OUTPUT 44
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#define CLK_TS 45
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#define CLK_SS 46
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#define CLK_SPI0 47
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#define CLK_SPI1 48
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#define CLK_SPI2 49
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#define CLK_SPI3 50
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#define CLK_I2S0 51
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#define CLK_I2S1 52
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#define CLK_SPDIF 53
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#define CLK_SDRAM 54
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#define CLK_DE 55
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#define CLK_EDP 56
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#define CLK_MP 57
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#define CLK_LCD0 58
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#define CLK_LCD1 59
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#define CLK_MIPI_DSI0 60
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#define CLK_MIPI_DSI1 61
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#define CLK_HDMI 62
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#define CLK_HDMI_SLOW 63
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#define CLK_MIPI_CSI 64
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#define CLK_CSI_ISP 65
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#define CLK_CSI_MISC 66
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#define CLK_CSI0_MCLK 67
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#define CLK_CSI1_MCLK 68
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#define CLK_FD 69
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#define CLK_VE 70
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#define CLK_AVS 71
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#define CLK_GPU_CORE 72
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#define CLK_GPU_MEMORY 73
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#define CLK_GPU_AXI 74
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#define CLK_SATA 75
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#define CLK_AC97 76
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#define CLK_MIPI_HSI 77
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#define CLK_GPADC 78
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#define CLK_CIR_TX 79
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#define CLK_BUS_FD 80
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#define CLK_BUS_VE 81
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#define CLK_BUS_GPU_CTRL 82
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#define CLK_BUS_SS 83
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#define CLK_BUS_MMC 84
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#define CLK_BUS_NAND0 85
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#define CLK_BUS_NAND1 86
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#define CLK_BUS_SDRAM 87
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#define CLK_BUS_MIPI_HSI 88
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#define CLK_BUS_SATA 89
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#define CLK_BUS_TS 90
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#define CLK_BUS_SPI0 91
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#define CLK_BUS_SPI1 92
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#define CLK_BUS_SPI2 93
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#define CLK_BUS_SPI3 94
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#define CLK_BUS_OTG 95
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#define CLK_BUS_USB 96
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#define CLK_BUS_GMAC 97
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#define CLK_BUS_MSGBOX 98
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#define CLK_BUS_SPINLOCK 99
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#define CLK_BUS_HSTIMER 100
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#define CLK_BUS_DMA 101
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#define CLK_BUS_LCD0 102
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#define CLK_BUS_LCD1 103
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#define CLK_BUS_EDP 104
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#define CLK_BUS_CSI 105
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#define CLK_BUS_HDMI 106
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#define CLK_BUS_DE 107
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#define CLK_BUS_MP 108
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#define CLK_BUS_MIPI_DSI 109
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#define CLK_BUS_SPDIF 110
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#define CLK_BUS_PIO 111
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#define CLK_BUS_AC97 112
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#define CLK_BUS_I2S0 113
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#define CLK_BUS_I2S1 114
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#define CLK_BUS_LRADC 115
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#define CLK_BUS_GPADC 116
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#define CLK_BUS_TWD 117
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#define CLK_BUS_CIR_TX 118
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#define CLK_BUS_I2C0 119
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#define CLK_BUS_I2C1 120
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#define CLK_BUS_I2C2 121
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#define CLK_BUS_I2C3 122
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#define CLK_BUS_I2C4 123
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#define CLK_BUS_UART0 124
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#define CLK_BUS_UART1 125
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#define CLK_BUS_UART2 126
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#define CLK_BUS_UART3 127
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#define CLK_BUS_UART4 128
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#define CLK_BUS_UART5 129
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#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */
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