mirror of https://gitee.com/openkylin/linux.git
1176 lines
28 KiB
C
1176 lines
28 KiB
C
/*
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* mt9t112 Camera Driver
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on ov772x driver, mt9m111 driver,
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*
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* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
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* Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
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* Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
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* Copyright (C) 2008 Magnus Damm
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/videodev2.h>
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#include <media/mt9t112.h>
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#include <media/soc_camera.h>
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#include <media/soc_mediabus.h>
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#include <media/v4l2-chip-ident.h>
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#include <media/v4l2-common.h>
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/* you can check PLL/clock info */
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/* #define EXT_CLOCK 24000000 */
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/************************************************************************
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macro
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************************************************************************/
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/*
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* frame size
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*/
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#define MAX_WIDTH 2048
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#define MAX_HEIGHT 1536
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#define VGA_WIDTH 640
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#define VGA_HEIGHT 480
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/*
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* macro of read/write
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*/
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#define ECHECKER(ret, x) \
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do { \
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(ret) = (x); \
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if ((ret) < 0) \
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return (ret); \
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} while (0)
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#define mt9t112_reg_write(ret, client, a, b) \
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ECHECKER(ret, __mt9t112_reg_write(client, a, b))
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#define mt9t112_mcu_write(ret, client, a, b) \
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ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
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#define mt9t112_reg_mask_set(ret, client, a, b, c) \
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ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
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#define mt9t112_mcu_mask_set(ret, client, a, b, c) \
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ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
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#define mt9t112_reg_read(ret, client, a) \
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ECHECKER(ret, __mt9t112_reg_read(client, a))
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/*
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* Logical address
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*/
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#define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
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#define VAR(id, offset) _VAR(id, offset, 0x0000)
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#define VAR8(id, offset) _VAR(id, offset, 0x8000)
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/************************************************************************
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struct
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************************************************************************/
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struct mt9t112_frame_size {
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u16 width;
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u16 height;
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};
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struct mt9t112_format {
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enum v4l2_mbus_pixelcode code;
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enum v4l2_colorspace colorspace;
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u16 fmt;
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u16 order;
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};
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struct mt9t112_priv {
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struct v4l2_subdev subdev;
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struct mt9t112_camera_info *info;
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struct i2c_client *client;
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struct soc_camera_device icd;
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struct mt9t112_frame_size frame;
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const struct mt9t112_format *format;
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int model;
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u32 flags;
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/* for flags */
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#define INIT_DONE (1<<0)
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};
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/************************************************************************
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supported format
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************************************************************************/
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static const struct mt9t112_format mt9t112_cfmts[] = {
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{
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.code = V4L2_MBUS_FMT_YUYV8_2X8_BE,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.fmt = 1,
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.order = 0,
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}, {
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.code = V4L2_MBUS_FMT_YVYU8_2X8_BE,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.fmt = 1,
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.order = 1,
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}, {
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.code = V4L2_MBUS_FMT_YUYV8_2X8_LE,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.fmt = 1,
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.order = 2,
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}, {
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.code = V4L2_MBUS_FMT_YVYU8_2X8_LE,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.fmt = 1,
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.order = 3,
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}, {
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.code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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.fmt = 8,
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.order = 2,
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}, {
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.code = V4L2_MBUS_FMT_RGB565_2X8_LE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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.fmt = 4,
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.order = 2,
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},
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};
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/************************************************************************
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general function
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************************************************************************/
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static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
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{
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return container_of(i2c_get_clientdata(client),
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struct mt9t112_priv,
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subdev);
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}
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static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
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{
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struct i2c_msg msg[2];
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u8 buf[2];
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int ret;
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command = swab16(command);
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msg[0].addr = client->addr;
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msg[0].flags = 0;
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msg[0].len = 2;
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msg[0].buf = (u8 *)&command;
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msg[1].addr = client->addr;
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msg[1].flags = I2C_M_RD;
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msg[1].len = 2;
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msg[1].buf = buf;
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/*
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* if return value of this function is < 0,
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* it mean error.
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* else, under 16bit is valid data.
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*/
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ret = i2c_transfer(client->adapter, msg, 2);
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if (ret < 0)
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return ret;
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memcpy(&ret, buf, 2);
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return swab16(ret);
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}
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static int __mt9t112_reg_write(const struct i2c_client *client,
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u16 command, u16 data)
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{
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struct i2c_msg msg;
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u8 buf[4];
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int ret;
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command = swab16(command);
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data = swab16(data);
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memcpy(buf + 0, &command, 2);
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memcpy(buf + 2, &data, 2);
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msg.addr = client->addr;
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msg.flags = 0;
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msg.len = 4;
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msg.buf = buf;
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/*
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* i2c_transfer return message length,
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* but this function should return 0 if correct case
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*/
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ret = i2c_transfer(client->adapter, &msg, 1);
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if (ret >= 0)
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ret = 0;
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return ret;
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}
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static int __mt9t112_reg_mask_set(const struct i2c_client *client,
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u16 command,
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u16 mask,
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u16 set)
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{
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int val = __mt9t112_reg_read(client, command);
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if (val < 0)
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return val;
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val &= ~mask;
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val |= set & mask;
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return __mt9t112_reg_write(client, command, val);
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}
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/* mcu access */
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static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
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{
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int ret;
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ret = __mt9t112_reg_write(client, 0x098E, command);
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if (ret < 0)
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return ret;
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return __mt9t112_reg_read(client, 0x0990);
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}
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static int __mt9t112_mcu_write(const struct i2c_client *client,
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u16 command, u16 data)
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{
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int ret;
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ret = __mt9t112_reg_write(client, 0x098E, command);
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if (ret < 0)
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return ret;
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return __mt9t112_reg_write(client, 0x0990, data);
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}
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static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
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u16 command,
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u16 mask,
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u16 set)
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{
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int val = __mt9t112_mcu_read(client, command);
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if (val < 0)
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return val;
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val &= ~mask;
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val |= set & mask;
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return __mt9t112_mcu_write(client, command, val);
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}
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static int mt9t112_reset(const struct i2c_client *client)
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{
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int ret;
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mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
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msleep(1);
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mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
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return ret;
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}
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#ifndef EXT_CLOCK
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#define CLOCK_INFO(a, b)
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#else
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#define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
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static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
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{
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int m, n, p1, p2, p3, p4, p5, p6, p7;
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u32 vco, clk;
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char *enable;
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ext /= 1000; /* kbyte order */
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mt9t112_reg_read(n, client, 0x0012);
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p1 = n & 0x000f;
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n = n >> 4;
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p2 = n & 0x000f;
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n = n >> 4;
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p3 = n & 0x000f;
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mt9t112_reg_read(n, client, 0x002a);
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p4 = n & 0x000f;
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n = n >> 4;
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p5 = n & 0x000f;
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n = n >> 4;
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p6 = n & 0x000f;
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mt9t112_reg_read(n, client, 0x002c);
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p7 = n & 0x000f;
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mt9t112_reg_read(n, client, 0x0010);
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m = n & 0x00ff;
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n = (n >> 8) & 0x003f;
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enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
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dev_info(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
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vco = 2 * m * ext / (n+1);
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enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
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dev_info(&client->dev, "VCO : %10u K %s\n", vco, enable);
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clk = vco / (p1+1) / (p2+1);
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enable = (96000 < clk) ? "X" : "";
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dev_info(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
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clk = vco / (p3+1);
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enable = (768000 < clk) ? "X" : "";
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dev_info(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
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clk = vco / (p6+1);
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enable = (96000 < clk) ? "X" : "";
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dev_info(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
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clk = vco / (p5+1);
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enable = (54000 < clk) ? "X" : "";
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dev_info(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
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clk = vco / (p4+1);
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enable = (70000 < clk) ? "X" : "";
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dev_info(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
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clk = vco / (p7+1);
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dev_info(&client->dev, "External sensor : %10u K\n", clk);
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clk = ext / (n+1);
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enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
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dev_info(&client->dev, "PFD : %10u K %s\n", clk, enable);
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return 0;
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}
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#endif
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static void mt9t112_frame_check(u32 *width, u32 *height)
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{
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if (*width > MAX_WIDTH)
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*width = MAX_WIDTH;
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if (*height > MAX_HEIGHT)
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*height = MAX_HEIGHT;
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}
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static int mt9t112_set_a_frame_size(const struct i2c_client *client,
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u16 width,
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u16 height)
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{
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int ret;
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u16 wstart = (MAX_WIDTH - width) / 2;
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u16 hstart = (MAX_HEIGHT - height) / 2;
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/* (Context A) Image Width/Height */
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mt9t112_mcu_write(ret, client, VAR(26, 0), width);
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mt9t112_mcu_write(ret, client, VAR(26, 2), height);
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/* (Context A) Output Width/Height */
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mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
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mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
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/* (Context A) Start Row/Column */
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mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
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mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
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/* (Context A) End Row/Column */
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mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
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mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
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mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
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return ret;
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}
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static int mt9t112_set_pll_dividers(const struct i2c_client *client,
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u8 m, u8 n,
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u8 p1, u8 p2, u8 p3,
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u8 p4, u8 p5, u8 p6,
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u8 p7)
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{
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int ret;
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u16 val;
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/* N/M */
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val = (n << 8) |
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(m << 0);
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mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
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/* P1/P2/P3 */
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val = ((p3 & 0x0F) << 8) |
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((p2 & 0x0F) << 4) |
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((p1 & 0x0F) << 0);
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mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
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/* P4/P5/P6 */
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val = (0x7 << 12) |
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((p6 & 0x0F) << 8) |
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((p5 & 0x0F) << 4) |
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((p4 & 0x0F) << 0);
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mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
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/* P7 */
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val = (0x1 << 12) |
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((p7 & 0x0F) << 0);
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mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
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return ret;
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}
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static int mt9t112_init_pll(const struct i2c_client *client)
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{
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struct mt9t112_priv *priv = to_mt9t112(client);
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int data, i, ret;
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mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
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/* PLL control: BYPASS PLL = 8517 */
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mt9t112_reg_write(ret, client, 0x0014, 0x2145);
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/* Replace these registers when new timing parameters are generated */
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mt9t112_set_pll_dividers(client,
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priv->info->divider.m,
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priv->info->divider.n,
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priv->info->divider.p1,
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priv->info->divider.p2,
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priv->info->divider.p3,
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priv->info->divider.p4,
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priv->info->divider.p5,
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priv->info->divider.p6,
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priv->info->divider.p7);
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/*
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* TEST_BYPASS on
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* PLL_ENABLE on
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* SEL_LOCK_DET on
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* TEST_BYPASS off
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*/
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mt9t112_reg_write(ret, client, 0x0014, 0x2525);
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mt9t112_reg_write(ret, client, 0x0014, 0x2527);
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mt9t112_reg_write(ret, client, 0x0014, 0x3427);
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mt9t112_reg_write(ret, client, 0x0014, 0x3027);
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mdelay(10);
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/*
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* PLL_BYPASS off
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* Reference clock count
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* I2C Master Clock Divider
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*/
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mt9t112_reg_write(ret, client, 0x0014, 0x3046);
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mt9t112_reg_write(ret, client, 0x0022, 0x0190);
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mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
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/* External sensor clock is PLL bypass */
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mt9t112_reg_write(ret, client, 0x002E, 0x0500);
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mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
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mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
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/* MCU disabled */
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mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
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/* out of standby */
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mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
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mdelay(50);
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/*
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* Standby Workaround
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* Disable Secondary I2C Pads
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*/
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mt9t112_reg_write(ret, client, 0x0614, 0x0001);
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mdelay(1);
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mt9t112_reg_write(ret, client, 0x0614, 0x0001);
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mdelay(1);
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mt9t112_reg_write(ret, client, 0x0614, 0x0001);
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mdelay(1);
|
|
mt9t112_reg_write(ret, client, 0x0614, 0x0001);
|
|
mdelay(1);
|
|
mt9t112_reg_write(ret, client, 0x0614, 0x0001);
|
|
mdelay(1);
|
|
mt9t112_reg_write(ret, client, 0x0614, 0x0001);
|
|
mdelay(1);
|
|
|
|
/* poll to verify out of standby. Must Poll this bit */
|
|
for (i = 0; i < 100; i++) {
|
|
mt9t112_reg_read(data, client, 0x0018);
|
|
if (!(0x4000 & data))
|
|
break;
|
|
|
|
mdelay(10);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt9t112_init_setting(const struct i2c_client *client)
|
|
{
|
|
|
|
int ret;
|
|
|
|
/* Adaptive Output Clock (A) */
|
|
mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
|
|
|
|
/* Read Mode (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
|
|
|
|
/* Fine Correction (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
|
|
|
|
/* Fine IT Min (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
|
|
|
|
/* Fine IT Max Margin (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
|
|
|
|
/* Base Frame Lines (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
|
|
|
|
/* Min Line Length (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
|
|
|
|
/* Line Length (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
|
|
|
|
/* Adaptive Output Clock (B) */
|
|
mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
|
|
|
|
/* Row Start (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
|
|
|
|
/* Column Start (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
|
|
|
|
/* Row End (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
|
|
|
|
/* Column End (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
|
|
|
|
/* Fine Correction (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
|
|
|
|
/* Fine IT Min (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
|
|
|
|
/* Fine IT Max Margin (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
|
|
|
|
/* Base Frame Lines (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
|
|
|
|
/* Min Line Length (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
|
|
|
|
/* Line Length (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
|
|
|
|
/*
|
|
* Flicker Dectection registers
|
|
* This section should be replaced whenever new Timing file is generated
|
|
* All the following registers need to be replaced
|
|
* Following registers are generated from Register Wizard but user can
|
|
* modify them. For detail see auto flicker detection tuning
|
|
*/
|
|
|
|
/* FD_FDPERIOD_SELECT */
|
|
mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
|
|
|
|
/* PRI_B_CONFIG_FD_ALGO_RUN */
|
|
mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
|
|
|
|
/* PRI_A_CONFIG_FD_ALGO_RUN */
|
|
mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
|
|
|
|
/*
|
|
* AFD range detection tuning registers
|
|
*/
|
|
|
|
/* search_f1_50 */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
|
|
|
|
/* search_f2_50 */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
|
|
|
|
/* search_f1_60 */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
|
|
|
|
/* search_f2_60 */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
|
|
|
|
/* period_50Hz (A) */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
|
|
|
|
/* secret register by aptina */
|
|
/* period_50Hz (A MSB) */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
|
|
|
|
/* period_60Hz (A) */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
|
|
|
|
/* secret register by aptina */
|
|
/* period_60Hz (A MSB) */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
|
|
|
|
/* period_50Hz (B) */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
|
|
|
|
/* secret register by aptina */
|
|
/* period_50Hz (B) MSB */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
|
|
|
|
/* period_60Hz (B) */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
|
|
|
|
/* secret register by aptina */
|
|
/* period_60Hz (B) MSB */
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
|
|
|
|
/* FD Mode */
|
|
mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
|
|
|
|
/* Stat_min */
|
|
mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
|
|
|
|
/* Stat_max */
|
|
mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
|
|
|
|
/* Min_amplitude */
|
|
mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
|
|
|
|
/* RX FIFO Watermark (A) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
|
|
|
|
/* RX FIFO Watermark (B) */
|
|
mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
|
|
|
|
/* MCLK: 16MHz
|
|
* PCLK: 73MHz
|
|
* CorePixCLK: 36.5 MHz
|
|
*/
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
|
|
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
|
|
mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt9t112_auto_focus_setting(const struct i2c_client *client)
|
|
{
|
|
int ret;
|
|
|
|
mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
|
|
mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
|
|
mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
|
|
|
|
mt9t112_reg_write(ret, client, 0x0614, 0x0000);
|
|
|
|
mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
|
|
mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
|
|
mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
|
|
mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
|
|
mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
|
|
mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
|
|
mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
|
|
mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
|
|
{
|
|
int ret;
|
|
|
|
mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt9t112_init_camera(const struct i2c_client *client)
|
|
{
|
|
int ret;
|
|
|
|
ECHECKER(ret, mt9t112_reset(client));
|
|
|
|
ECHECKER(ret, mt9t112_init_pll(client));
|
|
|
|
ECHECKER(ret, mt9t112_init_setting(client));
|
|
|
|
ECHECKER(ret, mt9t112_auto_focus_setting(client));
|
|
|
|
mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
|
|
|
|
/* Analog setting B */
|
|
mt9t112_reg_write(ret, client, 0x3084, 0x2409);
|
|
mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
|
|
mt9t112_reg_write(ret, client, 0x3094, 0x4949);
|
|
mt9t112_reg_write(ret, client, 0x3096, 0x4950);
|
|
|
|
/*
|
|
* Disable adaptive clock
|
|
* PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
|
|
* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
|
|
*/
|
|
mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
|
|
mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
|
|
|
|
/* Configure STatus in Status_before_length Format and enable header */
|
|
/* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
|
|
mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
|
|
|
|
/* Enable JPEG in context B */
|
|
/* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
|
|
mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
|
|
|
|
/* Disable Dac_TXLO */
|
|
mt9t112_reg_write(ret, client, 0x316C, 0x350F);
|
|
|
|
/* Set max slew rates */
|
|
mt9t112_reg_write(ret, client, 0x1E, 0x777);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/************************************************************************
|
|
|
|
|
|
soc_camera_ops
|
|
|
|
|
|
************************************************************************/
|
|
static int mt9t112_set_bus_param(struct soc_camera_device *icd,
|
|
unsigned long flags)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long mt9t112_query_bus_param(struct soc_camera_device *icd)
|
|
{
|
|
struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
struct soc_camera_link *icl = to_soc_camera_link(icd);
|
|
unsigned long flags = SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH |
|
|
SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH;
|
|
|
|
flags |= (priv->info->flags & MT9T112_FLAG_PCLK_RISING_EDGE) ?
|
|
SOCAM_PCLK_SAMPLE_RISING : SOCAM_PCLK_SAMPLE_FALLING;
|
|
|
|
if (priv->info->flags & MT9T112_FLAG_DATAWIDTH_8)
|
|
flags |= SOCAM_DATAWIDTH_8;
|
|
else
|
|
flags |= SOCAM_DATAWIDTH_10;
|
|
|
|
return soc_camera_apply_sensor_flags(icl, flags);
|
|
}
|
|
|
|
static struct soc_camera_ops mt9t112_ops = {
|
|
.set_bus_param = mt9t112_set_bus_param,
|
|
.query_bus_param = mt9t112_query_bus_param,
|
|
};
|
|
|
|
/************************************************************************
|
|
|
|
|
|
v4l2_subdev_core_ops
|
|
|
|
|
|
************************************************************************/
|
|
static int mt9t112_g_chip_ident(struct v4l2_subdev *sd,
|
|
struct v4l2_dbg_chip_ident *id)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
|
|
id->ident = priv->model;
|
|
id->revision = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_VIDEO_ADV_DEBUG
|
|
static int mt9t112_g_register(struct v4l2_subdev *sd,
|
|
struct v4l2_dbg_register *reg)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
int ret;
|
|
|
|
reg->size = 2;
|
|
mt9t112_reg_read(ret, client, reg->reg);
|
|
|
|
reg->val = (__u64)ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_s_register(struct v4l2_subdev *sd,
|
|
struct v4l2_dbg_register *reg)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
int ret;
|
|
|
|
mt9t112_reg_write(ret, client, reg->reg, reg->val);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
|
|
.g_chip_ident = mt9t112_g_chip_ident,
|
|
#ifdef CONFIG_VIDEO_ADV_DEBUG
|
|
.g_register = mt9t112_g_register,
|
|
.s_register = mt9t112_s_register,
|
|
#endif
|
|
};
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
v4l2_subdev_video_ops
|
|
|
|
|
|
************************************************************************/
|
|
static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
int ret = 0;
|
|
|
|
if (!enable) {
|
|
/* FIXME
|
|
*
|
|
* If user selected large output size,
|
|
* and used it long time,
|
|
* mt9t112 camera will be very warm.
|
|
*
|
|
* But current driver can not stop mt9t112 camera.
|
|
* So, set small size here to solve this problem.
|
|
*/
|
|
mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
|
|
return ret;
|
|
}
|
|
|
|
if (!(priv->flags & INIT_DONE)) {
|
|
u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE &
|
|
priv->info->flags) ? 0x0001 : 0x0000;
|
|
|
|
ECHECKER(ret, mt9t112_init_camera(client));
|
|
|
|
/* Invert PCLK (Data sampled on falling edge of pixclk) */
|
|
mt9t112_reg_write(ret, client, 0x3C20, param);
|
|
|
|
mdelay(5);
|
|
|
|
priv->flags |= INIT_DONE;
|
|
}
|
|
|
|
mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
|
|
mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
|
|
mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
|
|
|
|
mt9t112_set_a_frame_size(client,
|
|
priv->frame.width,
|
|
priv->frame.height);
|
|
|
|
ECHECKER(ret, mt9t112_auto_focus_trigger(client));
|
|
|
|
dev_dbg(&client->dev, "format : %d\n", priv->format->code);
|
|
dev_dbg(&client->dev, "size : %d x %d\n",
|
|
priv->frame.width,
|
|
priv->frame.height);
|
|
|
|
CLOCK_INFO(client, EXT_CLOCK);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt9t112_set_params(struct i2c_client *client, u32 width, u32 height,
|
|
enum v4l2_mbus_pixelcode code)
|
|
{
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
int i;
|
|
|
|
priv->format = NULL;
|
|
|
|
/*
|
|
* frame size check
|
|
*/
|
|
mt9t112_frame_check(&width, &height);
|
|
|
|
/*
|
|
* get color format
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
|
|
if (mt9t112_cfmts[i].code == code)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(mt9t112_cfmts))
|
|
return -EINVAL;
|
|
|
|
priv->frame.width = (u16)width;
|
|
priv->frame.height = (u16)height;
|
|
|
|
priv->format = mt9t112_cfmts + i;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
|
|
{
|
|
a->bounds.left = 0;
|
|
a->bounds.top = 0;
|
|
a->bounds.width = VGA_WIDTH;
|
|
a->bounds.height = VGA_HEIGHT;
|
|
a->defrect = a->bounds;
|
|
a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
|
|
a->pixelaspect.numerator = 1;
|
|
a->pixelaspect.denominator = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
|
|
{
|
|
a->c.left = 0;
|
|
a->c.top = 0;
|
|
a->c.width = VGA_WIDTH;
|
|
a->c.height = VGA_HEIGHT;
|
|
a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
struct v4l2_rect *rect = &a->c;
|
|
|
|
return mt9t112_set_params(client, rect->width, rect->height,
|
|
V4L2_MBUS_FMT_YUYV8_2X8_BE);
|
|
}
|
|
|
|
static int mt9t112_g_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
|
|
if (!priv->format) {
|
|
int ret = mt9t112_set_params(client, VGA_WIDTH, VGA_HEIGHT,
|
|
V4L2_MBUS_FMT_YUYV8_2X8_BE);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
mf->width = priv->frame.width;
|
|
mf->height = priv->frame.height;
|
|
/* TODO: set colorspace */
|
|
mf->code = priv->format->code;
|
|
mf->field = V4L2_FIELD_NONE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_s_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
struct i2c_client *client = sd->priv;
|
|
|
|
/* TODO: set colorspace */
|
|
return mt9t112_set_params(client, mf->width, mf->height, mf->code);
|
|
}
|
|
|
|
static int mt9t112_try_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
mt9t112_frame_check(&mf->width, &mf->height);
|
|
|
|
/* TODO: set colorspace */
|
|
mf->field = V4L2_FIELD_NONE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
|
|
enum v4l2_mbus_pixelcode *code)
|
|
{
|
|
if (index >= ARRAY_SIZE(mt9t112_cfmts))
|
|
return -EINVAL;
|
|
|
|
*code = mt9t112_cfmts[index].code;
|
|
return 0;
|
|
}
|
|
|
|
static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
|
|
.s_stream = mt9t112_s_stream,
|
|
.g_mbus_fmt = mt9t112_g_fmt,
|
|
.s_mbus_fmt = mt9t112_s_fmt,
|
|
.try_mbus_fmt = mt9t112_try_fmt,
|
|
.cropcap = mt9t112_cropcap,
|
|
.g_crop = mt9t112_g_crop,
|
|
.s_crop = mt9t112_s_crop,
|
|
.enum_mbus_fmt = mt9t112_enum_fmt,
|
|
};
|
|
|
|
/************************************************************************
|
|
|
|
|
|
i2c driver
|
|
|
|
|
|
************************************************************************/
|
|
static struct v4l2_subdev_ops mt9t112_subdev_ops = {
|
|
.core = &mt9t112_subdev_core_ops,
|
|
.video = &mt9t112_subdev_video_ops,
|
|
};
|
|
|
|
static int mt9t112_camera_probe(struct soc_camera_device *icd,
|
|
struct i2c_client *client)
|
|
{
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
const char *devname;
|
|
int chipid;
|
|
|
|
/*
|
|
* We must have a parent by now. And it cannot be a wrong one.
|
|
* So this entire test is completely redundant.
|
|
*/
|
|
if (!icd->dev.parent ||
|
|
to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* check and show chip ID
|
|
*/
|
|
mt9t112_reg_read(chipid, client, 0x0000);
|
|
|
|
switch (chipid) {
|
|
case 0x2680:
|
|
devname = "mt9t111";
|
|
priv->model = V4L2_IDENT_MT9T111;
|
|
break;
|
|
case 0x2682:
|
|
devname = "mt9t112";
|
|
priv->model = V4L2_IDENT_MT9T112;
|
|
break;
|
|
default:
|
|
dev_err(&client->dev, "Product ID error %04x\n", chipid);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt9t112_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *did)
|
|
{
|
|
struct mt9t112_priv *priv;
|
|
struct soc_camera_device *icd = client->dev.platform_data;
|
|
struct soc_camera_link *icl;
|
|
int ret;
|
|
|
|
if (!icd) {
|
|
dev_err(&client->dev, "mt9t112: missing soc-camera data!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
icl = to_soc_camera_link(icd);
|
|
if (!icl || !icl->priv)
|
|
return -EINVAL;
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->info = icl->priv;
|
|
|
|
v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
|
|
|
|
icd->ops = &mt9t112_ops;
|
|
|
|
ret = mt9t112_camera_probe(icd, client);
|
|
if (ret) {
|
|
icd->ops = NULL;
|
|
kfree(priv);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt9t112_remove(struct i2c_client *client)
|
|
{
|
|
struct mt9t112_priv *priv = to_mt9t112(client);
|
|
struct soc_camera_device *icd = client->dev.platform_data;
|
|
|
|
icd->ops = NULL;
|
|
kfree(priv);
|
|
return 0;
|
|
}
|
|
|
|
static const struct i2c_device_id mt9t112_id[] = {
|
|
{ "mt9t112", 0 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, mt9t112_id);
|
|
|
|
static struct i2c_driver mt9t112_i2c_driver = {
|
|
.driver = {
|
|
.name = "mt9t112",
|
|
},
|
|
.probe = mt9t112_probe,
|
|
.remove = mt9t112_remove,
|
|
.id_table = mt9t112_id,
|
|
};
|
|
|
|
/************************************************************************
|
|
|
|
|
|
module function
|
|
|
|
|
|
************************************************************************/
|
|
static int __init mt9t112_module_init(void)
|
|
{
|
|
return i2c_add_driver(&mt9t112_i2c_driver);
|
|
}
|
|
|
|
static void __exit mt9t112_module_exit(void)
|
|
{
|
|
i2c_del_driver(&mt9t112_i2c_driver);
|
|
}
|
|
|
|
module_init(mt9t112_module_init);
|
|
module_exit(mt9t112_module_exit);
|
|
|
|
MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
|
|
MODULE_AUTHOR("Kuninori Morimoto");
|
|
MODULE_LICENSE("GPL v2");
|