mirror of https://gitee.com/openkylin/linux.git
318 lines
7.0 KiB
Plaintext
318 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Broadcom STB (bcm7445)";
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compatible = "brcm,bcm7445", "brcm,brcmstb";
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interrupt-parent = <&gic>;
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "brcm,brahma-b15";
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device_type = "cpu";
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enable-method = "brcm,brahma-b15";
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reg = <0>;
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};
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cpu@1 {
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compatible = "brcm,brahma-b15";
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device_type = "cpu";
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enable-method = "brcm,brahma-b15";
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reg = <1>;
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};
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cpu@2 {
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compatible = "brcm,brahma-b15";
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device_type = "cpu";
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enable-method = "brcm,brahma-b15";
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reg = <2>;
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};
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cpu@3 {
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compatible = "brcm,brahma-b15";
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device_type = "cpu";
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enable-method = "brcm,brahma-b15";
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reg = <3>;
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};
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};
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gic: interrupt-controller@ffd00000 {
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compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
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reg = <0x00 0xffd01000 0x00 0x1000>,
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<0x00 0xffd02000 0x00 0x2000>,
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<0x00 0xffd04000 0x00 0x2000>,
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<0x00 0xffd06000 0x00 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
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};
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rdb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x00 0xf0000000 0x1000000>;
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serial@40ab00 {
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compatible = "ns16550a";
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reg = <0x40ab00 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <81000000>;
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};
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sun_top_ctrl: syscon@404000 {
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compatible = "brcm,bcm7445-sun-top-ctrl",
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"syscon";
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reg = <0x404000 0x51c>;
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};
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hif_cpubiuctrl: syscon@3e2400 {
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compatible = "brcm,bcm7445-hif-cpubiuctrl",
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"syscon";
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reg = <0x3e2400 0x5b4>;
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};
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hif_continuation: syscon@452000 {
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compatible = "brcm,bcm7445-hif-continuation",
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"syscon";
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reg = <0x452000 0x100>;
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};
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irq0_intc: interrupt-controller@40a780 {
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compatible = "brcm,bcm7120-l2-intc";
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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reg = <0x40a780 0x8>;
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interrupt-controller;
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interrupts = <GIC_SPI 0x45 0x0>,
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<GIC_SPI 0x43 0x0>;
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brcm,int-map-mask = <0x25c>, <0x7000000>;
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brcm,int-fwd-mask = <0x70000>;
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};
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irq0_aon_intc: interrupt-controller@417280 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x417280 0x8>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_SPI 0x46 0x0>,
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<GIC_SPI 0x44 0x0>,
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<GIC_SPI 0x49 0x0>;
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brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
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brcm,int-fwd-mask = <0x0>;
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brcm,irq-can-wake;
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};
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hif_intr2_intc: interrupt-controller@3e1000 {
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compatible = "brcm,l2-intc";
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reg = <0x3e1000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 0x20 0x0>;
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interrupt-parent = <&gic>;
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interrupt-names = "hif";
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};
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aon_pm_l2_intc: interrupt-controller@410640 {
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compatible = "brcm,l2-intc";
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reg = <0x410640 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 0x40 0x0>;
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interrupt-parent = <&gic>;
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brcm,irq-can-wake;
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};
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aon-ctrl@410000 {
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compatible = "brcm,brcmstb-aon-ctrl";
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reg = <0x410000 0x200>, <0x410200 0x400>;
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reg-names = "aon-ctrl", "aon-sram";
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};
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nand: nand@3e2800 {
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
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reg-names = "nand", "flash-dma";
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reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
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interrupt-parent = <&hif_intr2_intc>;
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interrupts = <24>, <4>;
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interrupt-names = "nand_ctlrdy", "flash_dma_done";
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};
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sata@45a000 {
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compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
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reg-names = "ahci", "top-ctrl";
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reg = <0x45a000 0xa9c>, <0x458040 0x24>;
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interrupts = <GIC_SPI 30 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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sata0: sata-port@0 {
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reg = <0>;
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phys = <&sata_phy0>;
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};
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sata1: sata-port@1 {
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reg = <1>;
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phys = <&sata_phy1>;
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};
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};
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sata_phy: sata-phy@458100 {
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compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
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reg = <0x458100 0x1f00>;
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reg-names = "phy";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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sata_phy0: sata-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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sata_phy1: sata-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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upg_gio: gpio@40a700 {
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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reg = <0x40a700 0x80>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&irq0_intc>;
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interrupts = <6>;
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brcm,gpio-bank-widths = <32 32 32 24>;
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};
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upg_gio_aon: gpio@4172c0 {
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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reg = <0x4172c0 0x40>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupts-extended = <&irq0_aon_intc 0x6>,
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<&aon_pm_l2_intc 0x5>;
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wakeup-source;
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brcm,gpio-bank-widths = <18 4>;
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};
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};
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memory_controllers {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xf1100000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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memc@0 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x80000>;
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memc-ddr@2000 {
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compatible = "brcm,brcmstb-memc-ddr";
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reg = <0x2000 0x800>;
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};
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ddr-phy@6000 {
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compatible = "brcm,brcmstb-ddr-phy-v240.1";
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reg = <0x6000 0x21c>;
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};
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shimphy@8000 {
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
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reg = <0x8000 0xe4>;
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};
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};
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memc@1 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000 0x80000>;
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memc-ddr@2000 {
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compatible = "brcm,brcmstb-memc-ddr";
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reg = <0x2000 0x800>;
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};
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ddr-phy@6000 {
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compatible = "brcm,brcmstb-ddr-phy-v240.1";
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reg = <0x6000 0x21c>;
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};
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shimphy@8000 {
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
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reg = <0x8000 0xe4>;
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};
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};
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memc@2 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x100000 0x80000>;
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memc-ddr@2000 {
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compatible = "brcm,brcmstb-memc-ddr";
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reg = <0x2000 0x800>;
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};
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ddr-phy@6000 {
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compatible = "brcm,brcmstb-ddr-phy-v240.1";
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reg = <0x6000 0x21c>;
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};
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shimphy@8000 {
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
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reg = <0x8000 0xe4>;
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};
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};
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};
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sram@ffe00000 {
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compatible = "brcm,boot-sram", "mmio-sram";
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reg = <0x0 0xffe00000 0x0 0x10000>;
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};
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smpboot {
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compatible = "brcm,brcmstb-smpboot";
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syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
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syscon-cont = <&hif_continuation>;
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};
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reboot {
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compatible = "brcm,brcmstb-reboot";
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syscon = <&sun_top_ctrl 0x304 0x308>;
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};
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};
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