mirror of https://gitee.com/openkylin/linux.git
960 lines
24 KiB
C
960 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
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*
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* Copyright (C) 2013 ARM Limited
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* Copyright (C) 2017 Red Hat
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*/
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#include <linux/atomic.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/io-pgtable.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/kconfig.h>
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#include <linux/init.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_iommu.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/qcom_scm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "arm-smmu.h"
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#define SMMU_INTR_SEL_NS 0x2000
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struct qcom_iommu_ctx;
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struct qcom_iommu_dev {
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/* IOMMU core code handle */
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struct iommu_device iommu;
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struct device *dev;
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struct clk *iface_clk;
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struct clk *bus_clk;
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void __iomem *local_base;
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u32 sec_id;
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u8 num_ctxs;
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struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
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};
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struct qcom_iommu_ctx {
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struct device *dev;
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void __iomem *base;
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bool secure_init;
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u8 asid; /* asid and ctx bank # are 1:1 */
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struct iommu_domain *domain;
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};
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struct qcom_iommu_domain {
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struct io_pgtable_ops *pgtbl_ops;
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spinlock_t pgtbl_lock;
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struct mutex init_mutex; /* Protects iommu pointer */
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struct iommu_domain domain;
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struct qcom_iommu_dev *iommu;
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};
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static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct qcom_iommu_domain, domain);
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}
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static const struct iommu_ops qcom_iommu_ops;
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static struct qcom_iommu_dev * to_iommu(struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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if (!fwspec || fwspec->ops != &qcom_iommu_ops)
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return NULL;
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return dev_iommu_priv_get(dev);
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}
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static struct qcom_iommu_ctx * to_ctx(struct device *dev, unsigned asid)
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{
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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if (!qcom_iommu)
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return NULL;
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return qcom_iommu->ctxs[asid - 1];
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}
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static inline void
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iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
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{
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writel_relaxed(val, ctx->base + reg);
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}
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static inline void
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iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
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{
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writeq_relaxed(val, ctx->base + reg);
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}
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static inline u32
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iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
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{
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return readl_relaxed(ctx->base + reg);
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}
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static inline u64
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iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
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{
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return readq_relaxed(ctx->base + reg);
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}
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static void qcom_iommu_tlb_sync(void *cookie)
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{
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struct iommu_fwspec *fwspec;
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struct device *dev = cookie;
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unsigned i;
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fwspec = dev_iommu_fwspec_get(dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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unsigned int val, ret;
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iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
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ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
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(val & 0x1) == 0, 0, 5000000);
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if (ret)
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dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
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}
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}
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static void qcom_iommu_tlb_inv_context(void *cookie)
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{
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struct device *dev = cookie;
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struct iommu_fwspec *fwspec;
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unsigned i;
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fwspec = dev_iommu_fwspec_get(dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
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}
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qcom_iommu_tlb_sync(cookie);
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}
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static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
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size_t granule, bool leaf, void *cookie)
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{
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struct device *dev = cookie;
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struct iommu_fwspec *fwspec;
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unsigned i, reg;
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reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
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fwspec = dev_iommu_fwspec_get(dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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size_t s = size;
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iova = (iova >> 12) << 12;
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iova |= ctx->asid;
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do {
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iommu_writel(ctx, reg, iova);
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iova += granule;
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} while (s -= granule);
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}
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}
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static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size,
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size_t granule, void *cookie)
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{
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qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie);
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qcom_iommu_tlb_sync(cookie);
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}
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static void qcom_iommu_tlb_flush_leaf(unsigned long iova, size_t size,
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size_t granule, void *cookie)
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{
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qcom_iommu_tlb_inv_range_nosync(iova, size, granule, true, cookie);
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qcom_iommu_tlb_sync(cookie);
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}
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static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
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unsigned long iova, size_t granule,
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void *cookie)
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{
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qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie);
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}
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static const struct iommu_flush_ops qcom_flush_ops = {
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.tlb_flush_all = qcom_iommu_tlb_inv_context,
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.tlb_flush_walk = qcom_iommu_tlb_flush_walk,
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.tlb_flush_leaf = qcom_iommu_tlb_flush_leaf,
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.tlb_add_page = qcom_iommu_tlb_add_page,
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};
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static irqreturn_t qcom_iommu_fault(int irq, void *dev)
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{
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struct qcom_iommu_ctx *ctx = dev;
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u32 fsr, fsynr;
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u64 iova;
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fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
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if (!(fsr & ARM_SMMU_FSR_FAULT))
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return IRQ_NONE;
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fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
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iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
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if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
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dev_err_ratelimited(ctx->dev,
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"Unhandled context fault: fsr=0x%x, "
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"iova=0x%016llx, fsynr=0x%x, cb=%d\n",
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fsr, iova, fsynr, ctx->asid);
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}
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iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
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iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
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return IRQ_HANDLED;
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}
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static int qcom_iommu_init_domain(struct iommu_domain *domain,
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struct qcom_iommu_dev *qcom_iommu,
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struct device *dev)
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{
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct io_pgtable_ops *pgtbl_ops;
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struct io_pgtable_cfg pgtbl_cfg;
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int i, ret = 0;
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u32 reg;
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mutex_lock(&qcom_domain->init_mutex);
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if (qcom_domain->iommu)
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goto out_unlock;
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pgtbl_cfg = (struct io_pgtable_cfg) {
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.pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
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.ias = 32,
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.oas = 40,
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.tlb = &qcom_flush_ops,
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.iommu_dev = qcom_iommu->dev,
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};
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qcom_domain->iommu = qcom_iommu;
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pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, dev);
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if (!pgtbl_ops) {
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dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
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ret = -ENOMEM;
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goto out_clear_iommu;
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}
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/* Update the domain's page sizes to reflect the page table format */
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domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
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domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
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domain->geometry.force_aperture = true;
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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if (!ctx->secure_init) {
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ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
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if (ret) {
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dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
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goto out_clear_iommu;
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}
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ctx->secure_init = true;
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}
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/* TTBRs */
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iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
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pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
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FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
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iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
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/* TCR */
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iommu_writel(ctx, ARM_SMMU_CB_TCR2,
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arm_smmu_lpae_tcr2(&pgtbl_cfg));
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iommu_writel(ctx, ARM_SMMU_CB_TCR,
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arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
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/* MAIRs (stage-1 only) */
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iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
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pgtbl_cfg.arm_lpae_s1_cfg.mair);
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iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
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pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
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/* SCTLR */
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reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
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ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE |
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ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE |
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ARM_SMMU_SCTLR_CFCFG;
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if (IS_ENABLED(CONFIG_BIG_ENDIAN))
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reg |= ARM_SMMU_SCTLR_E;
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iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
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ctx->domain = domain;
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}
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mutex_unlock(&qcom_domain->init_mutex);
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/* Publish page table ops for map/unmap */
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qcom_domain->pgtbl_ops = pgtbl_ops;
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return 0;
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out_clear_iommu:
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qcom_domain->iommu = NULL;
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out_unlock:
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mutex_unlock(&qcom_domain->init_mutex);
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return ret;
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}
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static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
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{
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struct qcom_iommu_domain *qcom_domain;
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if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
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return NULL;
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/*
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* Allocate the domain and initialise some of its data structures.
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* We can't really do anything meaningful until we've added a
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* master.
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*/
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qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
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if (!qcom_domain)
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return NULL;
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if (type == IOMMU_DOMAIN_DMA &&
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iommu_get_dma_cookie(&qcom_domain->domain)) {
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kfree(qcom_domain);
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return NULL;
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}
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mutex_init(&qcom_domain->init_mutex);
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spin_lock_init(&qcom_domain->pgtbl_lock);
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return &qcom_domain->domain;
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}
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static void qcom_iommu_domain_free(struct iommu_domain *domain)
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{
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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iommu_put_dma_cookie(domain);
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if (qcom_domain->iommu) {
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/*
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* NOTE: unmap can be called after client device is powered
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* off, for example, with GPUs or anything involving dma-buf.
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* So we cannot rely on the device_link. Make sure the IOMMU
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* is on to avoid unclocked accesses in the TLB inv path:
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*/
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pm_runtime_get_sync(qcom_domain->iommu->dev);
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free_io_pgtable_ops(qcom_domain->pgtbl_ops);
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pm_runtime_put_sync(qcom_domain->iommu->dev);
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}
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kfree(qcom_domain);
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}
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static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
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{
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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int ret;
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if (!qcom_iommu) {
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dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
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return -ENXIO;
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}
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/* Ensure that the domain is finalized */
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pm_runtime_get_sync(qcom_iommu->dev);
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ret = qcom_iommu_init_domain(domain, qcom_iommu, dev);
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pm_runtime_put_sync(qcom_iommu->dev);
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if (ret < 0)
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return ret;
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/*
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* Sanity check the domain. We don't support domains across
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* different IOMMUs.
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*/
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if (qcom_domain->iommu != qcom_iommu) {
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dev_err(dev, "cannot attach to IOMMU %s while already "
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"attached to domain on IOMMU %s\n",
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dev_name(qcom_domain->iommu->dev),
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dev_name(qcom_iommu->dev));
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return -EINVAL;
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}
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return 0;
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}
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static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
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{
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
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unsigned i;
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if (WARN_ON(!qcom_domain->iommu))
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return;
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pm_runtime_get_sync(qcom_iommu->dev);
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for (i = 0; i < fwspec->num_ids; i++) {
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struct qcom_iommu_ctx *ctx = to_ctx(dev, fwspec->ids[i]);
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/* Disable the context bank: */
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iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
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ctx->domain = NULL;
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}
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pm_runtime_put_sync(qcom_iommu->dev);
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}
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static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
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{
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int ret;
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unsigned long flags;
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
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if (!ops)
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return -ENODEV;
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spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
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ret = ops->map(ops, iova, paddr, size, prot);
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spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
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return ret;
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}
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static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t size, struct iommu_iotlb_gather *gather)
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{
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size_t ret;
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unsigned long flags;
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struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
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struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
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if (!ops)
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return 0;
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/* NOTE: unmap can be called after client device is powered off,
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* for example, with GPUs or anything involving dma-buf. So we
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* cannot rely on the device_link. Make sure the IOMMU is on to
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* avoid unclocked accesses in the TLB inv path:
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*/
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pm_runtime_get_sync(qcom_domain->iommu->dev);
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spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
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ret = ops->unmap(ops, iova, size, gather);
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spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
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pm_runtime_put_sync(qcom_domain->iommu->dev);
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|
return ret;
|
|
}
|
|
|
|
static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
|
|
{
|
|
struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
|
|
struct io_pgtable, ops);
|
|
if (!qcom_domain->pgtbl_ops)
|
|
return;
|
|
|
|
pm_runtime_get_sync(qcom_domain->iommu->dev);
|
|
qcom_iommu_tlb_sync(pgtable->cookie);
|
|
pm_runtime_put_sync(qcom_domain->iommu->dev);
|
|
}
|
|
|
|
static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
|
|
struct iommu_iotlb_gather *gather)
|
|
{
|
|
qcom_iommu_flush_iotlb_all(domain);
|
|
}
|
|
|
|
static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
phys_addr_t ret;
|
|
unsigned long flags;
|
|
struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
|
|
|
|
if (!ops)
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
|
|
ret = ops->iova_to_phys(ops, iova);
|
|
spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool qcom_iommu_capable(enum iommu_cap cap)
|
|
{
|
|
switch (cap) {
|
|
case IOMMU_CAP_CACHE_COHERENCY:
|
|
/*
|
|
* Return true here as the SMMU can always send out coherent
|
|
* requests.
|
|
*/
|
|
return true;
|
|
case IOMMU_CAP_NOEXEC:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int qcom_iommu_add_device(struct device *dev)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
|
|
struct iommu_group *group;
|
|
struct device_link *link;
|
|
|
|
if (!qcom_iommu)
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* Establish the link between iommu and master, so that the
|
|
* iommu gets runtime enabled/disabled as per the master's
|
|
* needs.
|
|
*/
|
|
link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
|
|
if (!link) {
|
|
dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
|
|
dev_name(qcom_iommu->dev), dev_name(dev));
|
|
return -ENODEV;
|
|
}
|
|
|
|
group = iommu_group_get_for_dev(dev);
|
|
if (IS_ERR(group))
|
|
return PTR_ERR(group);
|
|
|
|
iommu_group_put(group);
|
|
iommu_device_link(&qcom_iommu->iommu, dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_iommu_remove_device(struct device *dev)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
|
|
|
|
if (!qcom_iommu)
|
|
return;
|
|
|
|
iommu_device_unlink(&qcom_iommu->iommu, dev);
|
|
iommu_group_remove_device(dev);
|
|
iommu_fwspec_free(dev);
|
|
}
|
|
|
|
static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu;
|
|
struct platform_device *iommu_pdev;
|
|
unsigned asid = args->args[0];
|
|
|
|
if (args->args_count != 1) {
|
|
dev_err(dev, "incorrect number of iommu params found for %s "
|
|
"(found %d, expected 1)\n",
|
|
args->np->full_name, args->args_count);
|
|
return -EINVAL;
|
|
}
|
|
|
|
iommu_pdev = of_find_device_by_node(args->np);
|
|
if (WARN_ON(!iommu_pdev))
|
|
return -EINVAL;
|
|
|
|
qcom_iommu = platform_get_drvdata(iommu_pdev);
|
|
|
|
/* make sure the asid specified in dt is valid, so we don't have
|
|
* to sanity check this elsewhere, since 'asid - 1' is used to
|
|
* index into qcom_iommu->ctxs:
|
|
*/
|
|
if (WARN_ON(asid < 1) ||
|
|
WARN_ON(asid > qcom_iommu->num_ctxs))
|
|
return -EINVAL;
|
|
|
|
if (!dev_iommu_priv_get(dev)) {
|
|
dev_iommu_priv_set(dev, qcom_iommu);
|
|
} else {
|
|
/* make sure devices iommus dt node isn't referring to
|
|
* multiple different iommu devices. Multiple context
|
|
* banks are ok, but multiple devices are not:
|
|
*/
|
|
if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev)))
|
|
return -EINVAL;
|
|
}
|
|
|
|
return iommu_fwspec_add_ids(dev, &asid, 1);
|
|
}
|
|
|
|
static const struct iommu_ops qcom_iommu_ops = {
|
|
.capable = qcom_iommu_capable,
|
|
.domain_alloc = qcom_iommu_domain_alloc,
|
|
.domain_free = qcom_iommu_domain_free,
|
|
.attach_dev = qcom_iommu_attach_dev,
|
|
.detach_dev = qcom_iommu_detach_dev,
|
|
.map = qcom_iommu_map,
|
|
.unmap = qcom_iommu_unmap,
|
|
.flush_iotlb_all = qcom_iommu_flush_iotlb_all,
|
|
.iotlb_sync = qcom_iommu_iotlb_sync,
|
|
.iova_to_phys = qcom_iommu_iova_to_phys,
|
|
.add_device = qcom_iommu_add_device,
|
|
.remove_device = qcom_iommu_remove_device,
|
|
.device_group = generic_device_group,
|
|
.of_xlate = qcom_iommu_of_xlate,
|
|
.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
|
|
};
|
|
|
|
static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(qcom_iommu->iface_clk);
|
|
if (ret) {
|
|
dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(qcom_iommu->bus_clk);
|
|
if (ret) {
|
|
dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n");
|
|
clk_disable_unprepare(qcom_iommu->iface_clk);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
|
|
{
|
|
clk_disable_unprepare(qcom_iommu->bus_clk);
|
|
clk_disable_unprepare(qcom_iommu->iface_clk);
|
|
}
|
|
|
|
static int qcom_iommu_sec_ptbl_init(struct device *dev)
|
|
{
|
|
size_t psize = 0;
|
|
unsigned int spare = 0;
|
|
void *cpu_addr;
|
|
dma_addr_t paddr;
|
|
unsigned long attrs;
|
|
static bool allocated = false;
|
|
int ret;
|
|
|
|
if (allocated)
|
|
return 0;
|
|
|
|
ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
|
|
|
|
attrs = DMA_ATTR_NO_KERNEL_MAPPING;
|
|
|
|
cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
|
|
if (!cpu_addr) {
|
|
dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
|
|
psize);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
|
|
if (ret) {
|
|
dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
|
|
goto free_mem;
|
|
}
|
|
|
|
allocated = true;
|
|
return 0;
|
|
|
|
free_mem:
|
|
dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
|
|
return ret;
|
|
}
|
|
|
|
static int get_asid(const struct device_node *np)
|
|
{
|
|
u32 reg;
|
|
|
|
/* read the "reg" property directly to get the relative address
|
|
* of the context bank, and calculate the asid from that:
|
|
*/
|
|
if (of_property_read_u32_index(np, "reg", 0, ®))
|
|
return -ENODEV;
|
|
|
|
return reg / 0x1000; /* context banks are 0x1000 apart */
|
|
}
|
|
|
|
static int qcom_iommu_ctx_probe(struct platform_device *pdev)
|
|
{
|
|
struct qcom_iommu_ctx *ctx;
|
|
struct device *dev = &pdev->dev;
|
|
struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
|
|
struct resource *res;
|
|
int ret, irq;
|
|
|
|
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
|
if (!ctx)
|
|
return -ENOMEM;
|
|
|
|
ctx->dev = dev;
|
|
platform_set_drvdata(pdev, ctx);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
ctx->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(ctx->base))
|
|
return PTR_ERR(ctx->base);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return -ENODEV;
|
|
|
|
/* clear IRQs before registering fault handler, just in case the
|
|
* boot-loader left us a surprise:
|
|
*/
|
|
iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
|
|
|
|
ret = devm_request_irq(dev, irq,
|
|
qcom_iommu_fault,
|
|
IRQF_SHARED,
|
|
"qcom-iommu-fault",
|
|
ctx);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request IRQ %u\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
ret = get_asid(dev->of_node);
|
|
if (ret < 0) {
|
|
dev_err(dev, "missing reg property\n");
|
|
return ret;
|
|
}
|
|
|
|
ctx->asid = ret;
|
|
|
|
dev_dbg(dev, "found asid %u\n", ctx->asid);
|
|
|
|
qcom_iommu->ctxs[ctx->asid - 1] = ctx;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qcom_iommu_ctx_remove(struct platform_device *pdev)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
|
|
struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
qcom_iommu->ctxs[ctx->asid - 1] = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ctx_of_match[] = {
|
|
{ .compatible = "qcom,msm-iommu-v1-ns" },
|
|
{ .compatible = "qcom,msm-iommu-v1-sec" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static struct platform_driver qcom_iommu_ctx_driver = {
|
|
.driver = {
|
|
.name = "qcom-iommu-ctx",
|
|
.of_match_table = of_match_ptr(ctx_of_match),
|
|
},
|
|
.probe = qcom_iommu_ctx_probe,
|
|
.remove = qcom_iommu_ctx_remove,
|
|
};
|
|
|
|
static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
|
|
{
|
|
struct device_node *child;
|
|
|
|
for_each_child_of_node(qcom_iommu->dev->of_node, child)
|
|
if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec"))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int qcom_iommu_device_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *child;
|
|
struct qcom_iommu_dev *qcom_iommu;
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
int ret, max_asid = 0;
|
|
|
|
/* find the max asid (which is 1:1 to ctx bank idx), so we know how
|
|
* many child ctx devices we have:
|
|
*/
|
|
for_each_child_of_node(dev->of_node, child)
|
|
max_asid = max(max_asid, get_asid(child));
|
|
|
|
qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid),
|
|
GFP_KERNEL);
|
|
if (!qcom_iommu)
|
|
return -ENOMEM;
|
|
qcom_iommu->num_ctxs = max_asid;
|
|
qcom_iommu->dev = dev;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (res)
|
|
qcom_iommu->local_base = devm_ioremap_resource(dev, res);
|
|
|
|
qcom_iommu->iface_clk = devm_clk_get(dev, "iface");
|
|
if (IS_ERR(qcom_iommu->iface_clk)) {
|
|
dev_err(dev, "failed to get iface clock\n");
|
|
return PTR_ERR(qcom_iommu->iface_clk);
|
|
}
|
|
|
|
qcom_iommu->bus_clk = devm_clk_get(dev, "bus");
|
|
if (IS_ERR(qcom_iommu->bus_clk)) {
|
|
dev_err(dev, "failed to get bus clock\n");
|
|
return PTR_ERR(qcom_iommu->bus_clk);
|
|
}
|
|
|
|
if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
|
|
&qcom_iommu->sec_id)) {
|
|
dev_err(dev, "missing qcom,iommu-secure-id property\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (qcom_iommu_has_secure_context(qcom_iommu)) {
|
|
ret = qcom_iommu_sec_ptbl_init(dev);
|
|
if (ret) {
|
|
dev_err(dev, "cannot init secure pg table(%d)\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
platform_set_drvdata(pdev, qcom_iommu);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
/* register context bank devices, which are child nodes: */
|
|
ret = devm_of_platform_populate(dev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to populate iommu contexts\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
|
|
dev_name(dev));
|
|
if (ret) {
|
|
dev_err(dev, "Failed to register iommu in sysfs\n");
|
|
return ret;
|
|
}
|
|
|
|
iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops);
|
|
iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode);
|
|
|
|
ret = iommu_device_register(&qcom_iommu->iommu);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to register iommu\n");
|
|
return ret;
|
|
}
|
|
|
|
bus_set_iommu(&platform_bus_type, &qcom_iommu_ops);
|
|
|
|
if (qcom_iommu->local_base) {
|
|
pm_runtime_get_sync(dev);
|
|
writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
|
|
pm_runtime_put_sync(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qcom_iommu_device_remove(struct platform_device *pdev)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
|
|
|
|
bus_set_iommu(&platform_bus_type, NULL);
|
|
|
|
pm_runtime_force_suspend(&pdev->dev);
|
|
platform_set_drvdata(pdev, NULL);
|
|
iommu_device_sysfs_remove(&qcom_iommu->iommu);
|
|
iommu_device_unregister(&qcom_iommu->iommu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qcom_iommu_resume(struct device *dev)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
|
|
|
|
return qcom_iommu_enable_clocks(qcom_iommu);
|
|
}
|
|
|
|
static int __maybe_unused qcom_iommu_suspend(struct device *dev)
|
|
{
|
|
struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
|
|
|
|
qcom_iommu_disable_clocks(qcom_iommu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops qcom_iommu_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static const struct of_device_id qcom_iommu_of_match[] = {
|
|
{ .compatible = "qcom,msm-iommu-v1" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static struct platform_driver qcom_iommu_driver = {
|
|
.driver = {
|
|
.name = "qcom-iommu",
|
|
.of_match_table = of_match_ptr(qcom_iommu_of_match),
|
|
.pm = &qcom_iommu_pm_ops,
|
|
},
|
|
.probe = qcom_iommu_device_probe,
|
|
.remove = qcom_iommu_device_remove,
|
|
};
|
|
|
|
static int __init qcom_iommu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&qcom_iommu_ctx_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&qcom_iommu_driver);
|
|
if (ret)
|
|
platform_driver_unregister(&qcom_iommu_ctx_driver);
|
|
|
|
return ret;
|
|
}
|
|
device_initcall(qcom_iommu_init);
|