mirror of https://gitee.com/openkylin/linux.git
1021 lines
27 KiB
C
1021 lines
27 KiB
C
/*
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* drivers/net/phy/micrel.c
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*
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* Driver for Micrel PHYs
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*
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* Author: David J. Choi
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*
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* Copyright (c) 2010-2013 Micrel, Inc.
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* Copyright (c) 2014 Johan Hovold <johan@kernel.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Support : Micrel Phys:
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* Giga phys: ksz9021, ksz9031
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* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
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* ksz8021, ksz8031, ksz8051,
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* ksz8081, ksz8091,
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* ksz8061,
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* Switch : ksz8873, ksz886x
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/micrel_phy.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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/* Operation Mode Strap Override */
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#define MII_KSZPHY_OMSO 0x16
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#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
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#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
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#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
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#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
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/* general Interrupt control/status reg in vendor specific block. */
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#define MII_KSZPHY_INTCS 0x1B
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#define KSZPHY_INTCS_JABBER BIT(15)
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#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
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#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
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#define KSZPHY_INTCS_PARELLEL BIT(12)
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#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
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#define KSZPHY_INTCS_LINK_DOWN BIT(10)
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#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
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#define KSZPHY_INTCS_LINK_UP BIT(8)
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#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
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KSZPHY_INTCS_LINK_DOWN)
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/* PHY Control 1 */
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#define MII_KSZPHY_CTRL_1 0x1e
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/* PHY Control 2 / PHY Control (if no PHY Control 1) */
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#define MII_KSZPHY_CTRL_2 0x1f
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#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
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/* bitmap of PHY register to set interrupt mode */
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#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
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#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
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/* Write/read to/from extended registers */
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#define MII_KSZPHY_EXTREG 0x0b
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#define KSZPHY_EXTREG_WRITE 0x8000
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#define MII_KSZPHY_EXTREG_WRITE 0x0c
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#define MII_KSZPHY_EXTREG_READ 0x0d
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/* Extended registers */
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#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
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#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
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#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
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#define PS_TO_REG 200
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struct kszphy_hw_stat {
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const char *string;
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u8 reg;
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u8 bits;
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};
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static struct kszphy_hw_stat kszphy_hw_stats[] = {
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{ "phy_receive_errors", 21, 16},
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{ "phy_idle_errors", 10, 8 },
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};
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struct kszphy_type {
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u32 led_mode_reg;
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u16 interrupt_level_mask;
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bool has_broadcast_disable;
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bool has_nand_tree_disable;
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bool has_rmii_ref_clk_sel;
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};
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struct kszphy_priv {
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const struct kszphy_type *type;
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int led_mode;
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bool rmii_ref_clk_sel;
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bool rmii_ref_clk_sel_val;
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u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
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};
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static const struct kszphy_type ksz8021_type = {
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.led_mode_reg = MII_KSZPHY_CTRL_2,
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.has_broadcast_disable = true,
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.has_nand_tree_disable = true,
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.has_rmii_ref_clk_sel = true,
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};
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static const struct kszphy_type ksz8041_type = {
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.led_mode_reg = MII_KSZPHY_CTRL_1,
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};
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static const struct kszphy_type ksz8051_type = {
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.led_mode_reg = MII_KSZPHY_CTRL_2,
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.has_nand_tree_disable = true,
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};
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static const struct kszphy_type ksz8081_type = {
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.led_mode_reg = MII_KSZPHY_CTRL_2,
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.has_broadcast_disable = true,
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.has_nand_tree_disable = true,
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.has_rmii_ref_clk_sel = true,
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};
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static const struct kszphy_type ks8737_type = {
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.interrupt_level_mask = BIT(14),
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};
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static const struct kszphy_type ksz9021_type = {
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.interrupt_level_mask = BIT(14),
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};
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static int kszphy_extended_write(struct phy_device *phydev,
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u32 regnum, u16 val)
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{
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phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
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return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
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}
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static int kszphy_extended_read(struct phy_device *phydev,
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u32 regnum)
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{
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phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
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return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
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}
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static int kszphy_ack_interrupt(struct phy_device *phydev)
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{
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/* bit[7..0] int status, which is a read and clear register. */
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int rc;
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rc = phy_read(phydev, MII_KSZPHY_INTCS);
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return (rc < 0) ? rc : 0;
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}
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static int kszphy_config_intr(struct phy_device *phydev)
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{
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const struct kszphy_type *type = phydev->drv->driver_data;
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int temp;
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u16 mask;
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if (type && type->interrupt_level_mask)
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mask = type->interrupt_level_mask;
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else
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mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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if (temp < 0)
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return temp;
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temp &= ~mask;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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/* enable / disable interrupts */
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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temp = KSZPHY_INTCS_ALL;
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else
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temp = 0;
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return phy_write(phydev, MII_KSZPHY_INTCS, temp);
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}
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static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
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{
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int ctrl;
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ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
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if (ctrl < 0)
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return ctrl;
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if (val)
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ctrl |= KSZPHY_RMII_REF_CLK_SEL;
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else
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ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
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return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
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}
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static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
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{
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int rc, temp, shift;
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switch (reg) {
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case MII_KSZPHY_CTRL_1:
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shift = 14;
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break;
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case MII_KSZPHY_CTRL_2:
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shift = 4;
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break;
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default:
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return -EINVAL;
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}
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temp = phy_read(phydev, reg);
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if (temp < 0) {
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rc = temp;
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goto out;
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}
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temp &= ~(3 << shift);
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temp |= val << shift;
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rc = phy_write(phydev, reg, temp);
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out:
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if (rc < 0)
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phydev_err(phydev, "failed to set led mode\n");
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return rc;
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}
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/* Disable PHY address 0 as the broadcast address, so that it can be used as a
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* unique (non-broadcast) address on a shared bus.
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*/
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static int kszphy_broadcast_disable(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_KSZPHY_OMSO);
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if (ret < 0)
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goto out;
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ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
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out:
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if (ret)
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phydev_err(phydev, "failed to disable broadcast address\n");
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return ret;
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}
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static int kszphy_nand_tree_disable(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_KSZPHY_OMSO);
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if (ret < 0)
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goto out;
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if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
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return 0;
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ret = phy_write(phydev, MII_KSZPHY_OMSO,
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ret & ~KSZPHY_OMSO_NAND_TREE_ON);
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out:
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if (ret)
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phydev_err(phydev, "failed to disable NAND tree mode\n");
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return ret;
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}
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static int kszphy_config_init(struct phy_device *phydev)
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{
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struct kszphy_priv *priv = phydev->priv;
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const struct kszphy_type *type;
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int ret;
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if (!priv)
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return 0;
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type = priv->type;
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if (type->has_broadcast_disable)
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kszphy_broadcast_disable(phydev);
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if (type->has_nand_tree_disable)
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kszphy_nand_tree_disable(phydev);
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if (priv->rmii_ref_clk_sel) {
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ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
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if (ret) {
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phydev_err(phydev,
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"failed to set rmii reference clock\n");
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return ret;
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}
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}
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if (priv->led_mode >= 0)
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kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
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if (phy_interrupt_is_valid(phydev)) {
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int ctl = phy_read(phydev, MII_BMCR);
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if (ctl < 0)
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return ctl;
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ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int ksz8041_config_init(struct phy_device *phydev)
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{
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struct device_node *of_node = phydev->mdio.dev.of_node;
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/* Limit supported and advertised modes in fiber mode */
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if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
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phydev->dev_flags |= MICREL_PHY_FXEN;
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phydev->supported &= SUPPORTED_FIBRE |
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SUPPORTED_100baseT_Full |
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SUPPORTED_100baseT_Half;
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phydev->advertising &= ADVERTISED_FIBRE |
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ADVERTISED_100baseT_Full |
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ADVERTISED_100baseT_Half;
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phydev->autoneg = AUTONEG_DISABLE;
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}
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return kszphy_config_init(phydev);
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}
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static int ksz8041_config_aneg(struct phy_device *phydev)
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{
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/* Skip auto-negotiation in fiber mode */
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if (phydev->dev_flags & MICREL_PHY_FXEN) {
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phydev->speed = SPEED_100;
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return 0;
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}
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return genphy_config_aneg(phydev);
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}
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static int ksz9021_load_values_from_of(struct phy_device *phydev,
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const struct device_node *of_node,
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u16 reg,
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const char *field1, const char *field2,
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const char *field3, const char *field4)
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{
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int val1 = -1;
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int val2 = -2;
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int val3 = -3;
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int val4 = -4;
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int newval;
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int matches = 0;
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if (!of_property_read_u32(of_node, field1, &val1))
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matches++;
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if (!of_property_read_u32(of_node, field2, &val2))
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matches++;
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if (!of_property_read_u32(of_node, field3, &val3))
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matches++;
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if (!of_property_read_u32(of_node, field4, &val4))
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matches++;
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if (!matches)
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return 0;
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if (matches < 4)
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newval = kszphy_extended_read(phydev, reg);
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else
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newval = 0;
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if (val1 != -1)
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newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
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if (val2 != -2)
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newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
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if (val3 != -3)
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newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
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if (val4 != -4)
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newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
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return kszphy_extended_write(phydev, reg, newval);
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}
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static int ksz9021_config_init(struct phy_device *phydev)
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{
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const struct device *dev = &phydev->mdio.dev;
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const struct device_node *of_node = dev->of_node;
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const struct device *dev_walker;
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/* The Micrel driver has a deprecated option to place phy OF
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* properties in the MAC node. Walk up the tree of devices to
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* find a device with an OF node.
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*/
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dev_walker = &phydev->mdio.dev;
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do {
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of_node = dev_walker->of_node;
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dev_walker = dev_walker->parent;
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} while (!of_node && dev_walker);
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if (of_node) {
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
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"txen-skew-ps", "txc-skew-ps",
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"rxdv-skew-ps", "rxc-skew-ps");
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_RX_DATA_PAD_SKEW,
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"rxd0-skew-ps", "rxd1-skew-ps",
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"rxd2-skew-ps", "rxd3-skew-ps");
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_TX_DATA_PAD_SKEW,
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"txd0-skew-ps", "txd1-skew-ps",
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"txd2-skew-ps", "txd3-skew-ps");
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}
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return 0;
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}
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#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
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#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
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#define OP_DATA 1
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#define KSZ9031_PS_TO_REG 60
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/* Extended registers */
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/* MMD Address 0x0 */
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#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
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#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
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/* MMD Address 0x2 */
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#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
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#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
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#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
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#define MII_KSZ9031RN_CLK_PAD_SKEW 8
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static int ksz9031_extended_write(struct phy_device *phydev,
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u8 mode, u32 dev_addr, u32 regnum, u16 val)
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{
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
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phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
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return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
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}
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static int ksz9031_extended_read(struct phy_device *phydev,
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u8 mode, u32 dev_addr, u32 regnum)
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{
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
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phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
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return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
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}
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static int ksz9031_of_load_skew_values(struct phy_device *phydev,
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const struct device_node *of_node,
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u16 reg, size_t field_sz,
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const char *field[], u8 numfields)
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{
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int val[4] = {-1, -2, -3, -4};
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int matches = 0;
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u16 mask;
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u16 maxval;
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u16 newval;
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int i;
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for (i = 0; i < numfields; i++)
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if (!of_property_read_u32(of_node, field[i], val + i))
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matches++;
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if (!matches)
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return 0;
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if (matches < numfields)
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newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
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else
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newval = 0;
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maxval = (field_sz == 4) ? 0xf : 0x1f;
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for (i = 0; i < numfields; i++)
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if (val[i] != -(i + 1)) {
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mask = 0xffff;
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mask ^= maxval << (field_sz * i);
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newval = (newval & mask) |
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(((val[i] / KSZ9031_PS_TO_REG) & maxval)
|
|
<< (field_sz * i));
|
|
}
|
|
|
|
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
|
|
}
|
|
|
|
static int ksz9031_center_flp_timing(struct phy_device *phydev)
|
|
{
|
|
int result;
|
|
|
|
/* Center KSZ9031RNX FLP timing at 16ms. */
|
|
result = ksz9031_extended_write(phydev, OP_DATA, 0,
|
|
MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
|
|
result = ksz9031_extended_write(phydev, OP_DATA, 0,
|
|
MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
|
|
|
|
if (result)
|
|
return result;
|
|
|
|
return genphy_restart_aneg(phydev);
|
|
}
|
|
|
|
static int ksz9031_config_init(struct phy_device *phydev)
|
|
{
|
|
const struct device *dev = &phydev->mdio.dev;
|
|
const struct device_node *of_node = dev->of_node;
|
|
static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
|
|
static const char *rx_data_skews[4] = {
|
|
"rxd0-skew-ps", "rxd1-skew-ps",
|
|
"rxd2-skew-ps", "rxd3-skew-ps"
|
|
};
|
|
static const char *tx_data_skews[4] = {
|
|
"txd0-skew-ps", "txd1-skew-ps",
|
|
"txd2-skew-ps", "txd3-skew-ps"
|
|
};
|
|
static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
|
|
const struct device *dev_walker;
|
|
|
|
/* The Micrel driver has a deprecated option to place phy OF
|
|
* properties in the MAC node. Walk up the tree of devices to
|
|
* find a device with an OF node.
|
|
*/
|
|
dev_walker = &phydev->mdio.dev;
|
|
do {
|
|
of_node = dev_walker->of_node;
|
|
dev_walker = dev_walker->parent;
|
|
} while (!of_node && dev_walker);
|
|
|
|
if (of_node) {
|
|
ksz9031_of_load_skew_values(phydev, of_node,
|
|
MII_KSZ9031RN_CLK_PAD_SKEW, 5,
|
|
clk_skews, 2);
|
|
|
|
ksz9031_of_load_skew_values(phydev, of_node,
|
|
MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
|
|
control_skews, 2);
|
|
|
|
ksz9031_of_load_skew_values(phydev, of_node,
|
|
MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
|
|
rx_data_skews, 4);
|
|
|
|
ksz9031_of_load_skew_values(phydev, of_node,
|
|
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
|
|
tx_data_skews, 4);
|
|
}
|
|
|
|
return ksz9031_center_flp_timing(phydev);
|
|
}
|
|
|
|
#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
|
|
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
|
|
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
|
|
static int ksz8873mll_read_status(struct phy_device *phydev)
|
|
{
|
|
int regval;
|
|
|
|
/* dummy read */
|
|
regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
|
|
|
|
regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
|
|
|
|
if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
|
|
phydev->duplex = DUPLEX_HALF;
|
|
else
|
|
phydev->duplex = DUPLEX_FULL;
|
|
|
|
if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
|
|
phydev->speed = SPEED_10;
|
|
else
|
|
phydev->speed = SPEED_100;
|
|
|
|
phydev->link = 1;
|
|
phydev->pause = phydev->asym_pause = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ksz9031_read_status(struct phy_device *phydev)
|
|
{
|
|
int err;
|
|
int regval;
|
|
|
|
err = genphy_read_status(phydev);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Make sure the PHY is not broken. Read idle error count,
|
|
* and reset the PHY if it is maxed out.
|
|
*/
|
|
regval = phy_read(phydev, MII_STAT1000);
|
|
if ((regval & 0xFF) == 0xFF) {
|
|
phy_init_hw(phydev);
|
|
phydev->link = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ksz8873mll_config_aneg(struct phy_device *phydev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/* This routine returns -1 as an indication to the caller that the
|
|
* Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
|
|
* MMD extended PHY registers.
|
|
*/
|
|
static int
|
|
ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
|
|
int regnum)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
/* This routine does nothing since the Micrel ksz9021 does not support
|
|
* standard IEEE MMD extended PHY registers.
|
|
*/
|
|
static void
|
|
ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
|
|
int regnum, u32 val)
|
|
{
|
|
}
|
|
|
|
static int kszphy_get_sset_count(struct phy_device *phydev)
|
|
{
|
|
return ARRAY_SIZE(kszphy_hw_stats);
|
|
}
|
|
|
|
static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
|
|
memcpy(data + i * ETH_GSTRING_LEN,
|
|
kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
|
|
}
|
|
}
|
|
|
|
#ifndef UINT64_MAX
|
|
#define UINT64_MAX (u64)(~((u64)0))
|
|
#endif
|
|
static u64 kszphy_get_stat(struct phy_device *phydev, int i)
|
|
{
|
|
struct kszphy_hw_stat stat = kszphy_hw_stats[i];
|
|
struct kszphy_priv *priv = phydev->priv;
|
|
int val;
|
|
u64 ret;
|
|
|
|
val = phy_read(phydev, stat.reg);
|
|
if (val < 0) {
|
|
ret = UINT64_MAX;
|
|
} else {
|
|
val = val & ((1 << stat.bits) - 1);
|
|
priv->stats[i] += val;
|
|
ret = priv->stats[i];
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void kszphy_get_stats(struct phy_device *phydev,
|
|
struct ethtool_stats *stats, u64 *data)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
|
|
data[i] = kszphy_get_stat(phydev, i);
|
|
}
|
|
|
|
static int kszphy_suspend(struct phy_device *phydev)
|
|
{
|
|
/* Disable PHY Interrupts */
|
|
if (phy_interrupt_is_valid(phydev)) {
|
|
phydev->interrupts = PHY_INTERRUPT_DISABLED;
|
|
if (phydev->drv->config_intr)
|
|
phydev->drv->config_intr(phydev);
|
|
}
|
|
|
|
return genphy_suspend(phydev);
|
|
}
|
|
|
|
static int kszphy_resume(struct phy_device *phydev)
|
|
{
|
|
genphy_resume(phydev);
|
|
|
|
/* Enable PHY Interrupts */
|
|
if (phy_interrupt_is_valid(phydev)) {
|
|
phydev->interrupts = PHY_INTERRUPT_ENABLED;
|
|
if (phydev->drv->config_intr)
|
|
phydev->drv->config_intr(phydev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kszphy_probe(struct phy_device *phydev)
|
|
{
|
|
const struct kszphy_type *type = phydev->drv->driver_data;
|
|
const struct device_node *np = phydev->mdio.dev.of_node;
|
|
struct kszphy_priv *priv;
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
phydev->priv = priv;
|
|
|
|
priv->type = type;
|
|
|
|
if (type->led_mode_reg) {
|
|
ret = of_property_read_u32(np, "micrel,led-mode",
|
|
&priv->led_mode);
|
|
if (ret)
|
|
priv->led_mode = -1;
|
|
|
|
if (priv->led_mode > 3) {
|
|
phydev_err(phydev, "invalid led mode: 0x%02x\n",
|
|
priv->led_mode);
|
|
priv->led_mode = -1;
|
|
}
|
|
} else {
|
|
priv->led_mode = -1;
|
|
}
|
|
|
|
clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
|
|
/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
|
|
if (!IS_ERR_OR_NULL(clk)) {
|
|
unsigned long rate = clk_get_rate(clk);
|
|
bool rmii_ref_clk_sel_25_mhz;
|
|
|
|
priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
|
|
rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
|
|
"micrel,rmii-reference-clock-select-25-mhz");
|
|
|
|
if (rate > 24500000 && rate < 25500000) {
|
|
priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
|
|
} else if (rate > 49500000 && rate < 50500000) {
|
|
priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
|
|
} else {
|
|
phydev_err(phydev, "Clock rate out of range: %ld\n",
|
|
rate);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* Support legacy board-file configuration */
|
|
if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
|
|
priv->rmii_ref_clk_sel = true;
|
|
priv->rmii_ref_clk_sel_val = true;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver ksphy_driver[] = {
|
|
{
|
|
.phy_id = PHY_ID_KS8737,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KS8737",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ks8737_type,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8021,
|
|
.phy_id_mask = 0x00ffffff,
|
|
.name = "Micrel KSZ8021 or KSZ8031",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
|
|
SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8021_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8031,
|
|
.phy_id_mask = 0x00ffffff,
|
|
.name = "Micrel KSZ8031",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
|
|
SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8021_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8041,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KSZ8041",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
|
|
| SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8041_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = ksz8041_config_init,
|
|
.config_aneg = ksz8041_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8041RNLI,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KSZ8041RNLI",
|
|
.features = PHY_BASIC_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8041_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8051,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KSZ8051",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
|
|
| SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8051_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8001,
|
|
.name = "Micrel KSZ8001 or KS8721",
|
|
.phy_id_mask = 0x00fffffc,
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8041_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8081,
|
|
.name = "Micrel KSZ8081 or KSZ8091",
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz8081_type,
|
|
.probe = kszphy_probe,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = kszphy_suspend,
|
|
.resume = kszphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8061,
|
|
.name = "Micrel KSZ8061",
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ9021,
|
|
.phy_id_mask = 0x000ffffe,
|
|
.name = "Micrel KSZ9021 Gigabit PHY",
|
|
.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz9021_type,
|
|
.config_init = ksz9021_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.read_mmd_indirect = ksz9021_rd_mmd_phyreg,
|
|
.write_mmd_indirect = ksz9021_wr_mmd_phyreg,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ9031,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KSZ9031 Gigabit PHY",
|
|
.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.driver_data = &ksz9021_type,
|
|
.config_init = ksz9031_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = ksz9031_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = kszphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8873MLL,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KSZ8873MLL Switch",
|
|
.features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = ksz8873mll_config_aneg,
|
|
.read_status = ksz8873mll_read_status,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ886X,
|
|
.phy_id_mask = MICREL_PHY_ID_MASK,
|
|
.name = "Micrel KSZ886X Switch",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.get_sset_count = kszphy_get_sset_count,
|
|
.get_strings = kszphy_get_strings,
|
|
.get_stats = kszphy_get_stats,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
} };
|
|
|
|
module_phy_driver(ksphy_driver);
|
|
|
|
MODULE_DESCRIPTION("Micrel PHY driver");
|
|
MODULE_AUTHOR("David J. Choi");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
static struct mdio_device_id __maybe_unused micrel_tbl[] = {
|
|
{ PHY_ID_KSZ9021, 0x000ffffe },
|
|
{ PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ8001, 0x00fffffc },
|
|
{ PHY_ID_KS8737, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ8021, 0x00ffffff },
|
|
{ PHY_ID_KSZ8031, 0x00ffffff },
|
|
{ PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
|
|
{ PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, micrel_tbl);
|