mirror of https://gitee.com/openkylin/linux.git
654 lines
18 KiB
C
654 lines
18 KiB
C
/* Intel(R) Gigabit Ethernet Linux driver
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* Copyright(c) 2007-2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*/
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/* Linux PRO/1000 Ethernet Driver main header file */
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#ifndef _IGB_H_
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#define _IGB_H_
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#include "e1000_mac.h"
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#include "e1000_82575.h"
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/bitops.h>
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#include <linux/if_vlan.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/pci.h>
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#include <linux/mdio.h>
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struct igb_adapter;
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#define E1000_PCS_CFG_IGN_SD 1
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/* Interrupt defines */
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#define IGB_START_ITR 648 /* ~6000 ints/sec */
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#define IGB_4K_ITR 980
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#define IGB_20K_ITR 196
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#define IGB_70K_ITR 56
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/* TX/RX descriptor defines */
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#define IGB_DEFAULT_TXD 256
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#define IGB_DEFAULT_TX_WORK 128
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#define IGB_MIN_TXD 80
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#define IGB_MAX_TXD 4096
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#define IGB_DEFAULT_RXD 256
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#define IGB_MIN_RXD 80
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#define IGB_MAX_RXD 4096
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#define IGB_DEFAULT_ITR 3 /* dynamic */
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#define IGB_MAX_ITR_USECS 10000
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#define IGB_MIN_ITR_USECS 10
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#define NON_Q_VECTORS 1
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#define MAX_Q_VECTORS 8
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#define MAX_MSIX_ENTRIES 10
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/* Transmit and receive queues */
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#define IGB_MAX_RX_QUEUES 8
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#define IGB_MAX_RX_QUEUES_82575 4
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#define IGB_MAX_RX_QUEUES_I211 2
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#define IGB_MAX_TX_QUEUES 8
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#define IGB_MAX_VF_MC_ENTRIES 30
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#define IGB_MAX_VF_FUNCTIONS 8
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#define IGB_MAX_VFTA_ENTRIES 128
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#define IGB_82576_VF_DEV_ID 0x10CA
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#define IGB_I350_VF_DEV_ID 0x1520
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/* NVM version defines */
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#define IGB_MAJOR_MASK 0xF000
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#define IGB_MINOR_MASK 0x0FF0
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#define IGB_BUILD_MASK 0x000F
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#define IGB_COMB_VER_MASK 0x00FF
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#define IGB_MAJOR_SHIFT 12
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#define IGB_MINOR_SHIFT 4
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#define IGB_COMB_VER_SHFT 8
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#define IGB_NVM_VER_INVALID 0xFFFF
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#define IGB_ETRACK_SHIFT 16
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#define NVM_ETRACK_WORD 0x0042
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#define NVM_COMB_VER_OFF 0x0083
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#define NVM_COMB_VER_PTR 0x003d
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/* Transmit and receive latency (for PTP timestamps) */
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#define IGB_I210_TX_LATENCY_10 9542
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#define IGB_I210_TX_LATENCY_100 1024
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#define IGB_I210_TX_LATENCY_1000 178
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#define IGB_I210_RX_LATENCY_10 20662
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#define IGB_I210_RX_LATENCY_100 2213
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#define IGB_I210_RX_LATENCY_1000 448
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struct vf_data_storage {
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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u32 flags;
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unsigned long last_nack;
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u16 pf_vlan; /* When set, guest VLAN config not allowed. */
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u16 pf_qos;
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u16 tx_rate;
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bool spoofchk_enabled;
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};
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#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
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#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
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#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
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#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
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/* RX descriptor control thresholds.
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* PTHRESH - MAC will consider prefetch if it has fewer than this number of
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* descriptors available in its onboard memory.
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* Setting this to 0 disables RX descriptor prefetch.
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* HTHRESH - MAC will only prefetch if there are at least this many descriptors
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* available in host memory.
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* If PTHRESH is 0, this should also be 0.
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* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
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* descriptors until either it has this many to write back, or the
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* ITR timer expires.
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*/
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#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
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#define IGB_RX_HTHRESH 8
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#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
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#define IGB_TX_HTHRESH 1
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#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
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(adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
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#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
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(adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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/* Supported Rx Buffer Sizes */
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#define IGB_RXBUFFER_256 256
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#define IGB_RXBUFFER_2048 2048
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#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
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#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define AUTO_ALL_MODES 0
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#define IGB_EEPROM_APME 0x0400
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#ifndef IGB_MASTER_SLAVE
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/* Switch to override PHY master/slave setting */
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#define IGB_MASTER_SLAVE e1000_ms_hw_default
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#endif
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#define IGB_MNG_VLAN_NONE -1
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enum igb_tx_flags {
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/* cmd_type flags */
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IGB_TX_FLAGS_VLAN = 0x01,
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IGB_TX_FLAGS_TSO = 0x02,
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IGB_TX_FLAGS_TSTAMP = 0x04,
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/* olinfo flags */
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IGB_TX_FLAGS_IPV4 = 0x10,
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IGB_TX_FLAGS_CSUM = 0x20,
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};
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/* VLAN info */
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#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IGB_TX_FLAGS_VLAN_SHIFT 16
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/* The largest size we can write to the descriptor is 65535. In order to
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* maintain a power of two alignment we have to limit ourselves to 32K.
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*/
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#define IGB_MAX_TXD_PWR 15
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#define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
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/* Tx Descriptors needed, worst case */
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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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/* EEPROM byte offsets */
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#define IGB_SFF_8472_SWAP 0x5C
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#define IGB_SFF_8472_COMP 0x5E
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/* Bitmasks */
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#define IGB_SFF_ADDRESSING_MODE 0x4
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#define IGB_SFF_8472_UNSUP 0x00
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer
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*/
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struct igb_tx_buffer {
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union e1000_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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struct sk_buff *skb;
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unsigned int bytecount;
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u16 gso_segs;
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__be16 protocol;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 tx_flags;
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};
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struct igb_rx_buffer {
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dma_addr_t dma;
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struct page *page;
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unsigned int page_offset;
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};
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struct igb_tx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 restart_queue;
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u64 restart_queue2;
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};
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struct igb_rx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 drops;
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u64 csum_err;
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u64 alloc_failed;
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};
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struct igb_ring_container {
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struct igb_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u8 count; /* total number of rings in vector */
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u8 itr; /* current ITR setting for ring */
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};
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struct igb_ring {
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struct igb_q_vector *q_vector; /* backlink to q_vector */
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struct net_device *netdev; /* back pointer to net_device */
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struct device *dev; /* device pointer for dma mapping */
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union { /* array of buffer info structs */
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struct igb_tx_buffer *tx_buffer_info;
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struct igb_rx_buffer *rx_buffer_info;
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};
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void *desc; /* descriptor ring memory */
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unsigned long flags; /* ring specific flags */
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void __iomem *tail; /* pointer to ring tail register */
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dma_addr_t dma; /* phys address of the ring */
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unsigned int size; /* length of desc. ring in bytes */
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u16 count; /* number of desc. in the ring */
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u8 queue_index; /* logical index of the ring*/
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u8 reg_idx; /* physical index of the ring */
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/* everything past this point are written often */
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u16 next_to_clean;
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u16 next_to_use;
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u16 next_to_alloc;
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union {
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/* TX */
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struct {
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struct igb_tx_queue_stats tx_stats;
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struct u64_stats_sync tx_syncp;
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struct u64_stats_sync tx_syncp2;
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};
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/* RX */
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struct {
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struct sk_buff *skb;
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struct igb_rx_queue_stats rx_stats;
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struct u64_stats_sync rx_syncp;
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};
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};
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} ____cacheline_internodealigned_in_smp;
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struct igb_q_vector {
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struct igb_adapter *adapter; /* backlink */
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int cpu; /* CPU for DCA */
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u32 eims_value; /* EIMS mask value */
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u16 itr_val;
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u8 set_itr;
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void __iomem *itr_register;
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struct igb_ring_container rx, tx;
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struct napi_struct napi;
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struct rcu_head rcu; /* to avoid race with update stats on free */
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char name[IFNAMSIZ + 9];
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/* for dynamic allocation of rings associated with this q_vector */
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struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
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};
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enum e1000_ring_flags_t {
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IGB_RING_FLAG_RX_SCTP_CSUM,
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IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
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IGB_RING_FLAG_TX_CTX_IDX,
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IGB_RING_FLAG_TX_DETECT_HANG
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};
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#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
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#define IGB_RX_DESC(R, i) \
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(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
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#define IGB_TX_DESC(R, i) \
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(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
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#define IGB_TX_CTXTDESC(R, i) \
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(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
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/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
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static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
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const u32 stat_err_bits)
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{
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return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
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}
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/* igb_desc_unused - calculate if we have unused descriptors */
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static inline int igb_desc_unused(struct igb_ring *ring)
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{
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if (ring->next_to_clean > ring->next_to_use)
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return ring->next_to_clean - ring->next_to_use - 1;
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return ring->count + ring->next_to_clean - ring->next_to_use - 1;
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}
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#ifdef CONFIG_IGB_HWMON
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#define IGB_HWMON_TYPE_LOC 0
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#define IGB_HWMON_TYPE_TEMP 1
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#define IGB_HWMON_TYPE_CAUTION 2
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#define IGB_HWMON_TYPE_MAX 3
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struct hwmon_attr {
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struct device_attribute dev_attr;
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struct e1000_hw *hw;
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struct e1000_thermal_diode_data *sensor;
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char name[12];
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};
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struct hwmon_buff {
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struct attribute_group group;
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const struct attribute_group *groups[2];
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struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
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struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
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unsigned int n_hwmon;
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};
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#endif
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/* The number of L2 ether-type filter registers, Index 3 is reserved
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* for PTP 1588 timestamp
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*/
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#define MAX_ETYPE_FILTER (4 - 1)
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/* ETQF filter list: one static filter per filter consumer. This is
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* to avoid filter collisions later. Add new filters here!!
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*
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* Current filters: Filter 3
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*/
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#define IGB_ETQF_FILTER_1588 3
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#define IGB_N_EXTTS 2
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#define IGB_N_PEROUT 2
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#define IGB_N_SDP 4
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#define IGB_RETA_SIZE 128
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enum igb_filter_match_flags {
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IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
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IGB_FILTER_FLAG_VLAN_TCI = 0x2,
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};
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#define IGB_MAX_RXNFC_FILTERS 16
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/* RX network flow classification data structure */
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struct igb_nfc_input {
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/* Byte layout in order, all values with MSB first:
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* match_flags - 1 byte
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* etype - 2 bytes
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* vlan_tci - 2 bytes
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*/
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u8 match_flags;
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__be16 etype;
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__be16 vlan_tci;
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};
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struct igb_nfc_filter {
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struct hlist_node nfc_node;
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struct igb_nfc_input filter;
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u16 etype_reg_index;
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u16 sw_idx;
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u16 action;
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};
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/* board specific private data structure */
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struct igb_adapter {
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct net_device *netdev;
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unsigned long state;
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unsigned int flags;
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unsigned int num_q_vectors;
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struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
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/* Interrupt Throttle Rate */
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u32 rx_itr_setting;
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u32 tx_itr_setting;
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u16 tx_itr;
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u16 rx_itr;
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/* TX */
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u16 tx_work_limit;
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u32 tx_timeout_count;
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int num_tx_queues;
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struct igb_ring *tx_ring[16];
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/* RX */
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int num_rx_queues;
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struct igb_ring *rx_ring[16];
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u32 max_frame_size;
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u32 min_frame_size;
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struct timer_list watchdog_timer;
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struct timer_list phy_info_timer;
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u16 mng_vlan_id;
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u32 bd_number;
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u32 wol;
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u32 en_mng_pt;
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u16 link_speed;
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u16 link_duplex;
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u8 __iomem *io_addr; /* Mainly for iounmap use */
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struct work_struct reset_task;
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struct work_struct watchdog_task;
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bool fc_autoneg;
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u8 tx_timeout_factor;
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struct timer_list blink_timer;
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unsigned long led_status;
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/* OS defined structs */
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struct pci_dev *pdev;
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spinlock_t stats64_lock;
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struct rtnl_link_stats64 stats64;
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/* structs defined in e1000_hw.h */
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struct e1000_hw hw;
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struct e1000_hw_stats stats;
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struct e1000_phy_info phy_info;
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u32 test_icr;
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struct igb_ring test_tx_ring;
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struct igb_ring test_rx_ring;
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int msg_enable;
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struct igb_q_vector *q_vector[MAX_Q_VECTORS];
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u32 eims_enable_mask;
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u32 eims_other;
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/* to not mess up cache alignment, always add to the bottom */
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u16 tx_ring_count;
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u16 rx_ring_count;
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unsigned int vfs_allocated_count;
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struct vf_data_storage *vf_data;
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int vf_rate_link_speed;
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u32 rss_queues;
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u32 wvbr;
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u32 *shadow_vfta;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_caps;
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struct delayed_work ptp_overflow_work;
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struct work_struct ptp_tx_work;
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struct sk_buff *ptp_tx_skb;
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struct hwtstamp_config tstamp_config;
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unsigned long ptp_tx_start;
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unsigned long last_rx_ptp_check;
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unsigned long last_rx_timestamp;
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unsigned int ptp_flags;
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spinlock_t tmreg_lock;
|
|
struct cyclecounter cc;
|
|
struct timecounter tc;
|
|
u32 tx_hwtstamp_timeouts;
|
|
u32 rx_hwtstamp_cleared;
|
|
bool pps_sys_wrap_on;
|
|
|
|
struct ptp_pin_desc sdp_config[IGB_N_SDP];
|
|
struct {
|
|
struct timespec64 start;
|
|
struct timespec64 period;
|
|
} perout[IGB_N_PEROUT];
|
|
|
|
char fw_version[32];
|
|
#ifdef CONFIG_IGB_HWMON
|
|
struct hwmon_buff *igb_hwmon_buff;
|
|
bool ets;
|
|
#endif
|
|
struct i2c_algo_bit_data i2c_algo;
|
|
struct i2c_adapter i2c_adap;
|
|
struct i2c_client *i2c_client;
|
|
u32 rss_indir_tbl_init;
|
|
u8 rss_indir_tbl[IGB_RETA_SIZE];
|
|
|
|
unsigned long link_check_timeout;
|
|
int copper_tries;
|
|
struct e1000_info ei;
|
|
u16 eee_advert;
|
|
|
|
/* RX network flow classification support */
|
|
struct hlist_head nfc_filter_list;
|
|
unsigned int nfc_filter_count;
|
|
/* lock for RX network flow classification filter */
|
|
spinlock_t nfc_lock;
|
|
bool etype_bitmap[MAX_ETYPE_FILTER];
|
|
};
|
|
|
|
/* flags controlling PTP/1588 function */
|
|
#define IGB_PTP_ENABLED BIT(0)
|
|
#define IGB_PTP_OVERFLOW_CHECK BIT(1)
|
|
|
|
#define IGB_FLAG_HAS_MSI BIT(0)
|
|
#define IGB_FLAG_DCA_ENABLED BIT(1)
|
|
#define IGB_FLAG_QUAD_PORT_A BIT(2)
|
|
#define IGB_FLAG_QUEUE_PAIRS BIT(3)
|
|
#define IGB_FLAG_DMAC BIT(4)
|
|
#define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
|
|
#define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
|
|
#define IGB_FLAG_WOL_SUPPORTED BIT(8)
|
|
#define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
|
|
#define IGB_FLAG_MEDIA_RESET BIT(10)
|
|
#define IGB_FLAG_MAS_CAPABLE BIT(11)
|
|
#define IGB_FLAG_MAS_ENABLE BIT(12)
|
|
#define IGB_FLAG_HAS_MSIX BIT(13)
|
|
#define IGB_FLAG_EEE BIT(14)
|
|
#define IGB_FLAG_VLAN_PROMISC BIT(15)
|
|
|
|
/* Media Auto Sense */
|
|
#define IGB_MAS_ENABLE_0 0X0001
|
|
#define IGB_MAS_ENABLE_1 0X0002
|
|
#define IGB_MAS_ENABLE_2 0X0004
|
|
#define IGB_MAS_ENABLE_3 0X0008
|
|
|
|
/* DMA Coalescing defines */
|
|
#define IGB_MIN_TXPBSIZE 20408
|
|
#define IGB_TX_BUF_4096 4096
|
|
#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
|
|
|
|
#define IGB_82576_TSYNC_SHIFT 19
|
|
#define IGB_TS_HDR_LEN 16
|
|
enum e1000_state_t {
|
|
__IGB_TESTING,
|
|
__IGB_RESETTING,
|
|
__IGB_DOWN,
|
|
__IGB_PTP_TX_IN_PROGRESS,
|
|
};
|
|
|
|
enum igb_boards {
|
|
board_82575,
|
|
};
|
|
|
|
extern char igb_driver_name[];
|
|
extern char igb_driver_version[];
|
|
|
|
int igb_open(struct net_device *netdev);
|
|
int igb_close(struct net_device *netdev);
|
|
int igb_up(struct igb_adapter *);
|
|
void igb_down(struct igb_adapter *);
|
|
void igb_reinit_locked(struct igb_adapter *);
|
|
void igb_reset(struct igb_adapter *);
|
|
int igb_reinit_queues(struct igb_adapter *);
|
|
void igb_write_rss_indir_tbl(struct igb_adapter *);
|
|
int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
|
|
int igb_setup_tx_resources(struct igb_ring *);
|
|
int igb_setup_rx_resources(struct igb_ring *);
|
|
void igb_free_tx_resources(struct igb_ring *);
|
|
void igb_free_rx_resources(struct igb_ring *);
|
|
void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
|
|
void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
|
|
void igb_setup_tctl(struct igb_adapter *);
|
|
void igb_setup_rctl(struct igb_adapter *);
|
|
netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
|
|
void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);
|
|
void igb_alloc_rx_buffers(struct igb_ring *, u16);
|
|
void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
|
|
bool igb_has_link(struct igb_adapter *adapter);
|
|
void igb_set_ethtool_ops(struct net_device *);
|
|
void igb_power_up_link(struct igb_adapter *);
|
|
void igb_set_fw_version(struct igb_adapter *);
|
|
void igb_ptp_init(struct igb_adapter *adapter);
|
|
void igb_ptp_stop(struct igb_adapter *adapter);
|
|
void igb_ptp_reset(struct igb_adapter *adapter);
|
|
void igb_ptp_suspend(struct igb_adapter *adapter);
|
|
void igb_ptp_rx_hang(struct igb_adapter *adapter);
|
|
void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
|
|
void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
|
|
struct sk_buff *skb);
|
|
int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
|
int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
|
void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
|
|
#ifdef CONFIG_IGB_HWMON
|
|
void igb_sysfs_exit(struct igb_adapter *adapter);
|
|
int igb_sysfs_init(struct igb_adapter *adapter);
|
|
#endif
|
|
static inline s32 igb_reset_phy(struct e1000_hw *hw)
|
|
{
|
|
if (hw->phy.ops.reset)
|
|
return hw->phy.ops.reset(hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
|
|
{
|
|
if (hw->phy.ops.read_reg)
|
|
return hw->phy.ops.read_reg(hw, offset, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
|
|
{
|
|
if (hw->phy.ops.write_reg)
|
|
return hw->phy.ops.write_reg(hw, offset, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline s32 igb_get_phy_info(struct e1000_hw *hw)
|
|
{
|
|
if (hw->phy.ops.get_phy_info)
|
|
return hw->phy.ops.get_phy_info(hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
|
|
{
|
|
return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
|
|
}
|
|
|
|
int igb_add_filter(struct igb_adapter *adapter,
|
|
struct igb_nfc_filter *input);
|
|
int igb_erase_filter(struct igb_adapter *adapter,
|
|
struct igb_nfc_filter *input);
|
|
|
|
#endif /* _IGB_H_ */
|