mirror of https://gitee.com/openkylin/linux.git
521 lines
14 KiB
C
521 lines
14 KiB
C
/*
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* clk-xgene.c - AppliedMicro X-Gene Clock Interface
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*
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* Copyright (c) 2013, Applied Micro Circuits Corporation
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* Author: Loc Ho <lho@apm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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/* Register SCU_PCPPLL bit fields */
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#define N_DIV_RD(src) (((src) & 0x000001ff))
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/* Register SCU_SOCPLL bit fields */
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#define CLKR_RD(src) (((src) & 0x07000000)>>24)
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#define CLKOD_RD(src) (((src) & 0x00300000)>>20)
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#define REGSPEC_RESET_F1_MASK 0x00010000
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#define CLKF_RD(src) (((src) & 0x000001ff))
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#define XGENE_CLK_DRIVER_VER "0.1"
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static DEFINE_SPINLOCK(clk_lock);
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static inline u32 xgene_clk_read(void __iomem *csr)
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{
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return readl_relaxed(csr);
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}
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static inline void xgene_clk_write(u32 data, void __iomem *csr)
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{
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return writel_relaxed(data, csr);
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}
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/* PLL Clock */
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enum xgene_pll_type {
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PLL_TYPE_PCP = 0,
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PLL_TYPE_SOC = 1,
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};
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struct xgene_clk_pll {
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struct clk_hw hw;
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void __iomem *reg;
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spinlock_t *lock;
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u32 pll_offset;
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enum xgene_pll_type type;
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};
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#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
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static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
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{
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struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
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u32 data;
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data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
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pr_debug("%s pll %s\n", clk_hw_get_name(hw),
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data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
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return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
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}
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static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
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unsigned long fref;
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unsigned long fvco;
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u32 pll;
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u32 nref;
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u32 nout;
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u32 nfb;
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pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
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if (pllclk->type == PLL_TYPE_PCP) {
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/*
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* PLL VCO = Reference clock * NF
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* PCP PLL = PLL_VCO / 2
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*/
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nout = 2;
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fvco = parent_rate * (N_DIV_RD(pll) + 4);
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} else {
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/*
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* Fref = Reference Clock / NREF;
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* Fvco = Fref * NFB;
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* Fout = Fvco / NOUT;
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*/
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nref = CLKR_RD(pll) + 1;
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nout = CLKOD_RD(pll) + 1;
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nfb = CLKF_RD(pll);
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fref = parent_rate / nref;
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fvco = fref * nfb;
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}
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pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
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fvco / nout, parent_rate);
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return fvco / nout;
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}
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static const struct clk_ops xgene_clk_pll_ops = {
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.is_enabled = xgene_clk_pll_is_enabled,
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.recalc_rate = xgene_clk_pll_recalc_rate,
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};
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static struct clk *xgene_register_clk_pll(struct device *dev,
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const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u32 pll_offset,
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u32 type, spinlock_t *lock)
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{
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struct xgene_clk_pll *apmclk;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the APM clock structure */
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apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
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if (!apmclk) {
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pr_err("%s: could not allocate APM clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &xgene_clk_pll_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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apmclk->reg = reg;
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apmclk->lock = lock;
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apmclk->pll_offset = pll_offset;
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apmclk->type = type;
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apmclk->hw.init = &init;
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/* Register the clock */
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clk = clk_register(dev, &apmclk->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: could not register clk %s\n", __func__, name);
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kfree(apmclk);
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return NULL;
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}
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return clk;
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}
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static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
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{
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const char *clk_name = np->full_name;
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struct clk *clk;
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void __iomem *reg;
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reg = of_iomap(np, 0);
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if (reg == NULL) {
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pr_err("Unable to map CSR register for %s\n", np->full_name);
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return;
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}
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of_property_read_string(np, "clock-output-names", &clk_name);
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clk = xgene_register_clk_pll(NULL,
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clk_name, of_clk_get_parent_name(np, 0),
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CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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pr_debug("Add %s clock PLL\n", clk_name);
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}
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}
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static void xgene_socpllclk_init(struct device_node *np)
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{
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xgene_pllclk_init(np, PLL_TYPE_SOC);
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}
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static void xgene_pcppllclk_init(struct device_node *np)
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{
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xgene_pllclk_init(np, PLL_TYPE_PCP);
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}
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/* IP Clock */
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struct xgene_dev_parameters {
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void __iomem *csr_reg; /* CSR for IP clock */
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u32 reg_clk_offset; /* Offset to clock enable CSR */
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u32 reg_clk_mask; /* Mask bit for clock enable */
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u32 reg_csr_offset; /* Offset to CSR reset */
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u32 reg_csr_mask; /* Mask bit for disable CSR reset */
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void __iomem *divider_reg; /* CSR for divider */
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u32 reg_divider_offset; /* Offset to divider register */
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u32 reg_divider_shift; /* Bit shift to divider field */
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u32 reg_divider_width; /* Width of the bit to divider field */
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};
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struct xgene_clk {
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struct clk_hw hw;
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spinlock_t *lock;
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struct xgene_dev_parameters param;
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};
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#define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
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static int xgene_clk_enable(struct clk_hw *hw)
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{
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struct xgene_clk *pclk = to_xgene_clk(hw);
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unsigned long flags = 0;
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u32 data;
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phys_addr_t reg;
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if (pclk->lock)
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spin_lock_irqsave(pclk->lock, flags);
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if (pclk->param.csr_reg != NULL) {
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pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
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reg = __pa(pclk->param.csr_reg);
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/* First enable the clock */
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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data |= pclk->param.reg_clk_mask;
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xgene_clk_write(data, pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
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clk_hw_get_name(hw), ®,
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pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
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data);
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/* Second enable the CSR */
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_csr_offset);
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data &= ~pclk->param.reg_csr_mask;
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xgene_clk_write(data, pclk->param.csr_reg +
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pclk->param.reg_csr_offset);
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pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
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clk_hw_get_name(hw), ®,
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pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
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data);
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}
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if (pclk->lock)
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spin_unlock_irqrestore(pclk->lock, flags);
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return 0;
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}
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static void xgene_clk_disable(struct clk_hw *hw)
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{
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struct xgene_clk *pclk = to_xgene_clk(hw);
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unsigned long flags = 0;
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u32 data;
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if (pclk->lock)
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spin_lock_irqsave(pclk->lock, flags);
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if (pclk->param.csr_reg != NULL) {
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pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
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/* First put the CSR in reset */
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_csr_offset);
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data |= pclk->param.reg_csr_mask;
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xgene_clk_write(data, pclk->param.csr_reg +
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pclk->param.reg_csr_offset);
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/* Second disable the clock */
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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data &= ~pclk->param.reg_clk_mask;
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xgene_clk_write(data, pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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}
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if (pclk->lock)
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spin_unlock_irqrestore(pclk->lock, flags);
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}
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static int xgene_clk_is_enabled(struct clk_hw *hw)
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{
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struct xgene_clk *pclk = to_xgene_clk(hw);
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u32 data = 0;
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if (pclk->param.csr_reg != NULL) {
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pr_debug("%s clock checking\n", clk_hw_get_name(hw));
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
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data & pclk->param.reg_clk_mask ? "enabled" :
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"disabled");
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}
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if (pclk->param.csr_reg == NULL)
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return 1;
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return data & pclk->param.reg_clk_mask ? 1 : 0;
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}
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static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct xgene_clk *pclk = to_xgene_clk(hw);
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u32 data;
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if (pclk->param.divider_reg) {
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data = xgene_clk_read(pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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data >>= pclk->param.reg_divider_shift;
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data &= (1 << pclk->param.reg_divider_width) - 1;
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pr_debug("%s clock recalc rate %ld parent %ld\n",
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clk_hw_get_name(hw),
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parent_rate / data, parent_rate);
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return parent_rate / data;
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} else {
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pr_debug("%s clock recalc rate %ld parent %ld\n",
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clk_hw_get_name(hw), parent_rate, parent_rate);
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return parent_rate;
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}
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}
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static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct xgene_clk *pclk = to_xgene_clk(hw);
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unsigned long flags = 0;
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u32 data;
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u32 divider;
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u32 divider_save;
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if (pclk->lock)
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spin_lock_irqsave(pclk->lock, flags);
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if (pclk->param.divider_reg) {
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/* Let's compute the divider */
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if (rate > parent_rate)
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rate = parent_rate;
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divider_save = divider = parent_rate / rate; /* Rounded down */
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divider &= (1 << pclk->param.reg_divider_width) - 1;
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divider <<= pclk->param.reg_divider_shift;
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/* Set new divider */
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data = xgene_clk_read(pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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data &= ~((1 << pclk->param.reg_divider_width) - 1);
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data |= divider;
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xgene_clk_write(data, pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
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parent_rate / divider_save);
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} else {
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divider_save = 1;
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}
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if (pclk->lock)
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spin_unlock_irqrestore(pclk->lock, flags);
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return parent_rate / divider_save;
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}
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static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct xgene_clk *pclk = to_xgene_clk(hw);
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unsigned long parent_rate = *prate;
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u32 divider;
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if (pclk->param.divider_reg) {
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/* Let's compute the divider */
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if (rate > parent_rate)
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rate = parent_rate;
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divider = parent_rate / rate; /* Rounded down */
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} else {
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divider = 1;
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}
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return parent_rate / divider;
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}
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static const struct clk_ops xgene_clk_ops = {
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.enable = xgene_clk_enable,
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.disable = xgene_clk_disable,
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.is_enabled = xgene_clk_is_enabled,
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.recalc_rate = xgene_clk_recalc_rate,
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.set_rate = xgene_clk_set_rate,
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.round_rate = xgene_clk_round_rate,
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};
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static struct clk *xgene_register_clk(struct device *dev,
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const char *name, const char *parent_name,
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struct xgene_dev_parameters *parameters, spinlock_t *lock)
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{
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struct xgene_clk *apmclk;
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struct clk *clk;
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struct clk_init_data init;
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int rc;
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/* allocate the APM clock structure */
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apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
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if (!apmclk) {
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pr_err("%s: could not allocate APM clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &xgene_clk_ops;
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init.flags = 0;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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apmclk->lock = lock;
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apmclk->hw.init = &init;
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apmclk->param = *parameters;
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/* Register the clock */
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clk = clk_register(dev, &apmclk->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: could not register clk %s\n", __func__, name);
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kfree(apmclk);
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return clk;
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}
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/* Register the clock for lookup */
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rc = clk_register_clkdev(clk, name, NULL);
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if (rc != 0) {
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pr_err("%s: could not register lookup clk %s\n",
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__func__, name);
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}
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return clk;
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}
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static void __init xgene_devclk_init(struct device_node *np)
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{
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const char *clk_name = np->full_name;
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struct clk *clk;
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struct resource res;
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int rc;
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struct xgene_dev_parameters parameters;
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int i;
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/* Check if the entry is disabled */
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if (!of_device_is_available(np))
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return;
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/* Parse the DTS register for resource */
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parameters.csr_reg = NULL;
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parameters.divider_reg = NULL;
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for (i = 0; i < 2; i++) {
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void __iomem *map_res;
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rc = of_address_to_resource(np, i, &res);
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if (rc != 0) {
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if (i == 0) {
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pr_err("no DTS register for %s\n",
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np->full_name);
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return;
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}
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break;
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}
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map_res = of_iomap(np, i);
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if (map_res == NULL) {
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pr_err("Unable to map resource %d for %s\n",
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i, np->full_name);
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goto err;
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}
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if (strcmp(res.name, "div-reg") == 0)
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parameters.divider_reg = map_res;
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else /* if (strcmp(res->name, "csr-reg") == 0) */
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parameters.csr_reg = map_res;
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}
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if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset))
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parameters.reg_csr_offset = 0;
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if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask))
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parameters.reg_csr_mask = 0xF;
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if (of_property_read_u32(np, "enable-offset",
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¶meters.reg_clk_offset))
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parameters.reg_clk_offset = 0x8;
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if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask))
|
|
parameters.reg_clk_mask = 0xF;
|
|
if (of_property_read_u32(np, "divider-offset",
|
|
¶meters.reg_divider_offset))
|
|
parameters.reg_divider_offset = 0;
|
|
if (of_property_read_u32(np, "divider-width",
|
|
¶meters.reg_divider_width))
|
|
parameters.reg_divider_width = 0;
|
|
if (of_property_read_u32(np, "divider-shift",
|
|
¶meters.reg_divider_shift))
|
|
parameters.reg_divider_shift = 0;
|
|
of_property_read_string(np, "clock-output-names", &clk_name);
|
|
|
|
clk = xgene_register_clk(NULL, clk_name,
|
|
of_clk_get_parent_name(np, 0), ¶meters, &clk_lock);
|
|
if (IS_ERR(clk))
|
|
goto err;
|
|
pr_debug("Add %s clock\n", clk_name);
|
|
rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
if (rc != 0)
|
|
pr_err("%s: could register provider clk %s\n", __func__,
|
|
np->full_name);
|
|
|
|
return;
|
|
|
|
err:
|
|
if (parameters.csr_reg)
|
|
iounmap(parameters.csr_reg);
|
|
if (parameters.divider_reg)
|
|
iounmap(parameters.divider_reg);
|
|
}
|
|
|
|
CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
|
|
CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
|
|
CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
|