Tomasz Figa 6d7190f846 clk: exynos4: Define {E,V}PLL registers ... This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>		2013-04-04 15:51:15 +09:00
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Makefile	clk: exynos5440: register clocks using common clock framework	2013-03-25 18:17:05 +09:00
clk-exynos4.c	clk: exynos4: Define {E,V}PLL registers	2013-04-04 15:51:15 +09:00
clk-exynos5250.c	clk: exynos5250: register clocks using common clock framework	2013-03-25 18:16:56 +09:00
clk-exynos5440.c	clk: exynos5440: register clocks using common clock framework	2013-03-25 18:17:05 +09:00
clk-pll.c	clk: samsung: Remove unimplemented ops for pll	2013-04-04 15:51:09 +09:00
clk-pll.h	clk: samsung: add pll clock registration helper functions	2013-03-25 18:16:37 +09:00
clk.c	clk: samsung: add infrastructure to add separate aliases	2013-03-28 14:46:33 +09:00
clk.h	clk: samsung: add infrastructure to add separate aliases	2013-03-28 14:46:33 +09:00