mirror of https://gitee.com/openkylin/linux.git
946 lines
20 KiB
C
946 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
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* All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/spi/spi.h>
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#include <linux/crc7.h>
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#include "netdev.h"
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#include "cfg80211.h"
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struct wilc_spi {
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int crc_off;
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};
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static const struct wilc_hif_func wilc_hif_spi;
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/********************************************
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*
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* Spi protocol Function
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*
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********************************************/
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#define CMD_DMA_WRITE 0xc1
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#define CMD_DMA_READ 0xc2
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#define CMD_INTERNAL_WRITE 0xc3
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#define CMD_INTERNAL_READ 0xc4
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#define CMD_TERMINATE 0xc5
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#define CMD_REPEAT 0xc6
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#define CMD_DMA_EXT_WRITE 0xc7
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#define CMD_DMA_EXT_READ 0xc8
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#define CMD_SINGLE_WRITE 0xc9
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#define CMD_SINGLE_READ 0xca
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#define CMD_RESET 0xcf
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#define DATA_PKT_SZ_256 256
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#define DATA_PKT_SZ_512 512
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#define DATA_PKT_SZ_1K 1024
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#define DATA_PKT_SZ_4K (4 * 1024)
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#define DATA_PKT_SZ_8K (8 * 1024)
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#define DATA_PKT_SZ DATA_PKT_SZ_8K
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#define USE_SPI_DMA 0
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#define WILC_SPI_COMMAND_STAT_SUCCESS 0
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#define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf)
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struct wilc_spi_cmd {
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u8 cmd_type;
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union {
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struct {
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u8 addr[3];
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u8 crc[];
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} __packed simple_cmd;
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struct {
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u8 addr[3];
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u8 size[2];
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u8 crc[];
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} __packed dma_cmd;
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struct {
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u8 addr[3];
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u8 size[3];
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u8 crc[];
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} __packed dma_cmd_ext;
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struct {
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u8 addr[2];
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__be32 data;
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u8 crc[];
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} __packed internal_w_cmd;
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struct {
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u8 addr[3];
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__be32 data;
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u8 crc[];
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} __packed w_cmd;
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} u;
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} __packed;
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struct wilc_spi_read_rsp_data {
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u8 rsp_cmd_type;
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u8 status;
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u8 resp_header;
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u8 resp_data[4];
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u8 crc[];
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} __packed;
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struct wilc_spi_rsp_data {
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u8 rsp_cmd_type;
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u8 status;
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} __packed;
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static int wilc_bus_probe(struct spi_device *spi)
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{
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int ret;
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struct wilc *wilc;
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struct wilc_spi *spi_priv;
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spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
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if (!spi_priv)
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return -ENOMEM;
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ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
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if (ret) {
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kfree(spi_priv);
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return ret;
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}
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spi_set_drvdata(spi, wilc);
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wilc->dev = &spi->dev;
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wilc->bus_data = spi_priv;
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wilc->dev_irq_num = spi->irq;
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wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk");
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if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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else if (!IS_ERR(wilc->rtc_clk))
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clk_prepare_enable(wilc->rtc_clk);
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return 0;
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}
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static int wilc_bus_remove(struct spi_device *spi)
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{
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struct wilc *wilc = spi_get_drvdata(spi);
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if (!IS_ERR(wilc->rtc_clk))
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clk_disable_unprepare(wilc->rtc_clk);
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wilc_netdev_cleanup(wilc);
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return 0;
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}
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static const struct of_device_id wilc_of_match[] = {
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{ .compatible = "microchip,wilc1000", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, wilc_of_match);
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static struct spi_driver wilc_spi_driver = {
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.driver = {
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.name = MODALIAS,
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.of_match_table = wilc_of_match,
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},
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.probe = wilc_bus_probe,
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.remove = wilc_bus_remove,
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};
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module_spi_driver(wilc_spi_driver);
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MODULE_LICENSE("GPL");
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static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int ret;
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struct spi_message msg;
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if (len > 0 && b) {
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struct spi_transfer tr = {
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.tx_buf = b,
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.len = len,
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.delay = {
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.value = 0,
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.unit = SPI_DELAY_UNIT_USECS
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},
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};
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char *r_buffer = kzalloc(len, GFP_KERNEL);
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if (!r_buffer)
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return -ENOMEM;
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tr.rx_buf = r_buffer;
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dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
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memset(&msg, 0, sizeof(msg));
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spi_message_init(&msg);
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msg.spi = spi;
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msg.is_dma_mapped = USE_SPI_DMA;
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spi_message_add_tail(&tr, &msg);
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ret = spi_sync(spi, &msg);
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if (ret < 0)
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dev_err(&spi->dev, "SPI transaction failed\n");
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kfree(r_buffer);
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} else {
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dev_err(&spi->dev,
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"can't write data with the following length: %d\n",
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len);
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ret = -EINVAL;
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}
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return ret;
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}
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static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int ret;
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if (rlen > 0) {
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struct spi_message msg;
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struct spi_transfer tr = {
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.rx_buf = rb,
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.len = rlen,
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.delay = {
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.value = 0,
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.unit = SPI_DELAY_UNIT_USECS
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},
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};
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char *t_buffer = kzalloc(rlen, GFP_KERNEL);
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if (!t_buffer)
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return -ENOMEM;
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tr.tx_buf = t_buffer;
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memset(&msg, 0, sizeof(msg));
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spi_message_init(&msg);
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msg.spi = spi;
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msg.is_dma_mapped = USE_SPI_DMA;
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spi_message_add_tail(&tr, &msg);
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ret = spi_sync(spi, &msg);
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if (ret < 0)
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dev_err(&spi->dev, "SPI transaction failed\n");
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kfree(t_buffer);
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} else {
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dev_err(&spi->dev,
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"can't read data with the following length: %u\n",
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rlen);
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ret = -EINVAL;
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}
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return ret;
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}
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static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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int ret;
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if (rlen > 0) {
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struct spi_message msg;
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struct spi_transfer tr = {
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.rx_buf = rb,
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.tx_buf = wb,
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.len = rlen,
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.bits_per_word = 8,
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.delay = {
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.value = 0,
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.unit = SPI_DELAY_UNIT_USECS
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},
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};
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memset(&msg, 0, sizeof(msg));
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spi_message_init(&msg);
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msg.spi = spi;
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msg.is_dma_mapped = USE_SPI_DMA;
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spi_message_add_tail(&tr, &msg);
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ret = spi_sync(spi, &msg);
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if (ret < 0)
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dev_err(&spi->dev, "SPI transaction failed\n");
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} else {
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dev_err(&spi->dev,
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"can't read data with the following length: %u\n",
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rlen);
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ret = -EINVAL;
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}
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return ret;
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}
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static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct wilc_spi *spi_priv = wilc->bus_data;
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int ix, nbytes;
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int result = 0;
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u8 cmd, order, crc[2] = {0};
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/*
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* Data
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*/
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ix = 0;
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do {
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if (sz <= DATA_PKT_SZ) {
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nbytes = sz;
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order = 0x3;
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} else {
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nbytes = DATA_PKT_SZ;
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if (ix == 0)
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order = 0x1;
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else
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order = 0x02;
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}
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/*
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* Write command
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*/
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cmd = 0xf0;
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cmd |= order;
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if (wilc_spi_tx(wilc, &cmd, 1)) {
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dev_err(&spi->dev,
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"Failed data block cmd write, bus error...\n");
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result = -EINVAL;
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break;
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}
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/*
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* Write data
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*/
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if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
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dev_err(&spi->dev,
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"Failed data block write, bus error...\n");
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result = -EINVAL;
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break;
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}
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/*
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* Write Crc
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*/
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if (!spi_priv->crc_off) {
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if (wilc_spi_tx(wilc, crc, 2)) {
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dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
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result = -EINVAL;
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break;
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}
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}
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/*
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* No need to wait for response
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*/
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ix += nbytes;
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sz -= nbytes;
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} while (sz);
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return result;
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}
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/********************************************
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*
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* Spi Internal Read/Write Function
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*
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********************************************/
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static u8 wilc_get_crc7(u8 *buffer, u32 len)
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{
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return crc7_be(0xfe, buffer, len);
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}
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static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
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u8 clockless)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct wilc_spi *spi_priv = wilc->bus_data;
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u8 wb[32], rb[32];
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int cmd_len, resp_len;
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u8 crc[2];
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struct wilc_spi_cmd *c;
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struct wilc_spi_read_rsp_data *r;
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memset(wb, 0x0, sizeof(wb));
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memset(rb, 0x0, sizeof(rb));
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c = (struct wilc_spi_cmd *)wb;
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c->cmd_type = cmd;
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if (cmd == CMD_SINGLE_READ) {
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c->u.simple_cmd.addr[0] = adr >> 16;
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c->u.simple_cmd.addr[1] = adr >> 8;
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c->u.simple_cmd.addr[2] = adr;
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} else if (cmd == CMD_INTERNAL_READ) {
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c->u.simple_cmd.addr[0] = adr >> 8;
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if (clockless == 1)
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c->u.simple_cmd.addr[0] |= BIT(7);
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c->u.simple_cmd.addr[1] = adr;
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c->u.simple_cmd.addr[2] = 0x0;
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} else {
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dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
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return -EINVAL;
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}
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cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
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resp_len = sizeof(*r);
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if (!spi_priv->crc_off) {
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c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
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cmd_len += 1;
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resp_len += 2;
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}
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if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
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dev_err(&spi->dev,
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"spi buffer size too small (%d) (%d) (%zu)\n",
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cmd_len, resp_len, ARRAY_SIZE(wb));
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return -EINVAL;
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}
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if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
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dev_err(&spi->dev, "Failed cmd write, bus error...\n");
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return -EINVAL;
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}
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r = (struct wilc_spi_read_rsp_data *)&rb[cmd_len];
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if (r->rsp_cmd_type != cmd) {
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dev_err(&spi->dev,
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"Failed cmd response, cmd (%02x), resp (%02x)\n",
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cmd, r->rsp_cmd_type);
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return -EINVAL;
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}
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if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
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dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
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r->status);
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return -EINVAL;
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}
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if (WILC_GET_RESP_HDR_START(r->resp_header) != 0xf) {
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dev_err(&spi->dev, "Error, data read response (%02x)\n",
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r->resp_header);
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return -EINVAL;
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}
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if (b)
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memcpy(b, r->resp_data, 4);
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if (!spi_priv->crc_off)
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memcpy(crc, r->crc, 2);
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return 0;
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}
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static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
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u8 clockless)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct wilc_spi *spi_priv = wilc->bus_data;
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u8 wb[32], rb[32];
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int cmd_len, resp_len;
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struct wilc_spi_cmd *c;
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struct wilc_spi_rsp_data *r;
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memset(wb, 0x0, sizeof(wb));
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memset(rb, 0x0, sizeof(rb));
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c = (struct wilc_spi_cmd *)wb;
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c->cmd_type = cmd;
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if (cmd == CMD_INTERNAL_WRITE) {
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c->u.internal_w_cmd.addr[0] = adr >> 8;
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if (clockless == 1)
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c->u.internal_w_cmd.addr[0] |= BIT(7);
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c->u.internal_w_cmd.addr[1] = adr;
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c->u.internal_w_cmd.data = cpu_to_be32(data);
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cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
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if (!spi_priv->crc_off)
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c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
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} else if (cmd == CMD_SINGLE_WRITE) {
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c->u.w_cmd.addr[0] = adr >> 16;
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c->u.w_cmd.addr[1] = adr >> 8;
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c->u.w_cmd.addr[2] = adr;
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c->u.w_cmd.data = cpu_to_be32(data);
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cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
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if (!spi_priv->crc_off)
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c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
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} else {
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dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
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return -EINVAL;
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}
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if (!spi_priv->crc_off)
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cmd_len += 1;
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resp_len = sizeof(*r);
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if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
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dev_err(&spi->dev,
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"spi buffer size too small (%d) (%d) (%zu)\n",
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cmd_len, resp_len, ARRAY_SIZE(wb));
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return -EINVAL;
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}
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if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
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dev_err(&spi->dev, "Failed cmd write, bus error...\n");
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return -EINVAL;
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}
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r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
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if (r->rsp_cmd_type != cmd) {
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dev_err(&spi->dev,
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"Failed cmd response, cmd (%02x), resp (%02x)\n",
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cmd, r->rsp_cmd_type);
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return -EINVAL;
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}
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if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
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dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
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r->status);
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return -EINVAL;
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}
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return 0;
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}
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static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct wilc_spi *spi_priv = wilc->bus_data;
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u8 wb[32], rb[32];
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int cmd_len, resp_len;
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int retry, ix = 0;
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u8 crc[2];
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struct wilc_spi_cmd *c;
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struct wilc_spi_rsp_data *r;
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memset(wb, 0x0, sizeof(wb));
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memset(rb, 0x0, sizeof(rb));
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c = (struct wilc_spi_cmd *)wb;
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c->cmd_type = cmd;
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if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
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c->u.dma_cmd.addr[0] = adr >> 16;
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c->u.dma_cmd.addr[1] = adr >> 8;
|
|
c->u.dma_cmd.addr[2] = adr;
|
|
c->u.dma_cmd.size[0] = sz >> 8;
|
|
c->u.dma_cmd.size[1] = sz;
|
|
cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
|
|
if (!spi_priv->crc_off)
|
|
c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
|
|
} else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
|
|
c->u.dma_cmd_ext.addr[0] = adr >> 16;
|
|
c->u.dma_cmd_ext.addr[1] = adr >> 8;
|
|
c->u.dma_cmd_ext.addr[2] = adr;
|
|
c->u.dma_cmd_ext.size[0] = sz >> 16;
|
|
c->u.dma_cmd_ext.size[1] = sz >> 8;
|
|
c->u.dma_cmd_ext.size[2] = sz;
|
|
cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
|
|
if (!spi_priv->crc_off)
|
|
c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
|
|
} else {
|
|
dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
|
|
cmd);
|
|
return -EINVAL;
|
|
}
|
|
if (!spi_priv->crc_off)
|
|
cmd_len += 1;
|
|
|
|
resp_len = sizeof(*r);
|
|
|
|
if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
|
|
dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
|
|
cmd_len, resp_len, ARRAY_SIZE(wb));
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
|
|
dev_err(&spi->dev, "Failed cmd write, bus error...\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
|
|
if (r->rsp_cmd_type != cmd) {
|
|
dev_err(&spi->dev,
|
|
"Failed cmd response, cmd (%02x), resp (%02x)\n",
|
|
cmd, r->rsp_cmd_type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
|
|
dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
|
|
r->status);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
|
|
return 0;
|
|
|
|
while (sz > 0) {
|
|
int nbytes;
|
|
u8 rsp;
|
|
|
|
if (sz <= DATA_PKT_SZ)
|
|
nbytes = sz;
|
|
else
|
|
nbytes = DATA_PKT_SZ;
|
|
|
|
/*
|
|
* Data Response header
|
|
*/
|
|
retry = 100;
|
|
do {
|
|
if (wilc_spi_rx(wilc, &rsp, 1)) {
|
|
dev_err(&spi->dev,
|
|
"Failed resp read, bus err\n");
|
|
return -EINVAL;
|
|
}
|
|
if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
|
|
break;
|
|
} while (retry--);
|
|
|
|
/*
|
|
* Read bytes
|
|
*/
|
|
if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
|
|
dev_err(&spi->dev,
|
|
"Failed block read, bus err\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Read Crc
|
|
*/
|
|
if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
|
|
dev_err(&spi->dev,
|
|
"Failed block crc read, bus err\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ix += nbytes;
|
|
sz -= nbytes;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
int result;
|
|
u8 cmd = CMD_SINGLE_READ;
|
|
u8 clockless = 0;
|
|
|
|
if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
|
|
/* Clockless register */
|
|
cmd = CMD_INTERNAL_READ;
|
|
clockless = 1;
|
|
}
|
|
|
|
result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
|
|
if (result) {
|
|
dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
|
|
return result;
|
|
}
|
|
|
|
le32_to_cpus(data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
int result;
|
|
|
|
if (size <= 4)
|
|
return -EINVAL;
|
|
|
|
result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
|
|
if (result) {
|
|
dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
|
|
return result;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
int result;
|
|
|
|
result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
|
|
if (result) {
|
|
dev_err(&spi->dev, "Failed internal write cmd...\n");
|
|
return result;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
int result;
|
|
|
|
result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
|
|
if (result) {
|
|
dev_err(&spi->dev, "Failed internal read cmd...\n");
|
|
return result;
|
|
}
|
|
|
|
le32_to_cpus(data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/********************************************
|
|
*
|
|
* Spi interfaces
|
|
*
|
|
********************************************/
|
|
|
|
static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
int result;
|
|
u8 cmd = CMD_SINGLE_WRITE;
|
|
u8 clockless = 0;
|
|
|
|
if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
|
|
/* Clockless register */
|
|
cmd = CMD_INTERNAL_WRITE;
|
|
clockless = 1;
|
|
}
|
|
|
|
result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
|
|
if (result) {
|
|
dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
|
|
return result;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
int result;
|
|
|
|
/*
|
|
* has to be greated than 4
|
|
*/
|
|
if (size <= 4)
|
|
return -EINVAL;
|
|
|
|
result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
|
|
if (result) {
|
|
dev_err(&spi->dev,
|
|
"Failed cmd, write block (%08x)...\n", addr);
|
|
return result;
|
|
}
|
|
|
|
/*
|
|
* Data
|
|
*/
|
|
result = spi_data_write(wilc, buf, size);
|
|
if (result) {
|
|
dev_err(&spi->dev, "Failed block data write...\n");
|
|
return result;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/********************************************
|
|
*
|
|
* Bus interfaces
|
|
*
|
|
********************************************/
|
|
|
|
static int wilc_spi_deinit(struct wilc *wilc)
|
|
{
|
|
/*
|
|
* TODO:
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static int wilc_spi_init(struct wilc *wilc, bool resume)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
struct wilc_spi *spi_priv = wilc->bus_data;
|
|
u32 reg;
|
|
u32 chipid;
|
|
static int isinit;
|
|
int ret;
|
|
|
|
if (isinit) {
|
|
ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
|
|
if (ret)
|
|
dev_err(&spi->dev, "Fail cmd read chip id...\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* configure protocol
|
|
*/
|
|
|
|
/*
|
|
* TODO: We can remove the CRC trials if there is a definite
|
|
* way to reset
|
|
*/
|
|
/* the SPI to it's initial value. */
|
|
ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
|
|
if (ret) {
|
|
/*
|
|
* Read failed. Try with CRC off. This might happen when module
|
|
* is removed but chip isn't reset
|
|
*/
|
|
spi_priv->crc_off = 1;
|
|
dev_err(&spi->dev,
|
|
"Failed read with CRC on, retrying with CRC off\n");
|
|
ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
|
|
if (ret) {
|
|
/*
|
|
* Read failed with both CRC on and off,
|
|
* something went bad
|
|
*/
|
|
dev_err(&spi->dev, "Failed internal read protocol\n");
|
|
return ret;
|
|
}
|
|
}
|
|
if (spi_priv->crc_off == 0) {
|
|
reg &= ~0xc; /* disable crc checking */
|
|
reg &= ~0x70;
|
|
reg |= (0x5 << 4);
|
|
ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
|
|
if (ret) {
|
|
dev_err(&spi->dev,
|
|
"[wilc spi %d]: Failed internal write reg\n",
|
|
__LINE__);
|
|
return ret;
|
|
}
|
|
spi_priv->crc_off = 1;
|
|
}
|
|
|
|
/*
|
|
* make sure can read back chip id correctly
|
|
*/
|
|
ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Fail cmd read chip id...\n");
|
|
return ret;
|
|
}
|
|
|
|
isinit = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
|
|
{
|
|
int ret;
|
|
|
|
ret = spi_internal_read(wilc,
|
|
WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
|
|
*size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
|
|
{
|
|
return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
|
|
int_status);
|
|
}
|
|
|
|
static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
|
|
{
|
|
return spi_internal_write(wilc, WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
|
|
val);
|
|
}
|
|
|
|
static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
|
|
{
|
|
struct spi_device *spi = to_spi_device(wilc->dev);
|
|
u32 reg;
|
|
int ret, i;
|
|
|
|
if (nint > MAX_NUM_INT) {
|
|
dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* interrupt pin mux select
|
|
*/
|
|
ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed read reg (%08x)...\n",
|
|
WILC_PIN_MUX_0);
|
|
return ret;
|
|
}
|
|
reg |= BIT(8);
|
|
ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed write reg (%08x)...\n",
|
|
WILC_PIN_MUX_0);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* interrupt enable
|
|
*/
|
|
ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed read reg (%08x)...\n",
|
|
WILC_INTR_ENABLE);
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; (i < 5) && (nint > 0); i++, nint--)
|
|
reg |= (BIT((27 + i)));
|
|
|
|
ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed write reg (%08x)...\n",
|
|
WILC_INTR_ENABLE);
|
|
return ret;
|
|
}
|
|
if (nint) {
|
|
ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed read reg (%08x)...\n",
|
|
WILC_INTR2_ENABLE);
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; (i < 3) && (nint > 0); i++, nint--)
|
|
reg |= BIT(i);
|
|
|
|
ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed write reg (%08x)...\n",
|
|
WILC_INTR2_ENABLE);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Global spi HIF function table */
|
|
static const struct wilc_hif_func wilc_hif_spi = {
|
|
.hif_init = wilc_spi_init,
|
|
.hif_deinit = wilc_spi_deinit,
|
|
.hif_read_reg = wilc_spi_read_reg,
|
|
.hif_write_reg = wilc_spi_write_reg,
|
|
.hif_block_rx = wilc_spi_read,
|
|
.hif_block_tx = wilc_spi_write,
|
|
.hif_read_int = wilc_spi_read_int,
|
|
.hif_clear_int_ext = wilc_spi_clear_int_ext,
|
|
.hif_read_size = wilc_spi_read_size,
|
|
.hif_block_tx_ext = wilc_spi_write,
|
|
.hif_block_rx_ext = wilc_spi_read,
|
|
.hif_sync_ext = wilc_spi_sync_ext,
|
|
};
|