mirror of https://gitee.com/openkylin/linux.git
1086 lines
26 KiB
C
1086 lines
26 KiB
C
/*
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* Page table handling routines for radix page table.
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*
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* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#define pr_fmt(fmt) "radix-mmu: " fmt
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#include <linux/kernel.h>
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#include <linux/sched/mm.h>
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#include <linux/memblock.h>
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#include <linux/of_fdt.h>
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#include <linux/mm.h>
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#include <linux/string_helpers.h>
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#include <linux/stop_machine.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/mmu.h>
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#include <asm/firmware.h>
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#include <asm/powernv.h>
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#include <asm/sections.h>
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#include <asm/trace.h>
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#include <trace/events/thp.h>
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unsigned int mmu_pid_bits;
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unsigned int mmu_base_pid;
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static int native_register_process_table(unsigned long base, unsigned long pg_sz,
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unsigned long table_size)
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{
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unsigned long patb0, patb1;
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patb0 = be64_to_cpu(partition_tb[0].patb0);
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patb1 = base | table_size | PATB_GR;
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mmu_partition_table_set_entry(0, patb0, patb1);
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return 0;
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}
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static __ref void *early_alloc_pgtable(unsigned long size, int nid,
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unsigned long region_start, unsigned long region_end)
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{
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unsigned long pa = 0;
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void *pt;
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if (region_start || region_end) /* has region hint */
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pa = memblock_alloc_range(size, size, region_start, region_end,
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MEMBLOCK_NONE);
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else if (nid != -1) /* has node hint */
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pa = memblock_alloc_base_nid(size, size,
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MEMBLOCK_ALLOC_ANYWHERE,
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nid, MEMBLOCK_NONE);
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if (!pa)
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pa = memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE);
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BUG_ON(!pa);
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pt = __va(pa);
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memset(pt, 0, size);
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return pt;
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}
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static int early_map_kernel_page(unsigned long ea, unsigned long pa,
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pgprot_t flags,
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unsigned int map_page_size,
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int nid,
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unsigned long region_start, unsigned long region_end)
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{
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unsigned long pfn = pa >> PAGE_SHIFT;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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pgdp = pgd_offset_k(ea);
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if (pgd_none(*pgdp)) {
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pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
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region_start, region_end);
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pgd_populate(&init_mm, pgdp, pudp);
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}
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pudp = pud_offset(pgdp, ea);
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if (map_page_size == PUD_SIZE) {
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ptep = (pte_t *)pudp;
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goto set_the_pte;
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}
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if (pud_none(*pudp)) {
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pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
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region_start, region_end);
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pud_populate(&init_mm, pudp, pmdp);
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}
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pmdp = pmd_offset(pudp, ea);
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if (map_page_size == PMD_SIZE) {
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ptep = pmdp_ptep(pmdp);
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goto set_the_pte;
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}
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if (!pmd_present(*pmdp)) {
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ptep = early_alloc_pgtable(PAGE_SIZE, nid,
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region_start, region_end);
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pmd_populate_kernel(&init_mm, pmdp, ptep);
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}
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ptep = pte_offset_kernel(pmdp, ea);
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set_the_pte:
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set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
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smp_wmb();
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return 0;
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}
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/*
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* nid, region_start, and region_end are hints to try to place the page
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* table memory in the same node or region.
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*/
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static int __map_kernel_page(unsigned long ea, unsigned long pa,
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pgprot_t flags,
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unsigned int map_page_size,
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int nid,
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unsigned long region_start, unsigned long region_end)
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{
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unsigned long pfn = pa >> PAGE_SHIFT;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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/*
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* Make sure task size is correct as per the max adddr
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*/
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BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
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if (unlikely(!slab_is_available()))
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return early_map_kernel_page(ea, pa, flags, map_page_size,
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nid, region_start, region_end);
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/*
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* Should make page table allocation functions be able to take a
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* node, so we can place kernel page tables on the right nodes after
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* boot.
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*/
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pgdp = pgd_offset_k(ea);
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pudp = pud_alloc(&init_mm, pgdp, ea);
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if (!pudp)
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return -ENOMEM;
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if (map_page_size == PUD_SIZE) {
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ptep = (pte_t *)pudp;
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goto set_the_pte;
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}
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pmdp = pmd_alloc(&init_mm, pudp, ea);
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if (!pmdp)
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return -ENOMEM;
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if (map_page_size == PMD_SIZE) {
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ptep = pmdp_ptep(pmdp);
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goto set_the_pte;
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}
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ptep = pte_alloc_kernel(pmdp, ea);
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if (!ptep)
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return -ENOMEM;
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set_the_pte:
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set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
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smp_wmb();
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return 0;
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}
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int radix__map_kernel_page(unsigned long ea, unsigned long pa,
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pgprot_t flags,
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unsigned int map_page_size)
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{
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return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
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}
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#ifdef CONFIG_STRICT_KERNEL_RWX
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void radix__change_memory_range(unsigned long start, unsigned long end,
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unsigned long clear)
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{
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unsigned long idx;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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start = ALIGN_DOWN(start, PAGE_SIZE);
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end = PAGE_ALIGN(end); // aligns up
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pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
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start, end, clear);
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for (idx = start; idx < end; idx += PAGE_SIZE) {
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pgdp = pgd_offset_k(idx);
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pudp = pud_alloc(&init_mm, pgdp, idx);
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if (!pudp)
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continue;
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if (pud_huge(*pudp)) {
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ptep = (pte_t *)pudp;
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goto update_the_pte;
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}
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pmdp = pmd_alloc(&init_mm, pudp, idx);
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if (!pmdp)
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continue;
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if (pmd_huge(*pmdp)) {
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ptep = pmdp_ptep(pmdp);
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goto update_the_pte;
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}
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ptep = pte_alloc_kernel(pmdp, idx);
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if (!ptep)
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continue;
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update_the_pte:
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radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
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}
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radix__flush_tlb_kernel_range(start, end);
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}
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void radix__mark_rodata_ro(void)
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{
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unsigned long start, end;
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/*
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* mark_rodata_ro() will mark itself as !writable at some point.
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* Due to DD1 workaround in radix__pte_update(), we'll end up with
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* an invalid pte and the system will crash quite severly.
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*/
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if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
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pr_warn("Warning: Unable to mark rodata read only on P9 DD1\n");
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return;
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}
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start = (unsigned long)_stext;
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end = (unsigned long)__init_begin;
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radix__change_memory_range(start, end, _PAGE_WRITE);
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}
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void radix__mark_initmem_nx(void)
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{
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unsigned long start = (unsigned long)__init_begin;
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unsigned long end = (unsigned long)__init_end;
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radix__change_memory_range(start, end, _PAGE_EXEC);
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}
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#endif /* CONFIG_STRICT_KERNEL_RWX */
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static inline void __meminit print_mapping(unsigned long start,
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unsigned long end,
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unsigned long size)
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{
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char buf[10];
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if (end <= start)
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return;
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string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
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pr_info("Mapped 0x%016lx-0x%016lx with %s pages\n", start, end, buf);
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}
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static int __meminit create_physical_mapping(unsigned long start,
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unsigned long end,
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int nid)
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{
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unsigned long vaddr, addr, mapping_size = 0;
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pgprot_t prot;
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unsigned long max_mapping_size;
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#ifdef CONFIG_STRICT_KERNEL_RWX
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int split_text_mapping = 1;
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#else
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int split_text_mapping = 0;
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#endif
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start = _ALIGN_UP(start, PAGE_SIZE);
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for (addr = start; addr < end; addr += mapping_size) {
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unsigned long gap, previous_size;
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int rc;
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gap = end - addr;
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previous_size = mapping_size;
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max_mapping_size = PUD_SIZE;
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retry:
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if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
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mmu_psize_defs[MMU_PAGE_1G].shift &&
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PUD_SIZE <= max_mapping_size)
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mapping_size = PUD_SIZE;
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else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
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mmu_psize_defs[MMU_PAGE_2M].shift)
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mapping_size = PMD_SIZE;
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else
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mapping_size = PAGE_SIZE;
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if (split_text_mapping && (mapping_size == PUD_SIZE) &&
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(addr <= __pa_symbol(__init_begin)) &&
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(addr + mapping_size) >= __pa_symbol(_stext)) {
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max_mapping_size = PMD_SIZE;
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goto retry;
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}
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if (split_text_mapping && (mapping_size == PMD_SIZE) &&
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(addr <= __pa_symbol(__init_begin)) &&
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(addr + mapping_size) >= __pa_symbol(_stext))
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mapping_size = PAGE_SIZE;
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if (mapping_size != previous_size) {
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print_mapping(start, addr, previous_size);
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start = addr;
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}
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vaddr = (unsigned long)__va(addr);
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if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
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overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
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prot = PAGE_KERNEL_X;
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else
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prot = PAGE_KERNEL;
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rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
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if (rc)
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return rc;
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}
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print_mapping(start, addr, mapping_size);
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return 0;
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}
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void __init radix_init_pgtable(void)
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{
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unsigned long rts_field;
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struct memblock_region *reg;
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/* We don't support slb for radix */
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mmu_slb_size = 0;
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/*
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* Create the linear mapping, using standard page size for now
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*/
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for_each_memblock(memory, reg) {
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/*
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* The memblock allocator is up at this point, so the
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* page tables will be allocated within the range. No
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* need or a node (which we don't have yet).
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*/
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WARN_ON(create_physical_mapping(reg->base,
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reg->base + reg->size,
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-1));
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}
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/* Find out how many PID bits are supported */
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if (cpu_has_feature(CPU_FTR_HVMODE)) {
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if (!mmu_pid_bits)
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mmu_pid_bits = 20;
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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* When KVM is possible, we only use the top half of the
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* PID space to avoid collisions between host and guest PIDs
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* which can cause problems due to prefetch when exiting the
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* guest with AIL=3
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*/
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mmu_base_pid = 1 << (mmu_pid_bits - 1);
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#else
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mmu_base_pid = 1;
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#endif
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} else {
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/* The guest uses the bottom half of the PID space */
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if (!mmu_pid_bits)
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mmu_pid_bits = 19;
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mmu_base_pid = 1;
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}
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/*
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* Allocate Partition table and process table for the
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* host.
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*/
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BUG_ON(PRTB_SIZE_SHIFT > 36);
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process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
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/*
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* Fill in the process table.
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*/
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rts_field = radix__get_tree_size();
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process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
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/*
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* Fill in the partition table. We are suppose to use effective address
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* of process table here. But our linear mapping also enable us to use
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* physical address here.
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*/
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register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
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pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
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asm volatile("ptesync" : : : "memory");
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asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
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"r" (TLBIEL_INVAL_SET_LPID), "r" (0));
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
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/*
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* The init_mm context is given the first available (non-zero) PID,
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* which is the "guard PID" and contains no page table. PIDR should
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* never be set to zero because that duplicates the kernel address
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* space at the 0x0... offset (quadrant 0)!
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*
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* An arbitrary PID that may later be allocated by the PID allocator
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* for userspace processes must not be used either, because that
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* would cause stale user mappings for that PID on CPUs outside of
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* the TLB invalidation scheme (because it won't be in mm_cpumask).
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*
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* So permanently carve out one PID for the purpose of a guard PID.
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*/
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init_mm.context.id = mmu_base_pid;
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mmu_base_pid++;
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}
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static void __init radix_init_partition_table(void)
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{
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unsigned long rts_field, dw0;
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mmu_partition_table_init();
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rts_field = radix__get_tree_size();
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dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
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mmu_partition_table_set_entry(0, dw0, 0);
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pr_info("Initializing Radix MMU\n");
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pr_info("Partition table %p\n", partition_tb);
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}
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void __init radix_init_native(void)
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{
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register_process_table = native_register_process_table;
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}
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static int __init get_idx_from_shift(unsigned int shift)
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{
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int idx = -1;
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switch (shift) {
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case 0xc:
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idx = MMU_PAGE_4K;
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break;
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case 0x10:
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idx = MMU_PAGE_64K;
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break;
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case 0x15:
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idx = MMU_PAGE_2M;
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break;
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case 0x1e:
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idx = MMU_PAGE_1G;
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break;
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}
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return idx;
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}
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|
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static int __init radix_dt_scan_page_sizes(unsigned long node,
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const char *uname, int depth,
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void *data)
|
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{
|
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int size = 0;
|
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int shift, idx;
|
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unsigned int ap;
|
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const __be32 *prop;
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const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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|
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/* We are scanning "cpu" nodes only */
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if (type == NULL || strcmp(type, "cpu") != 0)
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return 0;
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/* Find MMU PID size */
|
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prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
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if (prop && size == 4)
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mmu_pid_bits = be32_to_cpup(prop);
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|
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/* Grab page size encodings */
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prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
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if (!prop)
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return 0;
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|
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pr_info("Page sizes from device-tree:\n");
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for (; size >= 4; size -= 4, ++prop) {
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struct mmu_psize_def *def;
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|
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/* top 3 bit is AP encoding */
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shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
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ap = be32_to_cpu(prop[0]) >> 29;
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pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
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idx = get_idx_from_shift(shift);
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if (idx < 0)
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continue;
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def = &mmu_psize_defs[idx];
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def->shift = shift;
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def->ap = ap;
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}
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|
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/* needed ? */
|
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cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
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return 1;
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}
|
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|
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void __init radix__early_init_devtree(void)
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{
|
|
int rc;
|
|
|
|
/*
|
|
* Try to find the available page sizes in the device-tree
|
|
*/
|
|
rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
|
|
if (rc != 0) /* Found */
|
|
goto found;
|
|
/*
|
|
* let's assume we have page 4k and 64k support
|
|
*/
|
|
mmu_psize_defs[MMU_PAGE_4K].shift = 12;
|
|
mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
|
|
|
|
mmu_psize_defs[MMU_PAGE_64K].shift = 16;
|
|
mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
|
|
found:
|
|
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
|
if (mmu_psize_defs[MMU_PAGE_2M].shift) {
|
|
/*
|
|
* map vmemmap using 2M if available
|
|
*/
|
|
mmu_vmemmap_psize = MMU_PAGE_2M;
|
|
}
|
|
#endif /* CONFIG_SPARSEMEM_VMEMMAP */
|
|
return;
|
|
}
|
|
|
|
static void update_hid_for_radix(void)
|
|
{
|
|
unsigned long hid0;
|
|
unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
|
|
|
|
asm volatile("ptesync": : :"memory");
|
|
/* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
|
|
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
|
|
: : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
|
|
/* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
|
|
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
|
|
: : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
|
|
asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
|
|
trace_tlbie(0, 0, rb, 0, 2, 0, 1);
|
|
trace_tlbie(0, 0, rb, 0, 2, 1, 1);
|
|
|
|
/*
|
|
* now switch the HID
|
|
*/
|
|
hid0 = mfspr(SPRN_HID0);
|
|
hid0 |= HID0_POWER9_RADIX;
|
|
mtspr(SPRN_HID0, hid0);
|
|
asm volatile("isync": : :"memory");
|
|
|
|
/* Wait for it to happen */
|
|
while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
|
|
cpu_relax();
|
|
}
|
|
|
|
static void radix_init_amor(void)
|
|
{
|
|
/*
|
|
* In HV mode, we init AMOR (Authority Mask Override Register) so that
|
|
* the hypervisor and guest can setup IAMR (Instruction Authority Mask
|
|
* Register), enable key 0 and set it to 1.
|
|
*
|
|
* AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
|
|
*/
|
|
mtspr(SPRN_AMOR, (3ul << 62));
|
|
}
|
|
|
|
static void radix_init_iamr(void)
|
|
{
|
|
unsigned long iamr;
|
|
|
|
/*
|
|
* The IAMR should set to 0 on DD1.
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
|
|
iamr = 0;
|
|
else
|
|
iamr = (1ul << 62);
|
|
|
|
/*
|
|
* Radix always uses key0 of the IAMR to determine if an access is
|
|
* allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
|
|
* fetch.
|
|
*/
|
|
mtspr(SPRN_IAMR, iamr);
|
|
}
|
|
|
|
void __init radix__early_init_mmu(void)
|
|
{
|
|
unsigned long lpcr;
|
|
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
/* PAGE_SIZE mappings */
|
|
mmu_virtual_psize = MMU_PAGE_64K;
|
|
#else
|
|
mmu_virtual_psize = MMU_PAGE_4K;
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
|
/* vmemmap mapping */
|
|
mmu_vmemmap_psize = mmu_virtual_psize;
|
|
#endif
|
|
/*
|
|
* initialize page table size
|
|
*/
|
|
__pte_index_size = RADIX_PTE_INDEX_SIZE;
|
|
__pmd_index_size = RADIX_PMD_INDEX_SIZE;
|
|
__pud_index_size = RADIX_PUD_INDEX_SIZE;
|
|
__pgd_index_size = RADIX_PGD_INDEX_SIZE;
|
|
__pud_cache_index = RADIX_PUD_INDEX_SIZE;
|
|
__pmd_cache_index = RADIX_PMD_INDEX_SIZE;
|
|
__pte_table_size = RADIX_PTE_TABLE_SIZE;
|
|
__pmd_table_size = RADIX_PMD_TABLE_SIZE;
|
|
__pud_table_size = RADIX_PUD_TABLE_SIZE;
|
|
__pgd_table_size = RADIX_PGD_TABLE_SIZE;
|
|
|
|
__pmd_val_bits = RADIX_PMD_VAL_BITS;
|
|
__pud_val_bits = RADIX_PUD_VAL_BITS;
|
|
__pgd_val_bits = RADIX_PGD_VAL_BITS;
|
|
|
|
__kernel_virt_start = RADIX_KERN_VIRT_START;
|
|
__kernel_virt_size = RADIX_KERN_VIRT_SIZE;
|
|
__vmalloc_start = RADIX_VMALLOC_START;
|
|
__vmalloc_end = RADIX_VMALLOC_END;
|
|
__kernel_io_start = RADIX_KERN_IO_START;
|
|
vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
|
|
ioremap_bot = IOREMAP_BASE;
|
|
|
|
#ifdef CONFIG_PCI
|
|
pci_io_base = ISA_IO_BASE;
|
|
#endif
|
|
__pte_frag_nr = RADIX_PTE_FRAG_NR;
|
|
__pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
radix_init_native();
|
|
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
|
|
update_hid_for_radix();
|
|
lpcr = mfspr(SPRN_LPCR);
|
|
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
|
|
radix_init_partition_table();
|
|
radix_init_amor();
|
|
} else {
|
|
radix_init_pseries();
|
|
}
|
|
|
|
memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
|
|
|
|
radix_init_iamr();
|
|
radix_init_pgtable();
|
|
/* Switch to the guard PID before turning on MMU */
|
|
radix__switch_mmu_context(NULL, &init_mm);
|
|
if (cpu_has_feature(CPU_FTR_HVMODE))
|
|
tlbiel_all();
|
|
}
|
|
|
|
void radix__early_init_mmu_secondary(void)
|
|
{
|
|
unsigned long lpcr;
|
|
/*
|
|
* update partition table control register and UPRT
|
|
*/
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
|
|
if (cpu_has_feature(CPU_FTR_POWER9_DD1))
|
|
update_hid_for_radix();
|
|
|
|
lpcr = mfspr(SPRN_LPCR);
|
|
mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
|
|
|
|
mtspr(SPRN_PTCR,
|
|
__pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
|
|
radix_init_amor();
|
|
}
|
|
radix_init_iamr();
|
|
|
|
radix__switch_mmu_context(NULL, &init_mm);
|
|
if (cpu_has_feature(CPU_FTR_HVMODE))
|
|
tlbiel_all();
|
|
}
|
|
|
|
void radix__mmu_cleanup_all(void)
|
|
{
|
|
unsigned long lpcr;
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
lpcr = mfspr(SPRN_LPCR);
|
|
mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
|
|
mtspr(SPRN_PTCR, 0);
|
|
powernv_set_nmmu_ptcr(0);
|
|
radix__flush_tlb_all();
|
|
}
|
|
}
|
|
|
|
void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
|
phys_addr_t first_memblock_size)
|
|
{
|
|
/* We don't currently support the first MEMBLOCK not mapping 0
|
|
* physical on those processors
|
|
*/
|
|
BUG_ON(first_memblock_base != 0);
|
|
|
|
/*
|
|
* Radix mode is not limited by RMA / VRMA addressing.
|
|
*/
|
|
ppc64_rma_size = ULONG_MAX;
|
|
}
|
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG
|
|
static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
|
|
{
|
|
pte_t *pte;
|
|
int i;
|
|
|
|
for (i = 0; i < PTRS_PER_PTE; i++) {
|
|
pte = pte_start + i;
|
|
if (!pte_none(*pte))
|
|
return;
|
|
}
|
|
|
|
pte_free_kernel(&init_mm, pte_start);
|
|
pmd_clear(pmd);
|
|
}
|
|
|
|
static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
|
|
{
|
|
pmd_t *pmd;
|
|
int i;
|
|
|
|
for (i = 0; i < PTRS_PER_PMD; i++) {
|
|
pmd = pmd_start + i;
|
|
if (!pmd_none(*pmd))
|
|
return;
|
|
}
|
|
|
|
pmd_free(&init_mm, pmd_start);
|
|
pud_clear(pud);
|
|
}
|
|
|
|
struct change_mapping_params {
|
|
pte_t *pte;
|
|
unsigned long start;
|
|
unsigned long end;
|
|
unsigned long aligned_start;
|
|
unsigned long aligned_end;
|
|
};
|
|
|
|
static int __meminit stop_machine_change_mapping(void *data)
|
|
{
|
|
struct change_mapping_params *params =
|
|
(struct change_mapping_params *)data;
|
|
|
|
if (!data)
|
|
return -1;
|
|
|
|
spin_unlock(&init_mm.page_table_lock);
|
|
pte_clear(&init_mm, params->aligned_start, params->pte);
|
|
create_physical_mapping(params->aligned_start, params->start, -1);
|
|
create_physical_mapping(params->end, params->aligned_end, -1);
|
|
spin_lock(&init_mm.page_table_lock);
|
|
return 0;
|
|
}
|
|
|
|
static void remove_pte_table(pte_t *pte_start, unsigned long addr,
|
|
unsigned long end)
|
|
{
|
|
unsigned long next;
|
|
pte_t *pte;
|
|
|
|
pte = pte_start + pte_index(addr);
|
|
for (; addr < end; addr = next, pte++) {
|
|
next = (addr + PAGE_SIZE) & PAGE_MASK;
|
|
if (next > end)
|
|
next = end;
|
|
|
|
if (!pte_present(*pte))
|
|
continue;
|
|
|
|
if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
|
|
/*
|
|
* The vmemmap_free() and remove_section_mapping()
|
|
* codepaths call us with aligned addresses.
|
|
*/
|
|
WARN_ONCE(1, "%s: unaligned range\n", __func__);
|
|
continue;
|
|
}
|
|
|
|
pte_clear(&init_mm, addr, pte);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* clear the pte and potentially split the mapping helper
|
|
*/
|
|
static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
|
|
unsigned long size, pte_t *pte)
|
|
{
|
|
unsigned long mask = ~(size - 1);
|
|
unsigned long aligned_start = addr & mask;
|
|
unsigned long aligned_end = addr + size;
|
|
struct change_mapping_params params;
|
|
bool split_region = false;
|
|
|
|
if ((end - addr) < size) {
|
|
/*
|
|
* We're going to clear the PTE, but not flushed
|
|
* the mapping, time to remap and flush. The
|
|
* effects if visible outside the processor or
|
|
* if we are running in code close to the
|
|
* mapping we cleared, we are in trouble.
|
|
*/
|
|
if (overlaps_kernel_text(aligned_start, addr) ||
|
|
overlaps_kernel_text(end, aligned_end)) {
|
|
/*
|
|
* Hack, just return, don't pte_clear
|
|
*/
|
|
WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
|
|
"text, not splitting\n", addr, end);
|
|
return;
|
|
}
|
|
split_region = true;
|
|
}
|
|
|
|
if (split_region) {
|
|
params.pte = pte;
|
|
params.start = addr;
|
|
params.end = end;
|
|
params.aligned_start = addr & ~(size - 1);
|
|
params.aligned_end = min_t(unsigned long, aligned_end,
|
|
(unsigned long)__va(memblock_end_of_DRAM()));
|
|
stop_machine(stop_machine_change_mapping, ¶ms, NULL);
|
|
return;
|
|
}
|
|
|
|
pte_clear(&init_mm, addr, pte);
|
|
}
|
|
|
|
static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
|
|
unsigned long end)
|
|
{
|
|
unsigned long next;
|
|
pte_t *pte_base;
|
|
pmd_t *pmd;
|
|
|
|
pmd = pmd_start + pmd_index(addr);
|
|
for (; addr < end; addr = next, pmd++) {
|
|
next = pmd_addr_end(addr, end);
|
|
|
|
if (!pmd_present(*pmd))
|
|
continue;
|
|
|
|
if (pmd_huge(*pmd)) {
|
|
split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
|
|
continue;
|
|
}
|
|
|
|
pte_base = (pte_t *)pmd_page_vaddr(*pmd);
|
|
remove_pte_table(pte_base, addr, next);
|
|
free_pte_table(pte_base, pmd);
|
|
}
|
|
}
|
|
|
|
static void remove_pud_table(pud_t *pud_start, unsigned long addr,
|
|
unsigned long end)
|
|
{
|
|
unsigned long next;
|
|
pmd_t *pmd_base;
|
|
pud_t *pud;
|
|
|
|
pud = pud_start + pud_index(addr);
|
|
for (; addr < end; addr = next, pud++) {
|
|
next = pud_addr_end(addr, end);
|
|
|
|
if (!pud_present(*pud))
|
|
continue;
|
|
|
|
if (pud_huge(*pud)) {
|
|
split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
|
|
continue;
|
|
}
|
|
|
|
pmd_base = (pmd_t *)pud_page_vaddr(*pud);
|
|
remove_pmd_table(pmd_base, addr, next);
|
|
free_pmd_table(pmd_base, pud);
|
|
}
|
|
}
|
|
|
|
static void __meminit remove_pagetable(unsigned long start, unsigned long end)
|
|
{
|
|
unsigned long addr, next;
|
|
pud_t *pud_base;
|
|
pgd_t *pgd;
|
|
|
|
spin_lock(&init_mm.page_table_lock);
|
|
|
|
for (addr = start; addr < end; addr = next) {
|
|
next = pgd_addr_end(addr, end);
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
if (!pgd_present(*pgd))
|
|
continue;
|
|
|
|
if (pgd_huge(*pgd)) {
|
|
split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
|
|
continue;
|
|
}
|
|
|
|
pud_base = (pud_t *)pgd_page_vaddr(*pgd);
|
|
remove_pud_table(pud_base, addr, next);
|
|
}
|
|
|
|
spin_unlock(&init_mm.page_table_lock);
|
|
radix__flush_tlb_kernel_range(start, end);
|
|
}
|
|
|
|
int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
|
|
{
|
|
return create_physical_mapping(start, end, nid);
|
|
}
|
|
|
|
int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
|
|
{
|
|
remove_pagetable(start, end);
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_MEMORY_HOTPLUG */
|
|
|
|
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
|
static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
|
|
pgprot_t flags, unsigned int map_page_size,
|
|
int nid)
|
|
{
|
|
return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
|
|
}
|
|
|
|
int __meminit radix__vmemmap_create_mapping(unsigned long start,
|
|
unsigned long page_size,
|
|
unsigned long phys)
|
|
{
|
|
/* Create a PTE encoding */
|
|
unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
|
|
int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
|
|
int ret;
|
|
|
|
ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
|
|
BUG_ON(ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG
|
|
void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
|
|
{
|
|
remove_pagetable(start, start + page_size);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
|
|
unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
|
|
pmd_t *pmdp, unsigned long clr,
|
|
unsigned long set)
|
|
{
|
|
unsigned long old;
|
|
|
|
#ifdef CONFIG_DEBUG_VM
|
|
WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
|
|
assert_spin_locked(&mm->page_table_lock);
|
|
#endif
|
|
|
|
old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
|
|
trace_hugepage_update(addr, old, clr, set);
|
|
|
|
return old;
|
|
}
|
|
|
|
pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
|
|
pmd_t *pmdp)
|
|
|
|
{
|
|
pmd_t pmd;
|
|
|
|
VM_BUG_ON(address & ~HPAGE_PMD_MASK);
|
|
VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
|
|
VM_BUG_ON(pmd_devmap(*pmdp));
|
|
/*
|
|
* khugepaged calls this for normal pmd
|
|
*/
|
|
pmd = *pmdp;
|
|
pmd_clear(pmdp);
|
|
|
|
/*FIXME!! Verify whether we need this kick below */
|
|
serialize_against_pte_lookup(vma->vm_mm);
|
|
|
|
radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
|
|
|
|
return pmd;
|
|
}
|
|
|
|
/*
|
|
* For us pgtable_t is pte_t *. Inorder to save the deposisted
|
|
* page table, we consider the allocated page table as a list
|
|
* head. On withdraw we need to make sure we zero out the used
|
|
* list_head memory area.
|
|
*/
|
|
void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
|
|
pgtable_t pgtable)
|
|
{
|
|
struct list_head *lh = (struct list_head *) pgtable;
|
|
|
|
assert_spin_locked(pmd_lockptr(mm, pmdp));
|
|
|
|
/* FIFO */
|
|
if (!pmd_huge_pte(mm, pmdp))
|
|
INIT_LIST_HEAD(lh);
|
|
else
|
|
list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
|
|
pmd_huge_pte(mm, pmdp) = pgtable;
|
|
}
|
|
|
|
pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
|
|
{
|
|
pte_t *ptep;
|
|
pgtable_t pgtable;
|
|
struct list_head *lh;
|
|
|
|
assert_spin_locked(pmd_lockptr(mm, pmdp));
|
|
|
|
/* FIFO */
|
|
pgtable = pmd_huge_pte(mm, pmdp);
|
|
lh = (struct list_head *) pgtable;
|
|
if (list_empty(lh))
|
|
pmd_huge_pte(mm, pmdp) = NULL;
|
|
else {
|
|
pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
|
|
list_del(lh);
|
|
}
|
|
ptep = (pte_t *) pgtable;
|
|
*ptep = __pte(0);
|
|
ptep++;
|
|
*ptep = __pte(0);
|
|
return pgtable;
|
|
}
|
|
|
|
|
|
pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
|
|
unsigned long addr, pmd_t *pmdp)
|
|
{
|
|
pmd_t old_pmd;
|
|
unsigned long old;
|
|
|
|
old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
|
|
old_pmd = __pmd(old);
|
|
/*
|
|
* Serialize against find_current_mm_pte which does lock-less
|
|
* lookup in page tables with local interrupts disabled. For huge pages
|
|
* it casts pmd_t to pte_t. Since format of pte_t is different from
|
|
* pmd_t we want to prevent transit from pmd pointing to page table
|
|
* to pmd pointing to huge page (and back) while interrupts are disabled.
|
|
* We clear pmd to possibly replace it with page table pointer in
|
|
* different code paths. So make sure we wait for the parallel
|
|
* find_current_mm_pte to finish.
|
|
*/
|
|
serialize_against_pte_lookup(mm);
|
|
return old_pmd;
|
|
}
|
|
|
|
int radix__has_transparent_hugepage(void)
|
|
{
|
|
/* For radix 2M at PMD level means thp */
|
|
if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|