mirror of https://gitee.com/openkylin/linux.git
245 lines
6.2 KiB
C
245 lines
6.2 KiB
C
/*
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* ARC FPGA Platform support code
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*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/console.h>
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#include <linux/of_platform.h>
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#include <asm/setup.h>
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#include <asm/clk.h>
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#include <asm/mach_desc.h>
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#include <plat/memmap.h>
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#include <plat/smp.h>
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#include <plat/irq.h>
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/*-----------------------BVCI Latency Unit -----------------------------*/
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#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT
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int lat_cycles = CONFIG_BVCI_LAT_CYCLES;
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/* BVCI Bus Profiler: Latency Unit */
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static void __init setup_bvci_lat_unit(void)
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{
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#define MAX_BVCI_UNITS 12
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unsigned int i;
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unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE;
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const unsigned long units_req = CONFIG_BVCI_LAT_UNITS;
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const unsigned int REG_UNIT = 21;
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const unsigned int REG_VAL = 22;
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/*
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* There are multiple Latency Units corresponding to the many
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* interfaces of the system bus arbiter (both CPU side as well as
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* the peripheral side).
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*
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* Unit 0 - System Arb and Mem Controller - adds latency to all
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* memory trasactions
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* Unit 1 - I$ and System Bus
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* Unit 2 - D$ and System Bus
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* ..
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* Unit 12 - IDE Disk controller and System Bus
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*
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* The programmers model requires writing to lat_unit reg first
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* and then the latency value (cycles) to lat_value reg
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*/
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if (CONFIG_BVCI_LAT_UNITS == 0) {
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writel(0, base + REG_UNIT);
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writel(lat_cycles, base + REG_VAL);
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pr_info("BVCI Latency for all Memory Transactions %d cycles\n",
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lat_cycles);
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} else {
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for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) {
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writel(i + 1, base + REG_UNIT); /* loop is 0 based */
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writel(lat_cycles, base + REG_VAL);
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pr_info("BVCI Latency for Unit[%d] = %d cycles\n",
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(i + 1), lat_cycles);
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}
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}
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}
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#else
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static void __init setup_bvci_lat_unit(void)
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{
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}
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#endif
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/*----------------------- Platform Devices -----------------------------*/
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#if IS_ENABLED(CONFIG_SERIAL_ARC)
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static unsigned long arc_uart_info[] = {
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0, /* uart->is_emulated (runtime @running_on_hw) */
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0, /* uart->port.uartclk */
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0, /* uart->baud */
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0
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};
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#if defined(CONFIG_SERIAL_ARC_CONSOLE)
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/*
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* static platform data - but only for early serial
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* TBD: derive this from a special DT node
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*/
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static struct resource arc_uart0_res[] = {
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{
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.start = UART0_BASE,
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.end = UART0_BASE + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = UART0_IRQ,
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.end = UART0_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device arc_uart0_dev = {
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.name = "arc-uart",
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.id = 0,
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.num_resources = ARRAY_SIZE(arc_uart0_res),
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.resource = arc_uart0_res,
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.dev = {
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.platform_data = &arc_uart_info,
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},
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};
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static struct platform_device *fpga_early_devs[] __initdata = {
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&arc_uart0_dev,
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};
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#endif /* CONFIG_SERIAL_ARC_CONSOLE */
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static void arc_fpga_serial_init(void)
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{
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/* To let driver workaround ISS bug: baudh Reg can't be set to 0 */
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arc_uart_info[0] = !running_on_hw;
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arc_uart_info[1] = arc_get_core_freq();
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arc_uart_info[2] = CONFIG_ARC_SERIAL_BAUD;
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#if defined(CONFIG_SERIAL_ARC_CONSOLE)
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early_platform_add_devices(fpga_early_devs,
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ARRAY_SIZE(fpga_early_devs));
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/*
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* ARC console driver registers itself as an early platform driver
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* of class "earlyprintk".
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* Install it here, followed by probe of devices.
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* The installation here doesn't require earlyprintk in command line
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* To do so however, replace the lines below with
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* parse_early_param();
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* early_platform_driver_probe("earlyprintk", 1, 1);
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* ^^
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*/
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early_platform_driver_register_all("earlyprintk");
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early_platform_driver_probe("earlyprintk", 1, 0);
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/*
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* This is to make sure that arc uart would be preferred console
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* despite one/more of following:
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* -command line lacked "console=ttyARC0" or
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* -CONFIG_VT_CONSOLE was enabled (for no reason whatsoever)
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* Note that this needs to be done after above early console is reg,
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* otherwise the early console never gets a chance to run.
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*/
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add_preferred_console("ttyARC", 0, "115200");
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#endif /* CONFIG_SERIAL_ARC_CONSOLE */
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}
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#else /* !IS_ENABLED(CONFIG_SERIAL_ARC) */
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static void arc_fpga_serial_init(void)
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{
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}
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#endif
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static void __init plat_fpga_early_init(void)
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{
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pr_info("[plat-arcfpga]: registering early dev resources\n");
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setup_bvci_lat_unit();
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arc_fpga_serial_init();
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#ifdef CONFIG_SMP
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iss_model_init_early_smp();
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#endif
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}
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static struct of_dev_auxdata plat_auxdata_lookup[] __initdata = {
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#if IS_ENABLED(CONFIG_SERIAL_ARC)
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OF_DEV_AUXDATA("snps,arc-uart", UART0_BASE, "arc-uart", arc_uart_info),
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#endif
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{}
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};
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static void __init plat_fpga_populate_dev(void)
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{
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pr_info("[plat-arcfpga]: registering device resources\n");
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/*
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* Traverses flattened DeviceTree - registering platform devices
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* complete with their resources
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*/
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of_platform_populate(NULL, of_default_bus_match_table,
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plat_auxdata_lookup, NULL);
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}
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/*----------------------- Machine Descriptions ------------------------------
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*
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* Machine description is simply a set of platform/board specific callbacks
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* This is not directly related to DeviceTree based dynamic device creation,
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* however as part of early device tree scan, we also select the right
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* callback set, by matching the DT compatible name.
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*/
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static const char *aa4_compat[] __initconst = {
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"snps,arc-angel4",
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NULL,
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};
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MACHINE_START(ANGEL4, "angel4")
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.dt_compat = aa4_compat,
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.init_early = plat_fpga_early_init,
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.init_machine = plat_fpga_populate_dev,
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.init_irq = plat_fpga_init_IRQ,
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#ifdef CONFIG_SMP
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.init_smp = iss_model_init_smp,
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#endif
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MACHINE_END
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static const char *ml509_compat[] __initconst = {
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"snps,arc-ml509",
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NULL,
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};
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MACHINE_START(ML509, "ml509")
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.dt_compat = ml509_compat,
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.init_early = plat_fpga_early_init,
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.init_machine = plat_fpga_populate_dev,
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.init_irq = plat_fpga_init_IRQ,
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#ifdef CONFIG_SMP
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.init_smp = iss_model_init_smp,
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#endif
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MACHINE_END
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static const char *nsimosci_compat[] __initconst = {
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"snps,nsimosci",
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NULL,
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};
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MACHINE_START(NSIMOSCI, "nsimosci")
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.dt_compat = nsimosci_compat,
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.init_early = NULL,
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.init_machine = plat_fpga_populate_dev,
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.init_irq = NULL,
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MACHINE_END
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