mirror of https://gitee.com/openkylin/linux.git
71f32f56cb
The USB controller/phy clocks and reset controls are in a separate address block, unlike previous SoCs where they were in the clock controller. Also, access to the address block is controlled by a clock gate to AHB. Add support for resets requiring a clock to be enabled when asserting/deasserting the reset controls, and add the sun9i USB clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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| .. | ||
| Makefile | ||
| clk-a10-hosc.c | ||
| clk-a20-gmac.c | ||
| clk-factors.c | ||
| clk-factors.h | ||
| clk-mod0.c | ||
| clk-sun6i-apb0-gates.c | ||
| clk-sun6i-apb0.c | ||
| clk-sun6i-ar100.c | ||
| clk-sun8i-apb0.c | ||
| clk-sun8i-mbus.c | ||
| clk-sun9i-core.c | ||
| clk-sun9i-mmc.c | ||
| clk-sunxi.c | ||
| clk-usb.c | ||