mirror of https://gitee.com/openkylin/linux.git
668 lines
16 KiB
C
668 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2014-2018 Broadcom */
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#include <drm/drmP.h>
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#include <drm/drm_syncobj.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/sched/signal.h>
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#include "uapi/drm/v3d_drm.h"
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#include "v3d_trace.h"
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static void
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v3d_init_core(struct v3d_dev *v3d, int core)
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{
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/* Set OVRTMUOUT, which means that the texture sampler uniform
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* configuration's tmu output type field is used, instead of
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* using the hardware default behavior based on the texture
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* type. If you want the default behavior, you can still put
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* "2" in the indirect texture state's output_type field.
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*/
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V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
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/* Whenever we flush the L2T cache, we always want to flush
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* the whole thing.
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*/
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V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0);
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V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0);
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}
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/* Sets invariant state for the HW. */
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static void
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v3d_init_hw_state(struct v3d_dev *v3d)
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{
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v3d_init_core(v3d, 0);
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}
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static void
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v3d_idle_axi(struct v3d_dev *v3d, int core)
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{
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V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
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if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
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(V3D_GMP_STATUS_RD_COUNT_MASK |
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V3D_GMP_STATUS_WR_COUNT_MASK |
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V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
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DRM_ERROR("Failed to wait for safe GMP shutdown\n");
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}
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}
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static void
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v3d_idle_gca(struct v3d_dev *v3d)
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{
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if (v3d->ver >= 41)
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return;
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V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
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if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
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V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) ==
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V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) {
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DRM_ERROR("Failed to wait for safe GCA shutdown\n");
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}
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}
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static void
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v3d_reset_v3d(struct v3d_dev *v3d)
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{
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int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION);
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if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) {
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V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0,
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V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT);
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V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0);
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/* GFXH-1383: The SW_INIT may cause a stray write to address 0
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* of the unit, so reset it to its power-on value here.
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*/
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V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK);
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} else {
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WARN_ON_ONCE(V3D_GET_FIELD(version,
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V3D_TOP_GR_BRIDGE_MAJOR) != 7);
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V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1,
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V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT);
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V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0);
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}
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v3d_init_hw_state(v3d);
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}
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void
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v3d_reset(struct v3d_dev *v3d)
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{
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struct drm_device *dev = &v3d->drm;
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DRM_ERROR("Resetting GPU.\n");
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trace_v3d_reset_begin(dev);
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/* XXX: only needed for safe powerdown, not reset. */
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if (false)
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v3d_idle_axi(v3d, 0);
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v3d_idle_gca(v3d);
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v3d_reset_v3d(v3d);
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v3d_mmu_set_page_table(v3d);
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v3d_irq_reset(v3d);
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trace_v3d_reset_end(dev);
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}
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static void
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v3d_flush_l3(struct v3d_dev *v3d)
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{
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if (v3d->ver < 41) {
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u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
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V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
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gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
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if (v3d->ver < 33) {
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V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
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gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
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}
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}
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}
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/* Invalidates the (read-only) L2 cache. */
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static void
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v3d_invalidate_l2(struct v3d_dev *v3d, int core)
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{
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V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
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V3D_L2CACTL_L2CCLR |
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V3D_L2CACTL_L2CENA);
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}
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static void
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v3d_invalidate_l1td(struct v3d_dev *v3d, int core)
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{
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V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
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if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
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V3D_L2TCACTL_L2TFLS), 100)) {
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DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
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}
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}
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/* Invalidates texture L2 cachelines */
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static void
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v3d_flush_l2t(struct v3d_dev *v3d, int core)
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{
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v3d_invalidate_l1td(v3d, core);
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V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
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V3D_L2TCACTL_L2TFLS |
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V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
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if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
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V3D_L2TCACTL_L2TFLS), 100)) {
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DRM_ERROR("Timeout waiting for L2T flush\n");
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}
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}
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/* Invalidates the slice caches. These are read-only caches. */
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static void
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v3d_invalidate_slices(struct v3d_dev *v3d, int core)
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{
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V3D_CORE_WRITE(core, V3D_CTL_SLCACTL,
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V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) |
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V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) |
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V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
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V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC));
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}
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/* Invalidates texture L2 cachelines */
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static void
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v3d_invalidate_l2t(struct v3d_dev *v3d, int core)
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{
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V3D_CORE_WRITE(core,
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V3D_CTL_L2TCACTL,
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V3D_L2TCACTL_L2TFLS |
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V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAR, V3D_L2TCACTL_FLM));
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if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
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V3D_L2TCACTL_L2TFLS), 100)) {
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DRM_ERROR("Timeout waiting for L2T invalidate\n");
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}
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}
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void
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v3d_invalidate_caches(struct v3d_dev *v3d)
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{
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v3d_flush_l3(v3d);
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v3d_invalidate_l2(v3d, 0);
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v3d_invalidate_slices(v3d, 0);
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v3d_flush_l2t(v3d, 0);
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}
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void
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v3d_flush_caches(struct v3d_dev *v3d)
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{
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v3d_invalidate_l1td(v3d, 0);
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v3d_invalidate_l2t(v3d, 0);
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}
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static void
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v3d_attach_object_fences(struct v3d_exec_info *exec)
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{
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struct dma_fence *out_fence = &exec->render.base.s_fence->finished;
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struct v3d_bo *bo;
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int i;
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for (i = 0; i < exec->bo_count; i++) {
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bo = to_v3d_bo(&exec->bo[i]->base);
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/* XXX: Use shared fences for read-only objects. */
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reservation_object_add_excl_fence(bo->resv, out_fence);
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}
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}
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static void
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v3d_unlock_bo_reservations(struct drm_device *dev,
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struct v3d_exec_info *exec,
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struct ww_acquire_ctx *acquire_ctx)
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{
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int i;
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for (i = 0; i < exec->bo_count; i++) {
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struct v3d_bo *bo = to_v3d_bo(&exec->bo[i]->base);
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ww_mutex_unlock(&bo->resv->lock);
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}
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ww_acquire_fini(acquire_ctx);
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}
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/* Takes the reservation lock on all the BOs being referenced, so that
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* at queue submit time we can update the reservations.
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*
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* We don't lock the RCL the tile alloc/state BOs, or overflow memory
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* (all of which are on exec->unref_list). They're entirely private
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* to v3d, so we don't attach dma-buf fences to them.
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*/
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static int
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v3d_lock_bo_reservations(struct drm_device *dev,
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struct v3d_exec_info *exec,
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struct ww_acquire_ctx *acquire_ctx)
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{
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int contended_lock = -1;
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int i, ret;
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struct v3d_bo *bo;
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ww_acquire_init(acquire_ctx, &reservation_ww_class);
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retry:
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if (contended_lock != -1) {
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bo = to_v3d_bo(&exec->bo[contended_lock]->base);
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ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
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acquire_ctx);
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if (ret) {
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ww_acquire_done(acquire_ctx);
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return ret;
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}
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}
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for (i = 0; i < exec->bo_count; i++) {
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if (i == contended_lock)
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continue;
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bo = to_v3d_bo(&exec->bo[i]->base);
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ret = ww_mutex_lock_interruptible(&bo->resv->lock, acquire_ctx);
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if (ret) {
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int j;
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for (j = 0; j < i; j++) {
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bo = to_v3d_bo(&exec->bo[j]->base);
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ww_mutex_unlock(&bo->resv->lock);
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}
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if (contended_lock != -1 && contended_lock >= i) {
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bo = to_v3d_bo(&exec->bo[contended_lock]->base);
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ww_mutex_unlock(&bo->resv->lock);
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}
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if (ret == -EDEADLK) {
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contended_lock = i;
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goto retry;
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}
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ww_acquire_done(acquire_ctx);
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return ret;
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}
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}
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ww_acquire_done(acquire_ctx);
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/* Reserve space for our shared (read-only) fence references,
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* before we commit the CL to the hardware.
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*/
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for (i = 0; i < exec->bo_count; i++) {
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bo = to_v3d_bo(&exec->bo[i]->base);
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ret = reservation_object_reserve_shared(bo->resv);
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if (ret) {
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v3d_unlock_bo_reservations(dev, exec, acquire_ctx);
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return ret;
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}
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}
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return 0;
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}
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/**
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* v3d_cl_lookup_bos() - Sets up exec->bo[] with the GEM objects
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* referenced by the job.
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* @dev: DRM device
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* @file_priv: DRM file for this fd
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* @exec: V3D job being set up
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*
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* The command validator needs to reference BOs by their index within
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* the submitted job's BO list. This does the validation of the job's
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* BO list and reference counting for the lifetime of the job.
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*
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* Note that this function doesn't need to unreference the BOs on
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* failure, because that will happen at v3d_exec_cleanup() time.
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*/
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static int
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v3d_cl_lookup_bos(struct drm_device *dev,
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struct drm_file *file_priv,
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struct drm_v3d_submit_cl *args,
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struct v3d_exec_info *exec)
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{
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u32 *handles;
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int ret = 0;
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int i;
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exec->bo_count = args->bo_handle_count;
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if (!exec->bo_count) {
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/* See comment on bo_index for why we have to check
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* this.
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*/
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DRM_DEBUG("Rendering requires BOs\n");
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return -EINVAL;
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}
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exec->bo = kvmalloc_array(exec->bo_count,
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sizeof(struct drm_gem_cma_object *),
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GFP_KERNEL | __GFP_ZERO);
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if (!exec->bo) {
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DRM_DEBUG("Failed to allocate validated BO pointers\n");
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return -ENOMEM;
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}
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handles = kvmalloc_array(exec->bo_count, sizeof(u32), GFP_KERNEL);
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if (!handles) {
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ret = -ENOMEM;
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DRM_DEBUG("Failed to allocate incoming GEM handles\n");
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goto fail;
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}
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if (copy_from_user(handles,
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(void __user *)(uintptr_t)args->bo_handles,
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exec->bo_count * sizeof(u32))) {
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ret = -EFAULT;
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DRM_DEBUG("Failed to copy in GEM handles\n");
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goto fail;
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}
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spin_lock(&file_priv->table_lock);
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for (i = 0; i < exec->bo_count; i++) {
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struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
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handles[i]);
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if (!bo) {
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DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
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i, handles[i]);
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ret = -ENOENT;
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spin_unlock(&file_priv->table_lock);
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goto fail;
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}
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drm_gem_object_get(bo);
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exec->bo[i] = to_v3d_bo(bo);
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}
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spin_unlock(&file_priv->table_lock);
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fail:
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kvfree(handles);
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return ret;
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}
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static void
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v3d_exec_cleanup(struct kref *ref)
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{
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struct v3d_exec_info *exec = container_of(ref, struct v3d_exec_info,
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refcount);
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struct v3d_dev *v3d = exec->v3d;
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unsigned int i;
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struct v3d_bo *bo, *save;
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dma_fence_put(exec->bin.in_fence);
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dma_fence_put(exec->render.in_fence);
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dma_fence_put(exec->bin.done_fence);
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dma_fence_put(exec->render.done_fence);
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dma_fence_put(exec->bin_done_fence);
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for (i = 0; i < exec->bo_count; i++)
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drm_gem_object_put_unlocked(&exec->bo[i]->base);
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kvfree(exec->bo);
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list_for_each_entry_safe(bo, save, &exec->unref_list, unref_head) {
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drm_gem_object_put_unlocked(&bo->base);
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}
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pm_runtime_mark_last_busy(v3d->dev);
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pm_runtime_put_autosuspend(v3d->dev);
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kfree(exec);
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}
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void v3d_exec_put(struct v3d_exec_info *exec)
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{
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kref_put(&exec->refcount, v3d_exec_cleanup);
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}
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int
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v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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int ret;
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struct drm_v3d_wait_bo *args = data;
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struct drm_gem_object *gem_obj;
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struct v3d_bo *bo;
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ktime_t start = ktime_get();
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u64 delta_ns;
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unsigned long timeout_jiffies =
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nsecs_to_jiffies_timeout(args->timeout_ns);
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if (args->pad != 0)
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return -EINVAL;
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gem_obj = drm_gem_object_lookup(file_priv, args->handle);
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if (!gem_obj) {
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DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
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return -EINVAL;
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}
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bo = to_v3d_bo(gem_obj);
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ret = reservation_object_wait_timeout_rcu(bo->resv,
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true, true,
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timeout_jiffies);
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if (ret == 0)
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ret = -ETIME;
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else if (ret > 0)
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ret = 0;
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/* Decrement the user's timeout, in case we got interrupted
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* such that the ioctl will be restarted.
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*/
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delta_ns = ktime_to_ns(ktime_sub(ktime_get(), start));
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if (delta_ns < args->timeout_ns)
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args->timeout_ns -= delta_ns;
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else
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args->timeout_ns = 0;
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/* Asked to wait beyond the jiffie/scheduler precision? */
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if (ret == -ETIME && args->timeout_ns)
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ret = -EAGAIN;
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drm_gem_object_put_unlocked(gem_obj);
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return ret;
|
|
}
|
|
|
|
/**
|
|
* v3d_submit_cl_ioctl() - Submits a job (frame) to the V3D.
|
|
* @dev: DRM device
|
|
* @data: ioctl argument
|
|
* @file_priv: DRM file for this fd
|
|
*
|
|
* This is the main entrypoint for userspace to submit a 3D frame to
|
|
* the GPU. Userspace provides the binner command list (if
|
|
* applicable), and the kernel sets up the render command list to draw
|
|
* to the framebuffer described in the ioctl, using the command lists
|
|
* that the 3D engine's binner will produce.
|
|
*/
|
|
int
|
|
v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct v3d_dev *v3d = to_v3d_dev(dev);
|
|
struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
|
|
struct drm_v3d_submit_cl *args = data;
|
|
struct v3d_exec_info *exec;
|
|
struct ww_acquire_ctx acquire_ctx;
|
|
struct drm_syncobj *sync_out;
|
|
int ret = 0;
|
|
|
|
if (args->pad != 0) {
|
|
DRM_INFO("pad must be zero: %d\n", args->pad);
|
|
return -EINVAL;
|
|
}
|
|
|
|
exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
|
|
if (!exec)
|
|
return -ENOMEM;
|
|
|
|
ret = pm_runtime_get_sync(v3d->dev);
|
|
if (ret < 0) {
|
|
kfree(exec);
|
|
return ret;
|
|
}
|
|
|
|
kref_init(&exec->refcount);
|
|
|
|
ret = drm_syncobj_find_fence(file_priv, args->in_sync_bcl,
|
|
0, &exec->bin.in_fence);
|
|
if (ret == -EINVAL)
|
|
goto fail;
|
|
|
|
ret = drm_syncobj_find_fence(file_priv, args->in_sync_rcl,
|
|
0, &exec->render.in_fence);
|
|
if (ret == -EINVAL)
|
|
goto fail;
|
|
|
|
exec->qma = args->qma;
|
|
exec->qms = args->qms;
|
|
exec->qts = args->qts;
|
|
exec->bin.exec = exec;
|
|
exec->bin.start = args->bcl_start;
|
|
exec->bin.end = args->bcl_end;
|
|
exec->render.exec = exec;
|
|
exec->render.start = args->rcl_start;
|
|
exec->render.end = args->rcl_end;
|
|
exec->v3d = v3d;
|
|
INIT_LIST_HEAD(&exec->unref_list);
|
|
|
|
ret = v3d_cl_lookup_bos(dev, file_priv, args, exec);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
ret = v3d_lock_bo_reservations(dev, exec, &acquire_ctx);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
mutex_lock(&v3d->sched_lock);
|
|
if (exec->bin.start != exec->bin.end) {
|
|
ret = drm_sched_job_init(&exec->bin.base,
|
|
&v3d_priv->sched_entity[V3D_BIN],
|
|
v3d_priv);
|
|
if (ret)
|
|
goto fail_unreserve;
|
|
|
|
exec->bin_done_fence =
|
|
dma_fence_get(&exec->bin.base.s_fence->finished);
|
|
|
|
kref_get(&exec->refcount); /* put by scheduler job completion */
|
|
drm_sched_entity_push_job(&exec->bin.base,
|
|
&v3d_priv->sched_entity[V3D_BIN]);
|
|
}
|
|
|
|
ret = drm_sched_job_init(&exec->render.base,
|
|
&v3d_priv->sched_entity[V3D_RENDER],
|
|
v3d_priv);
|
|
if (ret)
|
|
goto fail_unreserve;
|
|
|
|
kref_get(&exec->refcount); /* put by scheduler job completion */
|
|
drm_sched_entity_push_job(&exec->render.base,
|
|
&v3d_priv->sched_entity[V3D_RENDER]);
|
|
mutex_unlock(&v3d->sched_lock);
|
|
|
|
v3d_attach_object_fences(exec);
|
|
|
|
v3d_unlock_bo_reservations(dev, exec, &acquire_ctx);
|
|
|
|
/* Update the return sync object for the */
|
|
sync_out = drm_syncobj_find(file_priv, args->out_sync);
|
|
if (sync_out) {
|
|
drm_syncobj_replace_fence(sync_out, 0,
|
|
&exec->render.base.s_fence->finished);
|
|
drm_syncobj_put(sync_out);
|
|
}
|
|
|
|
v3d_exec_put(exec);
|
|
|
|
return 0;
|
|
|
|
fail_unreserve:
|
|
mutex_unlock(&v3d->sched_lock);
|
|
v3d_unlock_bo_reservations(dev, exec, &acquire_ctx);
|
|
fail:
|
|
v3d_exec_put(exec);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
v3d_gem_init(struct drm_device *dev)
|
|
{
|
|
struct v3d_dev *v3d = to_v3d_dev(dev);
|
|
u32 pt_size = 4096 * 1024;
|
|
int ret, i;
|
|
|
|
for (i = 0; i < V3D_MAX_QUEUES; i++)
|
|
v3d->queue[i].fence_context = dma_fence_context_alloc(1);
|
|
|
|
spin_lock_init(&v3d->mm_lock);
|
|
spin_lock_init(&v3d->job_lock);
|
|
mutex_init(&v3d->bo_lock);
|
|
mutex_init(&v3d->reset_lock);
|
|
mutex_init(&v3d->sched_lock);
|
|
|
|
/* Note: We don't allocate address 0. Various bits of HW
|
|
* treat 0 as special, such as the occlusion query counters
|
|
* where 0 means "disabled".
|
|
*/
|
|
drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1);
|
|
|
|
v3d->pt = dma_alloc_wc(v3d->dev, pt_size,
|
|
&v3d->pt_paddr,
|
|
GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
|
|
if (!v3d->pt) {
|
|
drm_mm_takedown(&v3d->mm);
|
|
dev_err(v3d->dev,
|
|
"Failed to allocate page tables. "
|
|
"Please ensure you have CMA enabled.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
v3d_init_hw_state(v3d);
|
|
v3d_mmu_set_page_table(v3d);
|
|
|
|
ret = v3d_sched_init(v3d);
|
|
if (ret) {
|
|
drm_mm_takedown(&v3d->mm);
|
|
dma_free_coherent(v3d->dev, 4096 * 1024, (void *)v3d->pt,
|
|
v3d->pt_paddr);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
v3d_gem_destroy(struct drm_device *dev)
|
|
{
|
|
struct v3d_dev *v3d = to_v3d_dev(dev);
|
|
|
|
v3d_sched_fini(v3d);
|
|
|
|
/* Waiting for exec to finish would need to be done before
|
|
* unregistering V3D.
|
|
*/
|
|
WARN_ON(v3d->bin_job);
|
|
WARN_ON(v3d->render_job);
|
|
|
|
drm_mm_takedown(&v3d->mm);
|
|
|
|
dma_free_coherent(v3d->dev, 4096 * 1024, (void *)v3d->pt, v3d->pt_paddr);
|
|
}
|