mirror of https://gitee.com/openkylin/linux.git
482 lines
11 KiB
C
482 lines
11 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef REG_ADDR_H
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#define REG_ADDR_H
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#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
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0
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#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
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0xfff << 0)
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#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
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12
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#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
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0xfff << 12)
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#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
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24
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#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
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0xff << 24)
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#define XSDM_REG_OPERATION_GEN \
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0xf80408UL
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#define NIG_REG_RX_BRB_OUT_EN \
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0x500e18UL
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#define NIG_REG_STORM_OUT_EN \
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0x500e08UL
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#define PSWRQ2_REG_L2P_VALIDATE_VFID \
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0x240c50UL
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#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
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0x2aae04UL
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#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
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0x2aa16cUL
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#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
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0x2aa118UL
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#define PSWHST_REG_ZONE_PERMISSION_TABLE \
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0x2a0800UL
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#define BAR0_MAP_REG_MSDM_RAM \
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0x1d00000UL
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#define BAR0_MAP_REG_USDM_RAM \
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0x1d80000UL
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#define BAR0_MAP_REG_PSDM_RAM \
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0x1f00000UL
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#define BAR0_MAP_REG_TSDM_RAM \
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0x1c80000UL
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#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
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0x5011f4UL
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#define PRS_REG_SEARCH_TCP \
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0x1f0400UL
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#define PRS_REG_SEARCH_UDP \
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0x1f0404UL
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#define PRS_REG_SEARCH_FCOE \
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0x1f0408UL
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#define PRS_REG_SEARCH_ROCE \
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0x1f040cUL
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#define PRS_REG_SEARCH_OPENFLOW \
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0x1f0434UL
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#define TM_REG_PF_ENABLE_CONN \
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0x2c043cUL
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#define TM_REG_PF_ENABLE_TASK \
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0x2c0444UL
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#define TM_REG_PF_SCAN_ACTIVE_CONN \
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0x2c04fcUL
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#define TM_REG_PF_SCAN_ACTIVE_TASK \
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0x2c0500UL
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#define IGU_REG_LEADING_EDGE_LATCH \
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0x18082cUL
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#define IGU_REG_TRAILING_EDGE_LATCH \
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0x180830UL
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#define QM_REG_USG_CNT_PF_TX \
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0x2f2eacUL
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#define QM_REG_USG_CNT_PF_OTHER \
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0x2f2eb0UL
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#define DORQ_REG_PF_DB_ENABLE \
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0x100508UL
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#define DORQ_REG_VF_USAGE_CNT \
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0x1009c4UL
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#define QM_REG_PF_EN \
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0x2f2ea4UL
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#define TCFC_REG_STRONG_ENABLE_PF \
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0x2d0708UL
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#define CCFC_REG_STRONG_ENABLE_PF \
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0x2e0708UL
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#define PGLUE_B_REG_PGL_ADDR_88_F0 \
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0x2aa404UL
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#define PGLUE_B_REG_PGL_ADDR_8C_F0 \
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0x2aa408UL
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#define PGLUE_B_REG_PGL_ADDR_90_F0 \
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0x2aa40cUL
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#define PGLUE_B_REG_PGL_ADDR_94_F0 \
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0x2aa410UL
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#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
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0x2aa138UL
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#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
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0x2aa174UL
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#define MISC_REG_GEN_PURP_CR0 \
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0x008c80UL
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#define MCP_REG_SCRATCH \
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0xe20000UL
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#define CNIG_REG_NW_PORT_MODE_BB_B0 \
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0x218200UL
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#define MISCS_REG_CHIP_NUM \
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0x00976cUL
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#define MISCS_REG_CHIP_REV \
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0x009770UL
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#define MISCS_REG_CMT_ENABLED_FOR_PAIR \
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0x00971cUL
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#define MISCS_REG_CHIP_TEST_REG \
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0x009778UL
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#define MISCS_REG_CHIP_METAL \
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0x009774UL
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#define MISCS_REG_FUNCTION_HIDE \
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0x0096f0UL
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#define BRB_REG_HEADER_SIZE \
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0x340804UL
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#define BTB_REG_HEADER_SIZE \
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0xdb0804UL
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#define CAU_REG_LONG_TIMEOUT_THRESHOLD \
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0x1c0708UL
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#define CCFC_REG_ACTIVITY_COUNTER \
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0x2e8800UL
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#define CCFC_REG_STRONG_ENABLE_VF \
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0x2e070cUL
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#define CDU_REG_CID_ADDR_PARAMS \
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0x580900UL
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#define DBG_REG_CLIENT_ENABLE \
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0x010004UL
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#define DMAE_REG_INIT \
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0x00c000UL
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#define DORQ_REG_IFEN \
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0x100040UL
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#define DORQ_REG_DB_DROP_REASON \
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0x100a2cUL
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#define DORQ_REG_DB_DROP_DETAILS \
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0x100a24UL
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#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
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0x100a1cUL
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#define GRC_REG_TIMEOUT_EN \
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0x050404UL
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#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
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0x050054UL
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#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
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0x05004cUL
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#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
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0x050050UL
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#define IGU_REG_BLOCK_CONFIGURATION \
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0x180040UL
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#define MCM_REG_INIT \
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0x1200000UL
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#define MCP2_REG_DBG_DWORD_ENABLE \
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0x052404UL
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#define MISC_REG_PORT_MODE \
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0x008c00UL
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#define MISCS_REG_CLK_100G_MODE \
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0x009070UL
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#define MSDM_REG_ENABLE_IN1 \
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0xfc0004UL
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#define MSEM_REG_ENABLE_IN \
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0x1800004UL
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#define NIG_REG_CM_HDR \
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0x500840UL
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#define NCSI_REG_CONFIG \
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0x040200UL
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#define PBF_REG_INIT \
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0xd80000UL
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#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
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0xd806c8UL
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#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
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0xd806ccUL
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#define PTU_REG_ATC_INIT_ARRAY \
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0x560000UL
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#define PCM_REG_INIT \
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0x1100000UL
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#define PGLUE_B_REG_ADMIN_PER_PF_REGION \
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0x2a9000UL
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#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
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0x2aa150UL
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#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
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0x2aa144UL
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#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
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0x2aa148UL
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#define PGLUE_B_REG_TX_ERR_WR_DETAILS \
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0x2aa14cUL
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#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
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0x2aa154UL
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#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
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0x2aa158UL
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#define PGLUE_B_REG_TX_ERR_RD_DETAILS \
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0x2aa15cUL
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#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
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0x2aa160UL
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#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
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0x2aa164UL
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#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
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0x2aa54cUL
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#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
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0x2aa544UL
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#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
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0x2aa548UL
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#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
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0x2aae74UL
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#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
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0x2aae78UL
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#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
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0x2aae7cUL
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#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
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0x2aae80UL
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#define PGLUE_B_REG_LATCHED_ERRORS_CLR \
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0x2aa3bcUL
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#define PRM_REG_DISABLE_PRM \
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0x230000UL
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#define PRS_REG_SOFT_RST \
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0x1f0000UL
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#define PSDM_REG_ENABLE_IN1 \
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0xfa0004UL
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#define PSEM_REG_ENABLE_IN \
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0x1600004UL
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#define PSWRQ_REG_DBG_SELECT \
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0x280020UL
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#define PSWRQ2_REG_CDUT_P_SIZE \
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0x24000cUL
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#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
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0x2a0040UL
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#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
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0x29e050UL
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#define PSWHST_REG_INCORRECT_ACCESS_VALID \
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0x2a0070UL
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#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
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0x2a0074UL
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#define PSWHST_REG_INCORRECT_ACCESS_DATA \
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0x2a0068UL
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#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
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0x2a006cUL
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#define PSWRD_REG_DBG_SELECT \
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0x29c040UL
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#define PSWRD2_REG_CONF11 \
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0x29d064UL
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#define PSWWR_REG_USDM_FULL_TH \
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0x29a040UL
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#define PSWWR2_REG_CDU_FULL_TH2 \
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0x29b040UL
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#define QM_REG_MAXPQSIZE_0 \
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0x2f0434UL
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#define RSS_REG_RSS_INIT_EN \
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0x238804UL
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#define RDIF_REG_STOP_ON_ERROR \
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0x300040UL
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#define SRC_REG_SOFT_RST \
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0x23874cUL
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#define TCFC_REG_ACTIVITY_COUNTER \
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0x2d8800UL
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#define TCM_REG_INIT \
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0x1180000UL
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#define TM_REG_PXP_READ_DATA_FIFO_INIT \
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0x2c0014UL
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#define TSDM_REG_ENABLE_IN1 \
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0xfb0004UL
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#define TSEM_REG_ENABLE_IN \
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0x1700004UL
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#define TDIF_REG_STOP_ON_ERROR \
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0x310040UL
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#define UCM_REG_INIT \
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0x1280000UL
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#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
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0x051004UL
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#define USDM_REG_ENABLE_IN1 \
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0xfd0004UL
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#define USEM_REG_ENABLE_IN \
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0x1900004UL
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#define XCM_REG_INIT \
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0x1000000UL
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#define XSDM_REG_ENABLE_IN1 \
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0xf80004UL
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#define XSEM_REG_ENABLE_IN \
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0x1400004UL
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#define YCM_REG_INIT \
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0x1080000UL
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#define YSDM_REG_ENABLE_IN1 \
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0xf90004UL
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#define YSEM_REG_ENABLE_IN \
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0x1500004UL
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#define XYLD_REG_SCBD_STRICT_PRIO \
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0x4c0000UL
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#define TMLD_REG_SCBD_STRICT_PRIO \
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0x4d0000UL
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#define MULD_REG_SCBD_STRICT_PRIO \
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0x4e0000UL
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#define YULD_REG_SCBD_STRICT_PRIO \
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0x4c8000UL
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#define MISC_REG_SHARED_MEM_ADDR \
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0x008c20UL
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#define DMAE_REG_GO_C0 \
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0x00c048UL
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#define DMAE_REG_GO_C1 \
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0x00c04cUL
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#define DMAE_REG_GO_C2 \
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0x00c050UL
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#define DMAE_REG_GO_C3 \
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0x00c054UL
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#define DMAE_REG_GO_C4 \
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0x00c058UL
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#define DMAE_REG_GO_C5 \
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0x00c05cUL
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#define DMAE_REG_GO_C6 \
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0x00c060UL
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#define DMAE_REG_GO_C7 \
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0x00c064UL
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#define DMAE_REG_GO_C8 \
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0x00c068UL
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#define DMAE_REG_GO_C9 \
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0x00c06cUL
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#define DMAE_REG_GO_C10 \
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0x00c070UL
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#define DMAE_REG_GO_C11 \
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0x00c074UL
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#define DMAE_REG_GO_C12 \
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0x00c078UL
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#define DMAE_REG_GO_C13 \
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0x00c07cUL
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#define DMAE_REG_GO_C14 \
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0x00c080UL
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#define DMAE_REG_GO_C15 \
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0x00c084UL
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#define DMAE_REG_GO_C16 \
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0x00c088UL
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#define DMAE_REG_GO_C17 \
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0x00c08cUL
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#define DMAE_REG_GO_C18 \
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0x00c090UL
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#define DMAE_REG_GO_C19 \
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0x00c094UL
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#define DMAE_REG_GO_C20 \
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0x00c098UL
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#define DMAE_REG_GO_C21 \
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0x00c09cUL
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#define DMAE_REG_GO_C22 \
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0x00c0a0UL
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#define DMAE_REG_GO_C23 \
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0x00c0a4UL
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#define DMAE_REG_GO_C24 \
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0x00c0a8UL
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#define DMAE_REG_GO_C25 \
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0x00c0acUL
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#define DMAE_REG_GO_C26 \
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0x00c0b0UL
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#define DMAE_REG_GO_C27 \
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0x00c0b4UL
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#define DMAE_REG_GO_C28 \
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0x00c0b8UL
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#define DMAE_REG_GO_C29 \
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0x00c0bcUL
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#define DMAE_REG_GO_C30 \
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0x00c0c0UL
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#define DMAE_REG_GO_C31 \
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0x00c0c4UL
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#define DMAE_REG_CMD_MEM \
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0x00c800UL
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#define QM_REG_MAXPQSIZETXSEL_0 \
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0x2f0440UL
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#define QM_REG_SDMCMDREADY \
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0x2f1e10UL
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#define QM_REG_SDMCMDADDR \
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0x2f1e04UL
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#define QM_REG_SDMCMDDATALSB \
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0x2f1e08UL
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#define QM_REG_SDMCMDDATAMSB \
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0x2f1e0cUL
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#define QM_REG_SDMCMDGO \
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0x2f1e14UL
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#define QM_REG_RLPFCRD \
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0x2f4d80UL
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#define QM_REG_RLPFINCVAL \
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0x2f4c80UL
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#define QM_REG_RLGLBLCRD \
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0x2f4400UL
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#define QM_REG_RLGLBLINCVAL \
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0x2f3400UL
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#define IGU_REG_ATTENTION_ENABLE \
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0x18083cUL
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#define IGU_REG_ATTN_MSG_ADDR_L \
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0x180820UL
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#define IGU_REG_ATTN_MSG_ADDR_H \
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0x180824UL
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#define MISC_REG_AEU_GENERAL_ATTN_0 \
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0x008400UL
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#define CAU_REG_SB_ADDR_MEMORY \
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0x1c8000UL
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#define CAU_REG_SB_VAR_MEMORY \
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0x1c6000UL
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#define CAU_REG_PI_MEMORY \
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0x1d0000UL
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#define IGU_REG_PF_CONFIGURATION \
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0x180800UL
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#define IGU_REG_VF_CONFIGURATION \
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0x180804UL
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#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
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0x00849cUL
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#define MISC_REG_AEU_AFTER_INVERT_1_IGU \
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0x0087b4UL
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#define MISC_REG_AEU_MASK_ATTN_IGU \
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0x008494UL
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#define IGU_REG_CLEANUP_STATUS_0 \
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0x180980UL
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#define IGU_REG_CLEANUP_STATUS_1 \
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0x180a00UL
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#define IGU_REG_CLEANUP_STATUS_2 \
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0x180a80UL
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#define IGU_REG_CLEANUP_STATUS_3 \
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0x180b00UL
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#define IGU_REG_CLEANUP_STATUS_4 \
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0x180b80UL
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#define IGU_REG_COMMAND_REG_32LSB_DATA \
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0x180840UL
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#define IGU_REG_COMMAND_REG_CTRL \
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0x180848UL
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#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
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0x1 << 1)
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#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
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0x1 << 0)
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#define IGU_REG_MAPPING_MEMORY \
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0x184000UL
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#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
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0x180408UL
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#define MISCS_REG_GENERIC_POR_0 \
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0x0096d4UL
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#define MCP_REG_NVM_CFG4 \
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0xe0642cUL
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#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
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0x7 << 0)
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#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
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0
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#define MCP_REG_CPU_STATE \
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0xe05004UL
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#define MCP_REG_CPU_EVENT_MASK \
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0xe05008UL
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#define PGLUE_B_REG_PF_BAR0_SIZE \
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0x2aae60UL
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#define PGLUE_B_REG_PF_BAR1_SIZE \
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0x2aae64UL
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#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
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#define PRS_REG_GRE_PROTOCOL 0x1f0734UL
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#define PRS_REG_VXLAN_PORT 0x1f0738UL
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#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
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#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
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#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
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#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
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#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
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#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
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#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
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#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
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#define NIG_REG_VXLAN_PORT 0x50105cUL
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#define PBF_REG_VXLAN_PORT 0xd80518UL
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#define PBF_REG_NGE_PORT 0xd8051cUL
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#define PRS_REG_NGE_PORT 0x1f086cUL
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#define NIG_REG_NGE_PORT 0x508b38UL
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#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
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#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
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#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
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#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
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#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
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#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
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#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
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#define NIG_REG_NGE_COMP_VER 0x508b30UL
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#define PBF_REG_NGE_COMP_VER 0xd80524UL
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#define PRS_REG_NGE_COMP_VER 0x1f0878UL
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#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
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#define QM_REG_WFQVPWEIGHT 0x2fa000UL
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#endif
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