mirror of https://gitee.com/openkylin/linux.git
643 lines
18 KiB
C
643 lines
18 KiB
C
/* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This file contains the Northstar plus (NSP) IOMUX driver that supports
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* group based PINMUX configuration. The Northstar plus IOMUX controller
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* allows pins to be individually muxed to GPIO function. The NAND and MMC is
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* a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
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* To select PWM, one need to enable the corresponding gpio_b as well.
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*
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* gpio_a (8 - 11)
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* +----------
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* |
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* gpio_a (8-11) | gpio_b (0 - 3)
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* ------------------------+-------+----------
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* |
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* | pwm (0 - 3)
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* +----------
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "../core.h"
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#include "../pinctrl-utils.h"
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#define NSP_MUX_BASE0 0x00
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#define NSP_MUX_BASE1 0x01
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#define NSP_MUX_BASE2 0x02
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/*
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* nsp IOMUX register description
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*
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* @base: base 0 or base 1
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* @shift: bit shift for mux configuration of a group
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* @mask: bit mask of the function
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* @alt: alternate function to set to
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*/
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struct nsp_mux {
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unsigned int base;
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unsigned int shift;
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unsigned int mask;
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unsigned int alt;
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};
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/*
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* Keep track of nsp IOMUX configuration and prevent double configuration
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*
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* @nsp_mux: nsp IOMUX register description
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* @is_configured: flag to indicate whether a mux setting has already been
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* configured
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*/
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struct nsp_mux_log {
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struct nsp_mux mux;
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bool is_configured;
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};
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/*
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* Group based IOMUX configuration
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*
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* @name: name of the group
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* @pins: array of pins used by this group
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* @num_pins: total number of pins used by this group
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* @mux: nsp group based IOMUX configuration
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*/
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struct nsp_pin_group {
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const char *name;
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const unsigned int *pins;
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const unsigned int num_pins;
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const struct nsp_mux mux;
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};
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/*
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* nsp mux function and supported pin groups
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*
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* @name: name of the function
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* @groups: array of groups that can be supported by this function
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* @num_groups: total number of groups that can be supported by this function
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*/
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struct nsp_pin_function {
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const char *name;
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const char * const *groups;
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const unsigned int num_groups;
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};
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/*
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* nsp IOMUX pinctrl core
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*
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* @pctl: pointer to pinctrl_dev
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* @dev: pointer to device
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* @base0: first mux register
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* @base1: second mux register
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* @base2: third mux register
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* @groups: pointer to array of groups
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* @num_groups: total number of groups
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* @functions: pointer to array of functions
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* @num_functions: total number of functions
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* @mux_log: pointer to the array of mux logs
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* @lock: lock to protect register access
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*/
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struct nsp_pinctrl {
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struct pinctrl_dev *pctl;
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struct device *dev;
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void __iomem *base0;
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void __iomem *base1;
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void __iomem *base2;
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const struct nsp_pin_group *groups;
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unsigned int num_groups;
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const struct nsp_pin_function *functions;
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unsigned int num_functions;
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struct nsp_mux_log *mux_log;
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spinlock_t lock;
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};
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/*
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* Description of a pin in nsp
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*
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* @pin: pin number
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* @name: pin name
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* @gpio_select: reg data to select GPIO
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*/
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struct nsp_pin {
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unsigned int pin;
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char *name;
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unsigned int gpio_select;
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};
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#define NSP_PIN_DESC(p, n, g) \
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{ \
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.pin = p, \
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.name = n, \
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.gpio_select = g, \
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}
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/*
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* List of muxable pins in nsp
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*/
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static struct nsp_pin nsp_pins[] = {
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NSP_PIN_DESC(0, "spi_clk", 1),
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NSP_PIN_DESC(1, "spi_ss", 1),
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NSP_PIN_DESC(2, "spi_mosi", 1),
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NSP_PIN_DESC(3, "spi_miso", 1),
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NSP_PIN_DESC(4, "scl", 1),
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NSP_PIN_DESC(5, "sda", 1),
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NSP_PIN_DESC(6, "mdc", 1),
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NSP_PIN_DESC(7, "mdio", 1),
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NSP_PIN_DESC(8, "pwm0", 1),
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NSP_PIN_DESC(9, "pwm1", 1),
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NSP_PIN_DESC(10, "pwm2", 1),
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NSP_PIN_DESC(11, "pwm3", 1),
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NSP_PIN_DESC(12, "uart1_rx", 1),
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NSP_PIN_DESC(13, "uart1_tx", 1),
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NSP_PIN_DESC(14, "uart1_cts", 1),
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NSP_PIN_DESC(15, "uart1_rts", 1),
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NSP_PIN_DESC(16, "uart2_rx", 1),
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NSP_PIN_DESC(17, "uart2_tx", 1),
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NSP_PIN_DESC(18, "synce", 0),
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NSP_PIN_DESC(19, "sata0_led", 0),
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NSP_PIN_DESC(20, "sata1_led", 0),
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NSP_PIN_DESC(21, "xtal_out", 1),
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NSP_PIN_DESC(22, "sdio_pwr", 1),
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NSP_PIN_DESC(23, "sdio_en_1p8v", 1),
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NSP_PIN_DESC(24, "gpio_24", 1),
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NSP_PIN_DESC(25, "gpio_25", 1),
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NSP_PIN_DESC(26, "p5_led0", 0),
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NSP_PIN_DESC(27, "p5_led1", 0),
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NSP_PIN_DESC(28, "gpio_28", 1),
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NSP_PIN_DESC(29, "gpio_29", 1),
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NSP_PIN_DESC(30, "gpio_30", 1),
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NSP_PIN_DESC(31, "gpio_31", 1),
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NSP_PIN_DESC(32, "nand_ale", 0),
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NSP_PIN_DESC(33, "nand_ce0", 0),
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NSP_PIN_DESC(34, "nand_r/b", 0),
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NSP_PIN_DESC(35, "nand_dq0", 0),
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NSP_PIN_DESC(36, "nand_dq1", 0),
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NSP_PIN_DESC(37, "nand_dq2", 0),
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NSP_PIN_DESC(38, "nand_dq3", 0),
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NSP_PIN_DESC(39, "nand_dq4", 0),
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NSP_PIN_DESC(40, "nand_dq5", 0),
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NSP_PIN_DESC(41, "nand_dq6", 0),
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NSP_PIN_DESC(42, "nand_dq7", 0),
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};
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/*
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* List of groups of pins
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*/
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static const unsigned int spi_pins[] = {0, 1, 2, 3};
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static const unsigned int i2c_pins[] = {4, 5};
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static const unsigned int mdio_pins[] = {6, 7};
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static const unsigned int pwm0_pins[] = {8};
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static const unsigned int gpio_b_0_pins[] = {8};
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static const unsigned int pwm1_pins[] = {9};
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static const unsigned int gpio_b_1_pins[] = {9};
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static const unsigned int pwm2_pins[] = {10};
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static const unsigned int gpio_b_2_pins[] = {10};
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static const unsigned int pwm3_pins[] = {11};
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static const unsigned int gpio_b_3_pins[] = {11};
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static const unsigned int uart1_pins[] = {12, 13, 14, 15};
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static const unsigned int uart2_pins[] = {16, 17};
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static const unsigned int synce_pins[] = {18};
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static const unsigned int sata0_led_pins[] = {19};
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static const unsigned int sata1_led_pins[] = {20};
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static const unsigned int xtal_out_pins[] = {21};
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static const unsigned int sdio_pwr_pins[] = {22};
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static const unsigned int sdio_1p8v_pins[] = {23};
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static const unsigned int switch_p05_led0_pins[] = {26};
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static const unsigned int switch_p05_led1_pins[] = {27};
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static const unsigned int nand_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42};
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static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42};
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#define NSP_PIN_GROUP(group_name, ba, sh, ma, al) \
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{ \
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.name = __stringify(group_name) "_grp", \
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.pins = group_name ## _pins, \
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.num_pins = ARRAY_SIZE(group_name ## _pins), \
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.mux = { \
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.base = ba, \
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.shift = sh, \
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.mask = ma, \
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.alt = al, \
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} \
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}
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/*
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* List of nsp pin groups
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*/
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static const struct nsp_pin_group nsp_pin_groups[] = {
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NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
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NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
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NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
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NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
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NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
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NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
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NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
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NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
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NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
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NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
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NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
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NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
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NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
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NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
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NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
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NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
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NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
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NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
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NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
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NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
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NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
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NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
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NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
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};
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/*
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* List of groups supported by functions
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*/
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static const char * const spi_grps[] = {"spi_grp"};
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static const char * const i2c_grps[] = {"i2c_grp"};
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static const char * const mdio_grps[] = {"mdio_grp"};
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static const char * const pwm_grps[] = {"pwm0_grp", "pwm1_grp", "pwm2_grp"
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, "pwm3_grp"};
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static const char * const gpio_b_grps[] = {"gpio_b_0_grp", "gpio_b_1_grp",
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"gpio_b_2_grp", "gpio_b_3_grp"};
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static const char * const uart1_grps[] = {"uart1_grp"};
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static const char * const uart2_grps[] = {"uart2_grp"};
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static const char * const synce_grps[] = {"synce_grp"};
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static const char * const sata_led_grps[] = {"sata0_led_grp", "sata1_led_grp"};
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static const char * const xtal_out_grps[] = {"xtal_out_grp"};
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static const char * const sdio_grps[] = {"sdio_pwr_grp", "sdio_1p8v_grp"};
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static const char * const switch_led_grps[] = {"switch_p05_led0_grp",
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"switch_p05_led1_grp"};
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static const char * const nand_grps[] = {"nand_grp"};
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static const char * const emmc_grps[] = {"emmc_grp"};
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#define NSP_PIN_FUNCTION(func) \
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{ \
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.name = #func, \
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.groups = func ## _grps, \
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.num_groups = ARRAY_SIZE(func ## _grps), \
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}
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/*
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* List of supported functions in nsp
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*/
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static const struct nsp_pin_function nsp_pin_functions[] = {
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NSP_PIN_FUNCTION(spi),
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NSP_PIN_FUNCTION(i2c),
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NSP_PIN_FUNCTION(mdio),
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NSP_PIN_FUNCTION(pwm),
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NSP_PIN_FUNCTION(gpio_b),
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NSP_PIN_FUNCTION(uart1),
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NSP_PIN_FUNCTION(uart2),
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NSP_PIN_FUNCTION(synce),
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NSP_PIN_FUNCTION(sata_led),
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NSP_PIN_FUNCTION(xtal_out),
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NSP_PIN_FUNCTION(sdio),
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NSP_PIN_FUNCTION(switch_led),
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NSP_PIN_FUNCTION(nand),
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NSP_PIN_FUNCTION(emmc)
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};
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static int nsp_get_groups_count(struct pinctrl_dev *pctrl_dev)
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{
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struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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return pinctrl->num_groups;
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}
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static const char *nsp_get_group_name(struct pinctrl_dev *pctrl_dev,
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unsigned int selector)
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{
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struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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return pinctrl->groups[selector].name;
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}
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static int nsp_get_group_pins(struct pinctrl_dev *pctrl_dev,
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unsigned int selector, const unsigned int **pins,
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unsigned int *num_pins)
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{
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struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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*pins = pinctrl->groups[selector].pins;
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*num_pins = pinctrl->groups[selector].num_pins;
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return 0;
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}
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static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
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struct seq_file *s, unsigned int offset)
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{
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seq_printf(s, " %s", dev_name(pctrl_dev->dev));
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}
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static const struct pinctrl_ops nsp_pinctrl_ops = {
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.get_groups_count = nsp_get_groups_count,
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.get_group_name = nsp_get_group_name,
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.get_group_pins = nsp_get_group_pins,
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.pin_dbg_show = nsp_pin_dbg_show,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int nsp_get_functions_count(struct pinctrl_dev *pctrl_dev)
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{
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struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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return pinctrl->num_functions;
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}
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static const char *nsp_get_function_name(struct pinctrl_dev *pctrl_dev,
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unsigned int selector)
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{
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struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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return pinctrl->functions[selector].name;
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}
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static int nsp_get_function_groups(struct pinctrl_dev *pctrl_dev,
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unsigned int selector,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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*groups = pinctrl->functions[selector].groups;
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*num_groups = pinctrl->functions[selector].num_groups;
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return 0;
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}
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static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl,
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const struct nsp_pin_function *func,
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const struct nsp_pin_group *grp,
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struct nsp_mux_log *mux_log)
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{
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const struct nsp_mux *mux = &grp->mux;
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int i;
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u32 val, mask;
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unsigned long flags;
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void __iomem *base_address;
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for (i = 0; i < pinctrl->num_groups; i++) {
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if ((mux->shift != mux_log[i].mux.shift) ||
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(mux->base != mux_log[i].mux.base))
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continue;
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/* if this is a new configuration, just do it! */
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if (!mux_log[i].is_configured)
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break;
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/*
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* IOMUX has been configured previously and one is trying to
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* configure it to a different function
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*/
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if (mux_log[i].mux.alt != mux->alt) {
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dev_err(pinctrl->dev,
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"double configuration error detected!\n");
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dev_err(pinctrl->dev, "func:%s grp:%s\n",
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func->name, grp->name);
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return -EINVAL;
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}
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return 0;
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}
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if (i == pinctrl->num_groups)
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return -EINVAL;
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mask = mux->mask;
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mux_log[i].mux.alt = mux->alt;
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mux_log[i].is_configured = true;
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switch (mux->base) {
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case NSP_MUX_BASE0:
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base_address = pinctrl->base0;
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break;
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case NSP_MUX_BASE1:
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base_address = pinctrl->base1;
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break;
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case NSP_MUX_BASE2:
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base_address = pinctrl->base2;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&pinctrl->lock, flags);
|
|
val = readl(base_address);
|
|
val &= ~(mask << grp->mux.shift);
|
|
val |= grp->mux.alt << grp->mux.shift;
|
|
writel(val, base_address);
|
|
spin_unlock_irqrestore(&pinctrl->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
|
|
unsigned int func_select, unsigned int grp_select)
|
|
{
|
|
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
|
const struct nsp_pin_function *func;
|
|
const struct nsp_pin_group *grp;
|
|
|
|
if (grp_select >= pinctrl->num_groups ||
|
|
func_select >= pinctrl->num_functions)
|
|
return -EINVAL;
|
|
|
|
func = &pinctrl->functions[func_select];
|
|
grp = &pinctrl->groups[grp_select];
|
|
|
|
dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
|
|
func_select, func->name, grp_select, grp->name);
|
|
|
|
dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift,
|
|
grp->mux.alt);
|
|
|
|
return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
|
|
}
|
|
|
|
|
|
static int nsp_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int pin)
|
|
{
|
|
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
|
u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&pinctrl->lock, flags);
|
|
val = readl(pinctrl->base0);
|
|
if ((val & BIT(pin)) != (*gpio_select << pin)) {
|
|
val &= ~BIT(pin);
|
|
val |= *gpio_select << pin;
|
|
writel(val, pinctrl->base0);
|
|
}
|
|
spin_unlock_irqrestore(&pinctrl->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int pin)
|
|
{
|
|
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
|
u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&pinctrl->lock, flags);
|
|
val = readl(pinctrl->base0);
|
|
if ((val & (1 << pin)) == (*gpio_select << pin)) {
|
|
val &= ~(1 << pin);
|
|
if (!(*gpio_select))
|
|
val |= (1 << pin);
|
|
writel(val, pinctrl->base0);
|
|
}
|
|
spin_unlock_irqrestore(&pinctrl->lock, flags);
|
|
}
|
|
|
|
static const struct pinmux_ops nsp_pinmux_ops = {
|
|
.get_functions_count = nsp_get_functions_count,
|
|
.get_function_name = nsp_get_function_name,
|
|
.get_function_groups = nsp_get_function_groups,
|
|
.set_mux = nsp_pinmux_enable,
|
|
.gpio_request_enable = nsp_gpio_request_enable,
|
|
.gpio_disable_free = nsp_gpio_disable_free,
|
|
};
|
|
|
|
static struct pinctrl_desc nsp_pinctrl_desc = {
|
|
.name = "nsp-pinmux",
|
|
.pctlops = &nsp_pinctrl_ops,
|
|
.pmxops = &nsp_pinmux_ops,
|
|
};
|
|
|
|
static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
|
|
{
|
|
struct nsp_mux_log *log;
|
|
unsigned int i;
|
|
u32 no_of_groups = ARRAY_SIZE(nsp_pin_groups);
|
|
|
|
pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups,
|
|
sizeof(struct nsp_mux_log),
|
|
GFP_KERNEL);
|
|
if (!pinctrl->mux_log)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < no_of_groups; i++) {
|
|
log = &pinctrl->mux_log[i];
|
|
log->mux.base = nsp_pin_groups[i].mux.base;
|
|
log->mux.shift = nsp_pin_groups[i].mux.shift;
|
|
log->mux.alt = 0;
|
|
log->is_configured = false;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nsp_pinmux_probe(struct platform_device *pdev)
|
|
{
|
|
struct nsp_pinctrl *pinctrl;
|
|
struct resource *res;
|
|
int i, ret;
|
|
struct pinctrl_pin_desc *pins;
|
|
unsigned int num_pins = ARRAY_SIZE(nsp_pins);
|
|
|
|
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
|
|
if (!pinctrl)
|
|
return -ENOMEM;
|
|
pinctrl->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, pinctrl);
|
|
spin_lock_init(&pinctrl->lock);
|
|
|
|
pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(pinctrl->base0))
|
|
return PTR_ERR(pinctrl->base0);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (!res)
|
|
return -EINVAL;
|
|
pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (!pinctrl->base1) {
|
|
dev_err(&pdev->dev, "unable to map I/O space\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2);
|
|
if (IS_ERR(pinctrl->base2))
|
|
return PTR_ERR(pinctrl->base2);
|
|
|
|
ret = nsp_mux_log_init(pinctrl);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
|
|
return ret;
|
|
}
|
|
|
|
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < num_pins; i++) {
|
|
pins[i].number = nsp_pins[i].pin;
|
|
pins[i].name = nsp_pins[i].name;
|
|
pins[i].drv_data = &nsp_pins[i].gpio_select;
|
|
}
|
|
|
|
pinctrl->groups = nsp_pin_groups;
|
|
pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups);
|
|
pinctrl->functions = nsp_pin_functions;
|
|
pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
|
|
nsp_pinctrl_desc.pins = pins;
|
|
nsp_pinctrl_desc.npins = num_pins;
|
|
|
|
pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
|
|
pinctrl);
|
|
if (IS_ERR(pinctrl->pctl)) {
|
|
dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n");
|
|
return PTR_ERR(pinctrl->pctl);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id nsp_pinmux_of_match[] = {
|
|
{ .compatible = "brcm,nsp-pinmux" },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver nsp_pinmux_driver = {
|
|
.driver = {
|
|
.name = "nsp-pinmux",
|
|
.of_match_table = nsp_pinmux_of_match,
|
|
},
|
|
.probe = nsp_pinmux_probe,
|
|
};
|
|
|
|
static int __init nsp_pinmux_init(void)
|
|
{
|
|
return platform_driver_register(&nsp_pinmux_driver);
|
|
}
|
|
arch_initcall(nsp_pinmux_init);
|