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83 lines
3.7 KiB
Plaintext
83 lines
3.7 KiB
Plaintext
* ARM L2 Cache Controller
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ARM cores often have a separate level 2 cache controller. There are various
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implementations of the L2 cache controller with compatible programming models.
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Some of the properties that are just prefixed "cache-*" are taken from section
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3.7.3 of the ePAPR v1.1 specification which can be found at:
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https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
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The ARM L2 cache representation in the device tree should be done as follows:
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Required properties:
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- compatible : should be one of:
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"arm,pl310-cache"
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"arm,l220-cache"
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"arm,l210-cache"
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"bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
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"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
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offset needs to be added to the address before passing down to the L2
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cache controller
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"marvell,aurora-system-cache": Marvell Controller designed to be
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compatible with the ARM one, with system cache mode (meaning
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maintenance operations on L1 are broadcasted to the L2 and L2
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performs the same operation).
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"marvell,aurora-outer-cache": Marvell Controller designed to be
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compatible with the ARM one with outer cache mode.
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"marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
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with arm,pl310-cache controller.
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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- reg : Physical base address and size of cache controller's memory mapped
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registers.
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Optional properties:
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- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Minimum valid values are 1. Controllers
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without setup latency control should use a value of 0.
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- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Controllers without setup latency control
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should use 0. Controllers without separate read and write Tag RAM latency
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values should only use the first cell.
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- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
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- arm,filter-ranges : <start length> Starting address and length of window to
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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- arm,io-coherent : indicates that the system is operating in an hardware
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I/O coherent mode. Valid only when the arm,pl310-cache compatible
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string is used.
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- interrupts : 1 combined interrupt.
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- cache-size : specifies the size in bytes of the cache
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- cache-sets : specifies the number of associativity sets of the cache
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- cache-block-size : specifies the size in bytes of a cache block
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- cache-line-size : specifies the size in bytes of a line in the cache,
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if this is not specified, the line size is assumed to be equal to the
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cache block size
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- cache-id-part: cache id part number to be used if it is not present
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on hardware
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- wt-override: If present then L2 is forced to Write through mode
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- arm,double-linefill : Override double linefill enable setting. Enable if
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non-zero, disable if zero.
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- arm,double-linefill-incr : Override double linefill on INCR read. Enable
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if non-zero, disable if zero.
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- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
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if non-zero, disable if zero.
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- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
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disable if zero.
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- arm,prefetch-offset : Override prefetch offset value. Valid values are
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0-7, 15, 23, and 31.
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Example:
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <2 2 2>;
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arm,filter-ranges = <0x80000000 0x8000000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <45>;
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};
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