mirror of https://gitee.com/openkylin/linux.git
449 lines
13 KiB
C
449 lines
13 KiB
C
/*
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* Copyright 2005-2006 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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static int
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nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_bo *pb = chan->pushbuf_bo;
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struct nouveau_gpuobj *pushbuf = NULL;
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int ret;
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if (dev_priv->card_type >= NV_50) {
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ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
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dev_priv->vm_end, NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_AGP, &pushbuf);
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chan->pushbuf_base = pb->bo.offset;
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} else
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if (pb->bo.mem.mem_type == TTM_PL_TT) {
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ret = nouveau_gpuobj_gart_dma_new(chan, 0,
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dev_priv->gart_info.aper_size,
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NV_DMA_ACCESS_RO, &pushbuf,
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NULL);
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chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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} else
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if (dev_priv->card_type != NV_04) {
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ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
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dev_priv->fb_available_size,
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NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_VIDMEM, &pushbuf);
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chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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} else {
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/* NV04 cmdbuf hack, from original ddx.. not sure of it's
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* exact reason for existing :) PCI access to cmdbuf in
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* VRAM.
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*/
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ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
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pci_resource_start(dev->pdev,
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1),
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dev_priv->fb_available_size,
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NV_DMA_ACCESS_RO,
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NV_DMA_TARGET_PCI, &pushbuf);
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chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;
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}
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ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf);
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if (ret) {
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NV_ERROR(dev, "Error referencing pushbuf ctxdma: %d\n", ret);
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if (pushbuf != dev_priv->gart_info.sg_ctxdma)
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nouveau_gpuobj_del(dev, &pushbuf);
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return ret;
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}
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return 0;
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}
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static struct nouveau_bo *
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nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
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{
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struct nouveau_bo *pushbuf = NULL;
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int location, ret;
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if (nouveau_vram_pushbuf)
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location = TTM_PL_FLAG_VRAM;
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else
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location = TTM_PL_FLAG_TT;
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ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
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true, &pushbuf);
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if (ret) {
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NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
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return NULL;
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}
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ret = nouveau_bo_pin(pushbuf, location);
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if (ret) {
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NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
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nouveau_bo_ref(NULL, &pushbuf);
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return NULL;
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}
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return pushbuf;
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}
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/* allocates and initializes a fifo for user space consumption */
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int
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nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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struct drm_file *file_priv,
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uint32_t vram_handle, uint32_t tt_handle)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_channel *chan;
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int channel, user;
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int ret;
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/*
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* Alright, here is the full story
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* Nvidia cards have multiple hw fifo contexts (praise them for that,
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* no complicated crash-prone context switches)
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* We allocate a new context for each app and let it write to it
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* directly (woo, full userspace command submission !)
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* When there are no more contexts, you lost
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*/
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for (channel = 0; channel < pfifo->channels; channel++) {
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if (dev_priv->fifos[channel] == NULL)
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break;
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}
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/* no more fifos. you lost. */
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if (channel == pfifo->channels)
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return -EINVAL;
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dev_priv->fifos[channel] = kzalloc(sizeof(struct nouveau_channel),
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GFP_KERNEL);
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if (!dev_priv->fifos[channel])
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return -ENOMEM;
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chan = dev_priv->fifos[channel];
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INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
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INIT_LIST_HEAD(&chan->fence.pending);
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chan->dev = dev;
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chan->id = channel;
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chan->file_priv = file_priv;
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chan->vram_handle = vram_handle;
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chan->gart_handle = tt_handle;
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NV_INFO(dev, "Allocating FIFO number %d\n", channel);
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/* Allocate DMA push buffer */
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chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
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if (!chan->pushbuf_bo) {
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ret = -ENOMEM;
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NV_ERROR(dev, "pushbuf %d\n", ret);
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nouveau_channel_free(chan);
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return ret;
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}
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nouveau_dma_pre_init(chan);
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/* Locate channel's user control regs */
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if (dev_priv->card_type < NV_40)
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user = NV03_USER(channel);
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else
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if (dev_priv->card_type < NV_50)
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user = NV40_USER(channel);
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else
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user = NV50_USER(channel);
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chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
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PAGE_SIZE);
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if (!chan->user) {
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NV_ERROR(dev, "ioremap of regs failed.\n");
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nouveau_channel_free(chan);
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return -ENOMEM;
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}
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chan->user_put = 0x40;
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chan->user_get = 0x44;
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/* Allocate space for per-channel fixed notifier memory */
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ret = nouveau_notifier_init_channel(chan);
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if (ret) {
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NV_ERROR(dev, "ntfy %d\n", ret);
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nouveau_channel_free(chan);
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return ret;
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}
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/* Setup channel's default objects */
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ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
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if (ret) {
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NV_ERROR(dev, "gpuobj %d\n", ret);
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nouveau_channel_free(chan);
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return ret;
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}
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/* Create a dma object for the push buffer */
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ret = nouveau_channel_pushbuf_ctxdma_init(chan);
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if (ret) {
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NV_ERROR(dev, "pbctxdma %d\n", ret);
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nouveau_channel_free(chan);
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return ret;
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}
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/* disable the fifo caches */
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pfifo->reassign(dev, false);
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/* Create a graphics context for new channel */
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ret = pgraph->create_context(chan);
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if (ret) {
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nouveau_channel_free(chan);
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return ret;
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}
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/* Construct inital RAMFC for new channel */
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ret = pfifo->create_context(chan);
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if (ret) {
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nouveau_channel_free(chan);
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return ret;
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}
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pfifo->reassign(dev, true);
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ret = nouveau_dma_init(chan);
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if (!ret)
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ret = nouveau_fence_init(chan);
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if (ret) {
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nouveau_channel_free(chan);
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return ret;
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}
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nouveau_debugfs_channel_init(chan);
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NV_INFO(dev, "%s: initialised FIFO %d\n", __func__, channel);
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*chan_ret = chan;
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return 0;
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}
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/* stops a fifo */
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void
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nouveau_channel_free(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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unsigned long flags;
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int ret;
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NV_INFO(dev, "%s: freeing fifo %d\n", __func__, chan->id);
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nouveau_debugfs_channel_fini(chan);
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/* Give outstanding push buffers a chance to complete */
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spin_lock_irqsave(&chan->fence.lock, flags);
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nouveau_fence_update(chan);
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spin_unlock_irqrestore(&chan->fence.lock, flags);
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if (chan->fence.sequence != chan->fence.sequence_ack) {
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struct nouveau_fence *fence = NULL;
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ret = nouveau_fence_new(chan, &fence, true);
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if (ret == 0) {
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ret = nouveau_fence_wait(fence, NULL, false, false);
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nouveau_fence_unref((void *)&fence);
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}
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if (ret)
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NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
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}
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/* Ensure all outstanding fences are signaled. They should be if the
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* above attempts at idling were OK, but if we failed this'll tell TTM
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* we're done with the buffers.
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*/
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nouveau_fence_fini(chan);
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/* This will prevent pfifo from switching channels. */
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pfifo->reassign(dev, false);
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/* We want to give pgraph a chance to idle and get rid of all potential
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* errors. We need to do this before the lock, otherwise the irq handler
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* is unable to process them.
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*/
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if (pgraph->channel(dev) == chan)
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nouveau_wait_for_idle(dev);
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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pgraph->fifo_access(dev, false);
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if (pgraph->channel(dev) == chan)
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pgraph->unload_context(dev);
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pgraph->destroy_context(chan);
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pgraph->fifo_access(dev, true);
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if (pfifo->channel_id(dev) == chan->id) {
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pfifo->disable(dev);
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pfifo->unload_context(dev);
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pfifo->enable(dev);
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}
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pfifo->destroy_context(chan);
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pfifo->reassign(dev, true);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* Release the channel's resources */
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nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
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if (chan->pushbuf_bo) {
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nouveau_bo_unpin(chan->pushbuf_bo);
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nouveau_bo_ref(NULL, &chan->pushbuf_bo);
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}
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nouveau_gpuobj_channel_takedown(chan);
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nouveau_notifier_takedown_channel(chan);
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if (chan->user)
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iounmap(chan->user);
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dev_priv->fifos[chan->id] = NULL;
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kfree(chan);
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}
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/* cleans up all the fifos from file_priv */
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void
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nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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int i;
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NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
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for (i = 0; i < engine->fifo.channels; i++) {
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struct nouveau_channel *chan = dev_priv->fifos[i];
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if (chan && chan->file_priv == file_priv)
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nouveau_channel_free(chan);
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}
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}
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int
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nouveau_channel_owner(struct drm_device *dev, struct drm_file *file_priv,
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int channel)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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if (channel >= engine->fifo.channels)
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return 0;
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if (dev_priv->fifos[channel] == NULL)
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return 0;
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return (dev_priv->fifos[channel]->file_priv == file_priv);
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}
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/***********************************
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* ioctls wrapping the functions
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***********************************/
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static int
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nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_nouveau_channel_alloc *init = data;
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struct nouveau_channel *chan;
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int ret;
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NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
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if (dev_priv->engine.graph.accel_blocked)
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return -ENODEV;
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if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
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return -EINVAL;
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ret = nouveau_channel_alloc(dev, &chan, file_priv,
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init->fb_ctxdma_handle,
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init->tt_ctxdma_handle);
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if (ret)
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return ret;
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init->channel = chan->id;
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if (chan->dma.ib_max)
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init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
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NOUVEAU_GEM_DOMAIN_GART;
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else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
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init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
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else
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init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
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init->subchan[0].handle = NvM2MF;
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if (dev_priv->card_type < NV_50)
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init->subchan[0].grclass = 0x0039;
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else
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init->subchan[0].grclass = 0x5039;
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init->subchan[1].handle = NvSw;
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init->subchan[1].grclass = NV_SW;
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init->nr_subchan = 2;
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/* Named memory object area */
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ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
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&init->notifier_handle);
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if (ret) {
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nouveau_channel_free(chan);
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return ret;
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}
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return 0;
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}
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static int
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nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_nouveau_channel_free *cfree = data;
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struct nouveau_channel *chan;
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NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
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NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);
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nouveau_channel_free(chan);
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return 0;
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}
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/***********************************
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* finally, the ioctl table
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***********************************/
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struct drm_ioctl_desc nouveau_ioctls[] = {
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DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
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};
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int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
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