mirror of https://gitee.com/openkylin/linux.git
130 lines
3.6 KiB
C
130 lines
3.6 KiB
C
/*
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* Copyright (C) 2015 Altera Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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/* Clock Manager offsets */
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#define CLK_MGR_PLL_CLK_SRC_SHIFT 8
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#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
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/* Clock bypass bits */
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#define SOCFPGA_PLL_BG_PWRDWN 0
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#define SOCFPGA_PLL_PWR_DOWN 1
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#define SOCFPGA_PLL_EXT_ENA 2
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#define SOCFPGA_PLL_DIVF_MASK 0x00001FFF
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#define SOCFPGA_PLL_DIVF_SHIFT 0
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#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
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#define SOCFPGA_PLL_DIVQ_SHIFT 16
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#define SOCFGPA_MAX_PARENTS 5
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#define SOCFPGA_MAIN_PLL_CLK "main_pll"
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#define SOCFPGA_PERIP_PLL_CLK "periph_pll"
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#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
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void __iomem *clk_mgr_a10_base_addr;
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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unsigned long divf, divq, reg;
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unsigned long long vco_freq;
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/* read VCO1 reg for numerator and denominator */
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reg = readl(socfpgaclk->hw.reg + 0x4);
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divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
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divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
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vco_freq = (unsigned long long)parent_rate * (divf + 1);
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do_div(vco_freq, (1 + divq));
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return (unsigned long)vco_freq;
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}
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static u8 clk_pll_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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u32 pll_src;
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pll_src = readl(socfpgaclk->hw.reg);
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return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
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CLK_MGR_PLL_CLK_SRC_MASK;
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}
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static struct clk_ops clk_pll_ops = {
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.recalc_rate = clk_pll_recalc_rate,
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.get_parent = clk_pll_get_parent,
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};
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static struct __init clk * __socfpga_pll_init(struct device_node *node,
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const struct clk_ops *ops)
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{
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u32 reg;
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struct clk *clk;
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struct socfpga_pll *pll_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFGPA_MAX_PARENTS];
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struct clk_init_data init;
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struct device_node *clkmgr_np;
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int rc;
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int i = 0;
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of_property_read_u32(node, "reg", ®);
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (WARN_ON(!pll_clk))
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return NULL;
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clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
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clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
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BUG_ON(!clk_mgr_a10_base_addr);
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pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
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of_clk_get_parent_name(node, i)) != NULL)
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i++;
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init.num_parents = i;
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init.parent_names = parent_name;
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pll_clk->hw.hw.init = &init;
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pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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clk_pll_ops.enable = clk_gate_ops.enable;
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clk_pll_ops.disable = clk_gate_ops.disable;
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clk = clk_register(NULL, &pll_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(pll_clk);
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return NULL;
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}
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rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return clk;
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}
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void __init socfpga_a10_pll_init(struct device_node *node)
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{
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__socfpga_pll_init(node, &clk_pll_ops);
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}
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