mirror of https://gitee.com/openkylin/linux.git
656 lines
15 KiB
C
656 lines
15 KiB
C
/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C6400 based common clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <plat/cpu-freq.h>
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#include <plat/regs-clock.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
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* ext_xtal_mux for want of an actual name from the manual.
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*/
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struct clk clk_ext_xtal_mux = {
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.name = "ext_xtal",
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.id = -1,
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};
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#define clk_fin_apll clk_ext_xtal_mux
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#define clk_fin_mpll clk_ext_xtal_mux
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#define clk_fin_epll clk_ext_xtal_mux
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#define clk_fout_mpll clk_mpll
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struct clk_sources {
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unsigned int nr_sources;
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struct clk **sources;
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};
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struct clksrc_clk {
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struct clk clk;
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unsigned int mask;
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unsigned int shift;
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struct clk_sources *sources;
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unsigned int divider_shift;
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void __iomem *reg_divider;
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};
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struct clk clk_fout_apll = {
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.name = "fout_apll",
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.id = -1,
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};
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static struct clk *clk_src_apll_list[] = {
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[0] = &clk_fin_apll,
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[1] = &clk_fout_apll,
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};
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static struct clk_sources clk_src_apll = {
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.sources = clk_src_apll_list,
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.nr_sources = ARRAY_SIZE(clk_src_apll_list),
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};
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struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
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.mask = S3C6400_CLKSRC_APLL_MOUT,
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.sources = &clk_src_apll,
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};
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struct clk clk_fout_epll = {
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.name = "fout_epll",
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.id = -1,
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};
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static struct clk *clk_src_epll_list[] = {
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[0] = &clk_fin_epll,
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[1] = &clk_fout_epll,
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};
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static struct clk_sources clk_src_epll = {
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.sources = clk_src_epll_list,
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.nr_sources = ARRAY_SIZE(clk_src_epll_list),
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};
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struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
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.mask = S3C6400_CLKSRC_EPLL_MOUT,
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.sources = &clk_src_epll,
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};
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static struct clk *clk_src_mpll_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &clk_fout_mpll,
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};
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static struct clk_sources clk_src_mpll = {
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.sources = clk_src_mpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
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};
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struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
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.mask = S3C6400_CLKSRC_MPLL_MOUT,
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.sources = &clk_src_mpll,
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};
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static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
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if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
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rate /= 2;
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return rate;
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}
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struct clk clk_dout_mpll = {
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.name = "dout_mpll",
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.id = -1,
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.parent = &clk_mout_mpll.clk,
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.get_rate = s3c64xx_clk_doutmpll_get_rate,
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};
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static struct clk *clkset_spi_mmc_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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&clk_fin_epll,
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&clk_27m,
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};
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static struct clk_sources clkset_spi_mmc = {
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.sources = clkset_spi_mmc_list,
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.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
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};
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static struct clk *clkset_irda_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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NULL,
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&clk_27m,
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};
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static struct clk_sources clkset_irda = {
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.sources = clkset_irda_list,
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.nr_sources = ARRAY_SIZE(clkset_irda_list),
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};
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static struct clk *clkset_uart_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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NULL,
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NULL
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};
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static struct clk_sources clkset_uart = {
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.sources = clkset_uart_list,
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.nr_sources = ARRAY_SIZE(clkset_uart_list),
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};
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static struct clk *clkset_uhost_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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&clk_fin_epll,
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&clk_48m,
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};
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static struct clk_sources clkset_uhost = {
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.sources = clkset_uhost_list,
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.nr_sources = ARRAY_SIZE(clkset_uhost_list),
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};
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/* The peripheral clocks are all controlled via clocksource followed
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* by an optional divider and gate stage. We currently roll this into
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* one clock which hides the intermediate clock from the mux.
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*
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* Note, the JPEG clock can only be an even divider...
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*
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* The scaler and LCD clocks depend on the S3C64XX version, and also
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* have a common parent divisor so are not included here.
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*/
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static inline struct clksrc_clk *to_clksrc(struct clk *clk)
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{
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return container_of(clk, struct clksrc_clk, clk);
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}
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static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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unsigned long rate = clk_get_rate(clk->parent);
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u32 clkdiv = __raw_readl(sclk->reg_divider);
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clkdiv >>= sclk->divider_shift;
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clkdiv &= 0xf;
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clkdiv++;
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rate /= clkdiv;
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return rate;
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}
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static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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void __iomem *reg = sclk->reg_divider;
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unsigned int div;
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u32 val;
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rate = clk_round_rate(clk, rate);
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div = clk_get_rate(clk->parent) / rate;
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val = __raw_readl(reg);
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val &= ~sclk->mask;
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val |= (rate - 1) << sclk->shift;
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__raw_writel(val, reg);
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return 0;
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}
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static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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struct clk_sources *srcs = sclk->sources;
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u32 clksrc = __raw_readl(S3C_CLK_SRC);
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int src_nr = -1;
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int ptr;
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for (ptr = 0; ptr < srcs->nr_sources; ptr++)
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if (srcs->sources[ptr] == parent) {
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src_nr = ptr;
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break;
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}
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if (src_nr >= 0) {
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clksrc &= ~sclk->mask;
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clksrc |= src_nr << sclk->shift;
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__raw_writel(clksrc, S3C_CLK_SRC);
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return 0;
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}
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return -EINVAL;
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}
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static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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int div;
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if (rate > parent_rate)
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rate = parent_rate;
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else {
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div = rate / parent_rate;
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if (div == 0)
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div = 1;
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if (div > 16)
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div = 16;
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rate = parent_rate / div;
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}
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return rate;
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}
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static struct clksrc_clk clk_mmc0 = {
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.clk = {
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.name = "mmc_bus",
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.id = 0,
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.ctrlbit = S3C_CLKCON_SCLK_MMC0,
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.enable = s3c64xx_sclk_ctrl,
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.set_parent = s3c64xx_setparent_clksrc,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_MMC0_SHIFT,
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.mask = S3C6400_CLKSRC_MMC0_MASK,
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.sources = &clkset_spi_mmc,
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.divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
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.reg_divider = S3C_CLK_DIV1,
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};
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static struct clksrc_clk clk_mmc1 = {
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.clk = {
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.name = "mmc_bus",
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.id = 1,
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.ctrlbit = S3C_CLKCON_SCLK_MMC1,
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.enable = s3c64xx_sclk_ctrl,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.set_parent = s3c64xx_setparent_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_MMC1_SHIFT,
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.mask = S3C6400_CLKSRC_MMC1_MASK,
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.sources = &clkset_spi_mmc,
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.divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
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.reg_divider = S3C_CLK_DIV1,
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};
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static struct clksrc_clk clk_mmc2 = {
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.clk = {
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.name = "mmc_bus",
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.id = 2,
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.ctrlbit = S3C_CLKCON_SCLK_MMC2,
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.enable = s3c64xx_sclk_ctrl,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.set_parent = s3c64xx_setparent_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_MMC2_SHIFT,
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.mask = S3C6400_CLKSRC_MMC2_MASK,
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.sources = &clkset_spi_mmc,
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.divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
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.reg_divider = S3C_CLK_DIV1,
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};
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static struct clksrc_clk clk_usbhost = {
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.clk = {
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.name = "usb-host-bus",
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.id = -1,
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.ctrlbit = S3C_CLKCON_SCLK_UHOST,
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.enable = s3c64xx_sclk_ctrl,
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.set_parent = s3c64xx_setparent_clksrc,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_UHOST_SHIFT,
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.mask = S3C6400_CLKSRC_UHOST_MASK,
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.sources = &clkset_uhost,
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.divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
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.reg_divider = S3C_CLK_DIV1,
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};
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static struct clksrc_clk clk_uart_uclk1 = {
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.clk = {
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.name = "uclk1",
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.id = -1,
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.ctrlbit = S3C_CLKCON_SCLK_UART,
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.enable = s3c64xx_sclk_ctrl,
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.set_parent = s3c64xx_setparent_clksrc,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_UART_SHIFT,
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.mask = S3C6400_CLKSRC_UART_MASK,
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.sources = &clkset_uart,
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.divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
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.reg_divider = S3C_CLK_DIV2,
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};
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/* Where does UCLK0 come from? */
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static struct clksrc_clk clk_spi0 = {
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.clk = {
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.name = "spi-bus",
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.id = 0,
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.ctrlbit = S3C_CLKCON_SCLK_SPI0,
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.enable = s3c64xx_sclk_ctrl,
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.set_parent = s3c64xx_setparent_clksrc,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_SPI0_SHIFT,
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.mask = S3C6400_CLKSRC_SPI0_MASK,
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.sources = &clkset_spi_mmc,
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.divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
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.reg_divider = S3C_CLK_DIV2,
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};
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static struct clksrc_clk clk_spi1 = {
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.clk = {
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.name = "spi-bus",
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.id = 1,
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.ctrlbit = S3C_CLKCON_SCLK_SPI1,
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.enable = s3c64xx_sclk_ctrl,
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.set_parent = s3c64xx_setparent_clksrc,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_SPI1_SHIFT,
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.mask = S3C6400_CLKSRC_SPI1_MASK,
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.sources = &clkset_spi_mmc,
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.divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
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.reg_divider = S3C_CLK_DIV2,
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};
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static struct clk clk_iis_cd0 = {
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.name = "iis_cdclk0",
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.id = -1,
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};
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static struct clk clk_iis_cd1 = {
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.name = "iis_cdclk1",
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.id = -1,
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};
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static struct clk clk_pcm_cd = {
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.name = "pcm_cdclk",
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.id = -1,
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};
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static struct clk *clkset_audio0_list[] = {
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[0] = &clk_mout_epll.clk,
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[1] = &clk_dout_mpll,
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[2] = &clk_fin_epll,
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[3] = &clk_iis_cd0,
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[4] = &clk_pcm_cd,
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};
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static struct clk_sources clkset_audio0 = {
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.sources = clkset_audio0_list,
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.nr_sources = ARRAY_SIZE(clkset_audio0_list),
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};
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static struct clksrc_clk clk_audio0 = {
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.clk = {
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.name = "audio-bus",
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.id = 0,
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.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
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.enable = s3c64xx_sclk_ctrl,
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.set_parent = s3c64xx_setparent_clksrc,
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.get_rate = s3c64xx_getrate_clksrc,
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.set_rate = s3c64xx_setrate_clksrc,
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.round_rate = s3c64xx_roundrate_clksrc,
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},
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.shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
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.mask = S3C6400_CLKSRC_AUDIO0_MASK,
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.sources = &clkset_audio0,
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.divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
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.reg_divider = S3C_CLK_DIV2,
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};
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static struct clk *clkset_audio1_list[] = {
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[0] = &clk_mout_epll.clk,
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[1] = &clk_dout_mpll,
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[2] = &clk_fin_epll,
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[3] = &clk_iis_cd1,
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[4] = &clk_pcm_cd,
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};
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static struct clk_sources clkset_audio1 = {
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.sources = clkset_audio1_list,
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.nr_sources = ARRAY_SIZE(clkset_audio1_list),
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};
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static struct clksrc_clk clk_audio1 = {
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.clk = {
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.name = "audio-bus",
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.id = 1,
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.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
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.enable = s3c64xx_sclk_ctrl,
|
|
.set_parent = s3c64xx_setparent_clksrc,
|
|
.get_rate = s3c64xx_getrate_clksrc,
|
|
.set_rate = s3c64xx_setrate_clksrc,
|
|
.round_rate = s3c64xx_roundrate_clksrc,
|
|
},
|
|
.shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
|
|
.mask = S3C6400_CLKSRC_AUDIO1_MASK,
|
|
.sources = &clkset_audio1,
|
|
.divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
|
|
.reg_divider = S3C_CLK_DIV2,
|
|
};
|
|
|
|
static struct clksrc_clk clk_irda = {
|
|
.clk = {
|
|
.name = "irda-bus",
|
|
.id = 0,
|
|
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
.set_parent = s3c64xx_setparent_clksrc,
|
|
.get_rate = s3c64xx_getrate_clksrc,
|
|
.set_rate = s3c64xx_setrate_clksrc,
|
|
.round_rate = s3c64xx_roundrate_clksrc,
|
|
},
|
|
.shift = S3C6400_CLKSRC_IRDA_SHIFT,
|
|
.mask = S3C6400_CLKSRC_IRDA_MASK,
|
|
.sources = &clkset_irda,
|
|
.divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
|
|
.reg_divider = S3C_CLK_DIV2,
|
|
};
|
|
|
|
/* Clock initialisation code */
|
|
|
|
static struct clksrc_clk *init_parents[] = {
|
|
&clk_mout_apll,
|
|
&clk_mout_epll,
|
|
&clk_mout_mpll,
|
|
&clk_mmc0,
|
|
&clk_mmc1,
|
|
&clk_mmc2,
|
|
&clk_usbhost,
|
|
&clk_uart_uclk1,
|
|
&clk_spi0,
|
|
&clk_spi1,
|
|
&clk_audio0,
|
|
&clk_audio1,
|
|
&clk_irda,
|
|
};
|
|
|
|
static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
|
|
{
|
|
struct clk_sources *srcs = clk->sources;
|
|
u32 clksrc = __raw_readl(S3C_CLK_SRC);
|
|
|
|
clksrc &= clk->mask;
|
|
clksrc >>= clk->shift;
|
|
|
|
if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
|
|
printk(KERN_ERR "%s: bad source %d\n",
|
|
clk->clk.name, clksrc);
|
|
return;
|
|
}
|
|
|
|
clk->clk.parent = srcs->sources[clksrc];
|
|
|
|
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
|
|
clk->clk.name, clk->clk.parent->name, clksrc,
|
|
clk_get_rate(&clk->clk));
|
|
}
|
|
|
|
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
|
|
|
|
void __init_or_cpufreq s3c6400_setup_clocks(void)
|
|
{
|
|
struct clk *xtal_clk;
|
|
unsigned long xtal;
|
|
unsigned long fclk;
|
|
unsigned long hclk;
|
|
unsigned long hclk2;
|
|
unsigned long pclk;
|
|
unsigned long epll;
|
|
unsigned long apll;
|
|
unsigned long mpll;
|
|
unsigned int ptr;
|
|
u32 clkdiv0;
|
|
|
|
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
|
|
|
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
|
|
printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
|
|
|
|
xtal_clk = clk_get(NULL, "xtal");
|
|
BUG_ON(IS_ERR(xtal_clk));
|
|
|
|
xtal = clk_get_rate(xtal_clk);
|
|
clk_put(xtal_clk);
|
|
|
|
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
|
|
|
|
epll = s3c6400_get_epll(xtal);
|
|
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
|
|
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
|
|
|
|
fclk = mpll;
|
|
|
|
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
|
|
apll, mpll, epll);
|
|
|
|
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
|
|
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
|
|
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
|
|
|
|
printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
|
|
hclk2, hclk, pclk);
|
|
|
|
clk_fout_mpll.rate = mpll;
|
|
clk_fout_epll.rate = epll;
|
|
clk_fout_apll.rate = apll;
|
|
|
|
clk_h.rate = hclk;
|
|
clk_p.rate = pclk;
|
|
clk_f.rate = fclk;
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
|
|
s3c6400_set_clksrc(init_parents[ptr]);
|
|
}
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_ext_xtal_mux,
|
|
&clk_iis_cd0,
|
|
&clk_iis_cd1,
|
|
&clk_pcm_cd,
|
|
&clk_mout_epll.clk,
|
|
&clk_fout_epll,
|
|
&clk_mout_mpll.clk,
|
|
&clk_dout_mpll,
|
|
&clk_mmc0.clk,
|
|
&clk_mmc1.clk,
|
|
&clk_mmc2.clk,
|
|
&clk_usbhost.clk,
|
|
&clk_uart_uclk1.clk,
|
|
&clk_spi0.clk,
|
|
&clk_spi1.clk,
|
|
&clk_audio0.clk,
|
|
&clk_audio1.clk,
|
|
&clk_irda.clk,
|
|
};
|
|
|
|
void __init s3c6400_register_clocks(void)
|
|
{
|
|
struct clk *clkp;
|
|
int ret;
|
|
int ptr;
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
|
|
clkp = clks[ptr];
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
}
|
|
|
|
clk_mpll.parent = &clk_mout_mpll.clk;
|
|
clk_epll.parent = &clk_mout_epll.clk;
|
|
}
|