mirror of https://gitee.com/openkylin/linux.git
146 lines
3.4 KiB
C
146 lines
3.4 KiB
C
/*
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* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
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* Copyright (C) 2004 Intel Corp.
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*
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* This code is released under the GNU General Public License version 2.
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*/
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/*
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* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include "pci.h"
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#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
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/* The base address of the last MMCONFIG device accessed */
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static u32 mmcfg_last_accessed_device;
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/*
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* Functions for accessing PCI configuration space with MMCONFIG accesses
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*/
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static u32 get_base_addr(unsigned int seg, int bus)
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{
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int cfg_num = -1;
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struct acpi_table_mcfg_config *cfg;
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while (1) {
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++cfg_num;
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if (cfg_num >= pci_mmcfg_config_num) {
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/* something bad is going on, no cfg table is found. */
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/* so we fall back to the old way we used to do this */
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/* and just rely on the first entry to be correct. */
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return pci_mmcfg_config[0].base_address;
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}
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cfg = &pci_mmcfg_config[cfg_num];
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if (cfg->pci_segment_group_number != seg)
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continue;
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if ((cfg->start_bus_number <= bus) &&
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(cfg->end_bus_number >= bus))
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return cfg->base_address;
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}
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}
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static inline void pci_exp_set_dev_base(unsigned int seg, int bus, int devfn)
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{
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u32 dev_base = get_base_addr(seg, bus) | (bus << 20) | (devfn << 12);
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if (dev_base != mmcfg_last_accessed_device) {
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mmcfg_last_accessed_device = dev_base;
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set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
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}
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}
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static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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unsigned long flags;
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if (!value || (bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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spin_lock_irqsave(&pci_config_lock, flags);
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pci_exp_set_dev_base(seg, bus, devfn);
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switch (len) {
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case 1:
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*value = readb(mmcfg_virt_addr + reg);
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break;
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case 2:
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*value = readw(mmcfg_virt_addr + reg);
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break;
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case 4:
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*value = readl(mmcfg_virt_addr + reg);
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break;
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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unsigned long flags;
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if ((bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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spin_lock_irqsave(&pci_config_lock, flags);
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pci_exp_set_dev_base(seg, bus, devfn);
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switch (len) {
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case 1:
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writeb(value, mmcfg_virt_addr + reg);
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break;
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case 2:
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writew(value, mmcfg_virt_addr + reg);
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break;
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case 4:
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writel(value, mmcfg_virt_addr + reg);
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break;
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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static struct pci_raw_ops pci_mmcfg = {
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.read = pci_mmcfg_read,
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.write = pci_mmcfg_write,
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};
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static int __init pci_mmcfg_init(void)
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{
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if ((pci_probe & PCI_PROBE_MMCONF) == 0)
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goto out;
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acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].base_address == 0))
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goto out;
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/* Kludge for now. Don't use mmconfig on AMD systems because
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those have some busses where mmconfig doesn't work,
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and we don't parse ACPI MCFG well enough to handle that.
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Remove when proper handling is added. */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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goto out;
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printk(KERN_INFO "PCI: Using MMCONFIG\n");
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raw_pci_ops = &pci_mmcfg;
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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out:
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return 0;
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}
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arch_initcall(pci_mmcfg_init);
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