mirror of https://gitee.com/openkylin/linux.git
291 lines
6.7 KiB
C
291 lines
6.7 KiB
C
/*
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*
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* Copyright (C) 2013 Texas Instruments Incorporated
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*
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* Hwmod common for AM335x and AM43x
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/types.h>
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#include "omap_hwmod.h"
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#include "cm33xx.h"
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#include "prm33xx.h"
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#include "omap_hwmod_33xx_43xx_common_data.h"
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#include "prcm43xx.h"
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#include "common.h"
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#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
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#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
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#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
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/*
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* 'l3' class
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* instance(s): l3_main, l3_s, l3_instr
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*/
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static struct omap_hwmod_class am33xx_l3_hwmod_class = {
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.name = "l3",
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};
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struct omap_hwmod am33xx_l3_main_hwmod = {
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.name = "l3_main",
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.class = &am33xx_l3_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l3_s */
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struct omap_hwmod am33xx_l3_s_hwmod = {
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.name = "l3_s",
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.class = &am33xx_l3_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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};
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/* l3_instr */
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struct omap_hwmod am33xx_l3_instr_hwmod = {
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.name = "l3_instr",
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.class = &am33xx_l3_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'l4' class
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* instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
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*/
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struct omap_hwmod_class am33xx_l4_hwmod_class = {
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.name = "l4",
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};
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/* l4_ls */
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struct omap_hwmod am33xx_l4_ls_hwmod = {
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.name = "l4_ls",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l4_wkup */
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struct omap_hwmod am33xx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'mpu' class
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*/
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static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
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.name = "mpu",
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};
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struct omap_hwmod am33xx_mpu_hwmod = {
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.name = "mpu",
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.class = &am33xx_mpu_hwmod_class,
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.clkdm_name = "mpu_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_mpu_m2_ck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'wakeup m3' class
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* Wakeup controller sub-system under wakeup domain
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*/
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struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
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.name = "wkup_m3",
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};
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/*
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* 'prcm' class
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* power and reset manager (whole prcm infrastructure)
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*/
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static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
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.name = "prcm",
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};
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/* prcm */
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struct omap_hwmod am33xx_prcm_hwmod = {
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.name = "prcm",
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.class = &am33xx_prcm_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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};
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/*
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* 'emif' class
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* instance(s): emif
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*/
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static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
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.rev_offs = 0x0000,
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};
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struct omap_hwmod_class am33xx_emif_hwmod_class = {
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.name = "emif",
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.sysc = &am33xx_emif_sysc,
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};
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/* ocmcram */
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static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
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.name = "ocmcram",
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};
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struct omap_hwmod am33xx_ocmcram_hwmod = {
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.name = "ocmcram",
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.class = &am33xx_ocmcram_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* 'smartreflex' class */
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static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
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.name = "smartreflex",
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};
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/* smartreflex0 */
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struct omap_hwmod am33xx_smartreflex0_hwmod = {
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.name = "smartreflex0",
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.class = &am33xx_smartreflex_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.main_clk = "smartreflex0_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* smartreflex1 */
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struct omap_hwmod am33xx_smartreflex1_hwmod = {
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.name = "smartreflex1",
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.class = &am33xx_smartreflex_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.main_clk = "smartreflex1_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'control' module class
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*/
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struct omap_hwmod_class am33xx_control_hwmod_class = {
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.name = "control",
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};
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/* gpmc */
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static struct omap_hwmod_class_sysconfig gpmc_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x10,
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.syss_offs = 0x14,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
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.name = "gpmc",
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.sysc = &gpmc_sysc,
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};
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struct omap_hwmod am33xx_gpmc_hwmod = {
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.name = "gpmc",
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.class = &am33xx_gpmc_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
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.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
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.main_clk = "l3s_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static void omap_hwmod_am33xx_clkctrl(void)
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{
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CLKCTRL(am33xx_smartreflex0_hwmod,
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AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_smartreflex1_hwmod,
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AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
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}
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void omap_hwmod_am33xx_reg(void)
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{
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omap_hwmod_am33xx_clkctrl();
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}
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static void omap_hwmod_am43xx_clkctrl(void)
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{
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CLKCTRL(am33xx_smartreflex0_hwmod,
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AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_smartreflex1_hwmod,
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AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
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}
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void omap_hwmod_am43xx_reg(void)
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{
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omap_hwmod_am43xx_clkctrl();
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}
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