mirror of https://gitee.com/openkylin/linux.git
712 lines
19 KiB
C
712 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
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#include <linux/kernel.h>
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#include "cc_driver.h"
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#include "cc_buffer_mgr.h"
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#include "cc_request_mgr.h"
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#include "cc_ivgen.h"
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#include "cc_pm.h"
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#define CC_MAX_POLL_ITER 10
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/* The highest descriptor count in used */
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#define CC_MAX_DESC_SEQ_LEN 23
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struct cc_req_mgr_handle {
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/* Request manager resources */
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unsigned int hw_queue_size; /* HW capability */
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unsigned int min_free_hw_slots;
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unsigned int max_used_sw_slots;
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struct cc_crypto_req req_queue[MAX_REQUEST_QUEUE_SIZE];
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u32 req_queue_head;
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u32 req_queue_tail;
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u32 axi_completed;
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u32 q_free_slots;
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/* This lock protects access to HW register
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* that must be single request at a time
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*/
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spinlock_t hw_lock;
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struct cc_hw_desc compl_desc;
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u8 *dummy_comp_buff;
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dma_addr_t dummy_comp_buff_dma;
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/* backlog queue */
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struct list_head backlog;
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unsigned int bl_len;
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spinlock_t bl_lock; /* protect backlog queue */
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#ifdef COMP_IN_WQ
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struct workqueue_struct *workq;
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struct delayed_work compwork;
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#else
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struct tasklet_struct comptask;
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#endif
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bool is_runtime_suspended;
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};
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struct cc_bl_item {
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struct cc_crypto_req creq;
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struct cc_hw_desc desc[CC_MAX_DESC_SEQ_LEN];
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unsigned int len;
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struct list_head list;
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bool notif;
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};
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static void comp_handler(unsigned long devarg);
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#ifdef COMP_IN_WQ
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static void comp_work_handler(struct work_struct *work);
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#endif
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void cc_req_mgr_fini(struct cc_drvdata *drvdata)
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{
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struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
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struct device *dev = drvdata_to_dev(drvdata);
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if (!req_mgr_h)
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return; /* Not allocated */
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if (req_mgr_h->dummy_comp_buff_dma) {
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dma_free_coherent(dev, sizeof(u32), req_mgr_h->dummy_comp_buff,
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req_mgr_h->dummy_comp_buff_dma);
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}
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dev_dbg(dev, "max_used_hw_slots=%d\n", (req_mgr_h->hw_queue_size -
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req_mgr_h->min_free_hw_slots));
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dev_dbg(dev, "max_used_sw_slots=%d\n", req_mgr_h->max_used_sw_slots);
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#ifdef COMP_IN_WQ
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flush_workqueue(req_mgr_h->workq);
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destroy_workqueue(req_mgr_h->workq);
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#else
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/* Kill tasklet */
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tasklet_kill(&req_mgr_h->comptask);
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#endif
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kzfree(req_mgr_h);
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drvdata->request_mgr_handle = NULL;
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}
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int cc_req_mgr_init(struct cc_drvdata *drvdata)
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{
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struct cc_req_mgr_handle *req_mgr_h;
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struct device *dev = drvdata_to_dev(drvdata);
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int rc = 0;
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req_mgr_h = kzalloc(sizeof(*req_mgr_h), GFP_KERNEL);
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if (!req_mgr_h) {
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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drvdata->request_mgr_handle = req_mgr_h;
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spin_lock_init(&req_mgr_h->hw_lock);
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spin_lock_init(&req_mgr_h->bl_lock);
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INIT_LIST_HEAD(&req_mgr_h->backlog);
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#ifdef COMP_IN_WQ
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dev_dbg(dev, "Initializing completion workqueue\n");
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req_mgr_h->workq = create_singlethread_workqueue("ccree");
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if (!req_mgr_h->workq) {
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dev_err(dev, "Failed creating work queue\n");
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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INIT_DELAYED_WORK(&req_mgr_h->compwork, comp_work_handler);
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#else
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dev_dbg(dev, "Initializing completion tasklet\n");
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tasklet_init(&req_mgr_h->comptask, comp_handler,
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(unsigned long)drvdata);
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#endif
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req_mgr_h->hw_queue_size = cc_ioread(drvdata,
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CC_REG(DSCRPTR_QUEUE_SRAM_SIZE));
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dev_dbg(dev, "hw_queue_size=0x%08X\n", req_mgr_h->hw_queue_size);
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if (req_mgr_h->hw_queue_size < MIN_HW_QUEUE_SIZE) {
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dev_err(dev, "Invalid HW queue size = %u (Min. required is %u)\n",
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req_mgr_h->hw_queue_size, MIN_HW_QUEUE_SIZE);
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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req_mgr_h->min_free_hw_slots = req_mgr_h->hw_queue_size;
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req_mgr_h->max_used_sw_slots = 0;
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/* Allocate DMA word for "dummy" completion descriptor use */
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req_mgr_h->dummy_comp_buff =
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dma_alloc_coherent(dev, sizeof(u32),
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&req_mgr_h->dummy_comp_buff_dma,
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GFP_KERNEL);
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if (!req_mgr_h->dummy_comp_buff) {
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dev_err(dev, "Not enough memory to allocate DMA (%zu) dropped buffer\n",
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sizeof(u32));
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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/* Init. "dummy" completion descriptor */
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hw_desc_init(&req_mgr_h->compl_desc);
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set_din_const(&req_mgr_h->compl_desc, 0, sizeof(u32));
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set_dout_dlli(&req_mgr_h->compl_desc, req_mgr_h->dummy_comp_buff_dma,
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sizeof(u32), NS_BIT, 1);
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set_flow_mode(&req_mgr_h->compl_desc, BYPASS);
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set_queue_last_ind(drvdata, &req_mgr_h->compl_desc);
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return 0;
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req_mgr_init_err:
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cc_req_mgr_fini(drvdata);
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return rc;
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}
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static void enqueue_seq(struct cc_drvdata *drvdata, struct cc_hw_desc seq[],
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unsigned int seq_len)
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{
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int i, w;
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void __iomem *reg = drvdata->cc_base + CC_REG(DSCRPTR_QUEUE_WORD0);
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struct device *dev = drvdata_to_dev(drvdata);
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/*
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* We do indeed write all 6 command words to the same
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* register. The HW supports this.
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*/
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for (i = 0; i < seq_len; i++) {
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for (w = 0; w <= 5; w++)
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writel_relaxed(seq[i].word[w], reg);
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if (cc_dump_desc)
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dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
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i, seq[i].word[0], seq[i].word[1],
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seq[i].word[2], seq[i].word[3],
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seq[i].word[4], seq[i].word[5]);
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}
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}
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/*!
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* Completion will take place if and only if user requested completion
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* by cc_send_sync_request().
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*
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* \param dev
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* \param dx_compl_h The completion event to signal
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*/
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static void request_mgr_complete(struct device *dev, void *dx_compl_h,
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int dummy)
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{
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struct completion *this_compl = dx_compl_h;
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complete(this_compl);
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}
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static int cc_queues_status(struct cc_drvdata *drvdata,
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struct cc_req_mgr_handle *req_mgr_h,
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unsigned int total_seq_len)
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{
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unsigned long poll_queue;
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struct device *dev = drvdata_to_dev(drvdata);
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/* SW queue is checked only once as it will not
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* be chaned during the poll because the spinlock_bh
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* is held by the thread
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*/
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if (((req_mgr_h->req_queue_head + 1) & (MAX_REQUEST_QUEUE_SIZE - 1)) ==
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req_mgr_h->req_queue_tail) {
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dev_err(dev, "SW FIFO is full. req_queue_head=%d sw_fifo_len=%d\n",
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req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE);
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return -ENOSPC;
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}
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if (req_mgr_h->q_free_slots >= total_seq_len)
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return 0;
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/* Wait for space in HW queue. Poll constant num of iterations. */
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for (poll_queue = 0; poll_queue < CC_MAX_POLL_ITER ; poll_queue++) {
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req_mgr_h->q_free_slots =
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cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));
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if (req_mgr_h->q_free_slots < req_mgr_h->min_free_hw_slots)
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req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots;
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if (req_mgr_h->q_free_slots >= total_seq_len) {
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/* If there is enough place return */
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return 0;
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}
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dev_dbg(dev, "HW FIFO is full. q_free_slots=%d total_seq_len=%d\n",
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req_mgr_h->q_free_slots, total_seq_len);
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}
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/* No room in the HW queue try again later */
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dev_dbg(dev, "HW FIFO full, timeout. req_queue_head=%d sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n",
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req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE,
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req_mgr_h->q_free_slots, total_seq_len);
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return -ENOSPC;
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}
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/*!
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* Enqueue caller request to crypto hardware.
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* Need to be called with HW lock held and PM running
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*
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* \param drvdata
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* \param cc_req The request to enqueue
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* \param desc The crypto sequence
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* \param len The crypto sequence length
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* \param add_comp If "true": add an artificial dout DMA to mark completion
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*
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* \return int Returns -EINPROGRESS or error code
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*/
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static int cc_do_send_request(struct cc_drvdata *drvdata,
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struct cc_crypto_req *cc_req,
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struct cc_hw_desc *desc, unsigned int len,
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bool add_comp, bool ivgen)
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{
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struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
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unsigned int used_sw_slots;
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unsigned int iv_seq_len = 0;
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unsigned int total_seq_len = len; /*initial sequence length*/
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struct cc_hw_desc iv_seq[CC_IVPOOL_SEQ_LEN];
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struct device *dev = drvdata_to_dev(drvdata);
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int rc;
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if (ivgen) {
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dev_dbg(dev, "Acquire IV from pool into %d DMA addresses %pad, %pad, %pad, IV-size=%u\n",
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cc_req->ivgen_dma_addr_len,
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&cc_req->ivgen_dma_addr[0],
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&cc_req->ivgen_dma_addr[1],
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&cc_req->ivgen_dma_addr[2],
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cc_req->ivgen_size);
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/* Acquire IV from pool */
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rc = cc_get_iv(drvdata, cc_req->ivgen_dma_addr,
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cc_req->ivgen_dma_addr_len,
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cc_req->ivgen_size, iv_seq, &iv_seq_len);
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if (rc) {
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dev_err(dev, "Failed to generate IV (rc=%d)\n", rc);
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return rc;
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}
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total_seq_len += iv_seq_len;
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}
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used_sw_slots = ((req_mgr_h->req_queue_head -
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req_mgr_h->req_queue_tail) &
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(MAX_REQUEST_QUEUE_SIZE - 1));
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if (used_sw_slots > req_mgr_h->max_used_sw_slots)
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req_mgr_h->max_used_sw_slots = used_sw_slots;
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/* Enqueue request - must be locked with HW lock*/
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req_mgr_h->req_queue[req_mgr_h->req_queue_head] = *cc_req;
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req_mgr_h->req_queue_head = (req_mgr_h->req_queue_head + 1) &
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(MAX_REQUEST_QUEUE_SIZE - 1);
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/* TODO: Use circ_buf.h ? */
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dev_dbg(dev, "Enqueue request head=%u\n", req_mgr_h->req_queue_head);
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/*
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* We are about to push command to the HW via the command registers
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* that may refernece hsot memory. We need to issue a memory barrier
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* to make sure there are no outstnading memory writes
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*/
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wmb();
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/* STAT_PHASE_4: Push sequence */
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if (ivgen)
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enqueue_seq(drvdata, iv_seq, iv_seq_len);
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enqueue_seq(drvdata, desc, len);
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if (add_comp) {
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enqueue_seq(drvdata, &req_mgr_h->compl_desc, 1);
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total_seq_len++;
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}
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if (req_mgr_h->q_free_slots < total_seq_len) {
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/* This situation should never occur. Maybe indicating problem
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* with resuming power. Set the free slot count to 0 and hope
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* for the best.
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*/
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dev_err(dev, "HW free slot count mismatch.");
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req_mgr_h->q_free_slots = 0;
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} else {
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/* Update the free slots in HW queue */
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req_mgr_h->q_free_slots -= total_seq_len;
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}
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/* Operation still in process */
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return -EINPROGRESS;
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}
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static void cc_enqueue_backlog(struct cc_drvdata *drvdata,
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struct cc_bl_item *bli)
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{
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struct cc_req_mgr_handle *mgr = drvdata->request_mgr_handle;
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spin_lock_bh(&mgr->bl_lock);
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list_add_tail(&bli->list, &mgr->backlog);
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++mgr->bl_len;
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spin_unlock_bh(&mgr->bl_lock);
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tasklet_schedule(&mgr->comptask);
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}
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static void cc_proc_backlog(struct cc_drvdata *drvdata)
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{
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struct cc_req_mgr_handle *mgr = drvdata->request_mgr_handle;
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struct cc_bl_item *bli;
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struct cc_crypto_req *creq;
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struct crypto_async_request *req;
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bool ivgen;
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unsigned int total_len;
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struct device *dev = drvdata_to_dev(drvdata);
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int rc;
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spin_lock(&mgr->bl_lock);
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while (mgr->bl_len) {
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bli = list_first_entry(&mgr->backlog, struct cc_bl_item, list);
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spin_unlock(&mgr->bl_lock);
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creq = &bli->creq;
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req = (struct crypto_async_request *)creq->user_arg;
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/*
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* Notify the request we're moving out of the backlog
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* but only if we haven't done so already.
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*/
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if (!bli->notif) {
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req->complete(req, -EINPROGRESS);
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bli->notif = true;
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}
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ivgen = !!creq->ivgen_dma_addr_len;
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total_len = bli->len + (ivgen ? CC_IVPOOL_SEQ_LEN : 0);
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spin_lock(&mgr->hw_lock);
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rc = cc_queues_status(drvdata, mgr, total_len);
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if (rc) {
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/*
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* There is still not room in the FIFO for
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* this request. Bail out. We'll return here
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* on the next completion irq.
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*/
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spin_unlock(&mgr->hw_lock);
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return;
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}
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rc = cc_do_send_request(drvdata, &bli->creq, bli->desc,
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bli->len, false, ivgen);
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spin_unlock(&mgr->hw_lock);
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if (rc != -EINPROGRESS) {
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cc_pm_put_suspend(dev);
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creq->user_cb(dev, req, rc);
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}
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/* Remove ourselves from the backlog list */
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spin_lock(&mgr->bl_lock);
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list_del(&bli->list);
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--mgr->bl_len;
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}
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spin_unlock(&mgr->bl_lock);
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}
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int cc_send_request(struct cc_drvdata *drvdata, struct cc_crypto_req *cc_req,
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struct cc_hw_desc *desc, unsigned int len,
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struct crypto_async_request *req)
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{
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int rc;
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struct cc_req_mgr_handle *mgr = drvdata->request_mgr_handle;
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bool ivgen = !!cc_req->ivgen_dma_addr_len;
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unsigned int total_len = len + (ivgen ? CC_IVPOOL_SEQ_LEN : 0);
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struct device *dev = drvdata_to_dev(drvdata);
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bool backlog_ok = req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG;
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gfp_t flags = cc_gfp_flags(req);
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struct cc_bl_item *bli;
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rc = cc_pm_get(dev);
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if (rc) {
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dev_err(dev, "ssi_power_mgr_runtime_get returned %x\n", rc);
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return rc;
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}
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spin_lock_bh(&mgr->hw_lock);
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rc = cc_queues_status(drvdata, mgr, total_len);
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#ifdef CC_DEBUG_FORCE_BACKLOG
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if (backlog_ok)
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rc = -ENOSPC;
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#endif /* CC_DEBUG_FORCE_BACKLOG */
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if (rc == -ENOSPC && backlog_ok) {
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spin_unlock_bh(&mgr->hw_lock);
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bli = kmalloc(sizeof(*bli), flags);
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if (!bli) {
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cc_pm_put_suspend(dev);
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return -ENOMEM;
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}
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memcpy(&bli->creq, cc_req, sizeof(*cc_req));
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memcpy(&bli->desc, desc, len * sizeof(*desc));
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bli->len = len;
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bli->notif = false;
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cc_enqueue_backlog(drvdata, bli);
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return -EBUSY;
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}
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if (!rc)
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rc = cc_do_send_request(drvdata, cc_req, desc, len, false,
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ivgen);
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spin_unlock_bh(&mgr->hw_lock);
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return rc;
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}
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int cc_send_sync_request(struct cc_drvdata *drvdata,
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struct cc_crypto_req *cc_req, struct cc_hw_desc *desc,
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unsigned int len)
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{
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int rc;
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
struct cc_req_mgr_handle *mgr = drvdata->request_mgr_handle;
|
|
|
|
init_completion(&cc_req->seq_compl);
|
|
cc_req->user_cb = request_mgr_complete;
|
|
cc_req->user_arg = &cc_req->seq_compl;
|
|
|
|
rc = cc_pm_get(dev);
|
|
if (rc) {
|
|
dev_err(dev, "ssi_power_mgr_runtime_get returned %x\n", rc);
|
|
return rc;
|
|
}
|
|
|
|
while (true) {
|
|
spin_lock_bh(&mgr->hw_lock);
|
|
rc = cc_queues_status(drvdata, mgr, len + 1);
|
|
|
|
if (!rc)
|
|
break;
|
|
|
|
spin_unlock_bh(&mgr->hw_lock);
|
|
if (rc != -EAGAIN) {
|
|
cc_pm_put_suspend(dev);
|
|
return rc;
|
|
}
|
|
wait_for_completion_interruptible(&drvdata->hw_queue_avail);
|
|
reinit_completion(&drvdata->hw_queue_avail);
|
|
}
|
|
|
|
rc = cc_do_send_request(drvdata, cc_req, desc, len, true, false);
|
|
spin_unlock_bh(&mgr->hw_lock);
|
|
|
|
if (rc != -EINPROGRESS) {
|
|
cc_pm_put_suspend(dev);
|
|
return rc;
|
|
}
|
|
|
|
wait_for_completion(&cc_req->seq_compl);
|
|
return 0;
|
|
}
|
|
|
|
/*!
|
|
* Enqueue caller request to crypto hardware during init process.
|
|
* assume this function is not called in middle of a flow,
|
|
* since we set QUEUE_LAST_IND flag in the last descriptor.
|
|
*
|
|
* \param drvdata
|
|
* \param desc The crypto sequence
|
|
* \param len The crypto sequence length
|
|
*
|
|
* \return int Returns "0" upon success
|
|
*/
|
|
int send_request_init(struct cc_drvdata *drvdata, struct cc_hw_desc *desc,
|
|
unsigned int len)
|
|
{
|
|
struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
|
|
unsigned int total_seq_len = len; /*initial sequence length*/
|
|
int rc = 0;
|
|
|
|
/* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT.
|
|
*/
|
|
rc = cc_queues_status(drvdata, req_mgr_h, total_seq_len);
|
|
if (rc)
|
|
return rc;
|
|
|
|
set_queue_last_ind(drvdata, &desc[(len - 1)]);
|
|
|
|
/*
|
|
* We are about to push command to the HW via the command registers
|
|
* that may refernece hsot memory. We need to issue a memory barrier
|
|
* to make sure there are no outstnading memory writes
|
|
*/
|
|
wmb();
|
|
enqueue_seq(drvdata, desc, len);
|
|
|
|
/* Update the free slots in HW queue */
|
|
req_mgr_h->q_free_slots =
|
|
cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void complete_request(struct cc_drvdata *drvdata)
|
|
{
|
|
struct cc_req_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
complete(&drvdata->hw_queue_avail);
|
|
#ifdef COMP_IN_WQ
|
|
queue_delayed_work(request_mgr_handle->workq,
|
|
&request_mgr_handle->compwork, 0);
|
|
#else
|
|
tasklet_schedule(&request_mgr_handle->comptask);
|
|
#endif
|
|
}
|
|
|
|
#ifdef COMP_IN_WQ
|
|
static void comp_work_handler(struct work_struct *work)
|
|
{
|
|
struct cc_drvdata *drvdata =
|
|
container_of(work, struct cc_drvdata, compwork.work);
|
|
|
|
comp_handler((unsigned long)drvdata);
|
|
}
|
|
#endif
|
|
|
|
static void proc_completions(struct cc_drvdata *drvdata)
|
|
{
|
|
struct cc_crypto_req *cc_req;
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
struct cc_req_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
unsigned int *tail = &request_mgr_handle->req_queue_tail;
|
|
unsigned int *head = &request_mgr_handle->req_queue_head;
|
|
|
|
while (request_mgr_handle->axi_completed) {
|
|
request_mgr_handle->axi_completed--;
|
|
|
|
/* Dequeue request */
|
|
if (*head == *tail) {
|
|
/* We are supposed to handle a completion but our
|
|
* queue is empty. This is not normal. Return and
|
|
* hope for the best.
|
|
*/
|
|
dev_err(dev, "Request queue is empty head == tail %u\n",
|
|
*head);
|
|
break;
|
|
}
|
|
|
|
cc_req = &request_mgr_handle->req_queue[*tail];
|
|
|
|
if (cc_req->user_cb)
|
|
cc_req->user_cb(dev, cc_req->user_arg, 0);
|
|
*tail = (*tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
|
|
dev_dbg(dev, "Dequeue request tail=%u\n", *tail);
|
|
dev_dbg(dev, "Request completed. axi_completed=%d\n",
|
|
request_mgr_handle->axi_completed);
|
|
cc_pm_put_suspend(dev);
|
|
}
|
|
}
|
|
|
|
static inline u32 cc_axi_comp_count(struct cc_drvdata *drvdata)
|
|
{
|
|
return FIELD_GET(AXIM_MON_COMP_VALUE,
|
|
cc_ioread(drvdata, drvdata->axim_mon_offset));
|
|
}
|
|
|
|
/* Deferred service handler, run as interrupt-fired tasklet */
|
|
static void comp_handler(unsigned long devarg)
|
|
{
|
|
struct cc_drvdata *drvdata = (struct cc_drvdata *)devarg;
|
|
struct cc_req_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
u32 irq;
|
|
|
|
irq = (drvdata->irq & CC_COMP_IRQ_MASK);
|
|
|
|
if (irq & CC_COMP_IRQ_MASK) {
|
|
/* To avoid the interrupt from firing as we unmask it,
|
|
* we clear it now
|
|
*/
|
|
cc_iowrite(drvdata, CC_REG(HOST_ICR), CC_COMP_IRQ_MASK);
|
|
|
|
/* Avoid race with above clear: Test completion counter
|
|
* once more
|
|
*/
|
|
request_mgr_handle->axi_completed +=
|
|
cc_axi_comp_count(drvdata);
|
|
|
|
while (request_mgr_handle->axi_completed) {
|
|
do {
|
|
proc_completions(drvdata);
|
|
/* At this point (after proc_completions()),
|
|
* request_mgr_handle->axi_completed is 0.
|
|
*/
|
|
request_mgr_handle->axi_completed =
|
|
cc_axi_comp_count(drvdata);
|
|
} while (request_mgr_handle->axi_completed > 0);
|
|
|
|
cc_iowrite(drvdata, CC_REG(HOST_ICR),
|
|
CC_COMP_IRQ_MASK);
|
|
|
|
request_mgr_handle->axi_completed +=
|
|
cc_axi_comp_count(drvdata);
|
|
}
|
|
}
|
|
/* after verifing that there is nothing to do,
|
|
* unmask AXI completion interrupt
|
|
*/
|
|
cc_iowrite(drvdata, CC_REG(HOST_IMR),
|
|
cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~irq);
|
|
|
|
cc_proc_backlog(drvdata);
|
|
}
|
|
|
|
/*
|
|
* resume the queue configuration - no need to take the lock as this happens
|
|
* inside the spin lock protection
|
|
*/
|
|
#if defined(CONFIG_PM)
|
|
int cc_resume_req_queue(struct cc_drvdata *drvdata)
|
|
{
|
|
struct cc_req_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
spin_lock_bh(&request_mgr_handle->hw_lock);
|
|
request_mgr_handle->is_runtime_suspended = false;
|
|
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* suspend the queue configuration. Since it is used for the runtime suspend
|
|
* only verify that the queue can be suspended.
|
|
*/
|
|
int cc_suspend_req_queue(struct cc_drvdata *drvdata)
|
|
{
|
|
struct cc_req_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
/* lock the send_request */
|
|
spin_lock_bh(&request_mgr_handle->hw_lock);
|
|
if (request_mgr_handle->req_queue_head !=
|
|
request_mgr_handle->req_queue_tail) {
|
|
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
|
return -EBUSY;
|
|
}
|
|
request_mgr_handle->is_runtime_suspended = true;
|
|
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool cc_req_queue_suspended(struct cc_drvdata *drvdata)
|
|
{
|
|
struct cc_req_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
return request_mgr_handle->is_runtime_suspended;
|
|
}
|
|
|
|
#endif
|