mirror of https://gitee.com/openkylin/linux.git
1644 lines
38 KiB
C
1644 lines
38 KiB
C
/*
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* This file is part of STM32 Crypto driver for Linux.
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*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics.
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*
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* License terms: GPL V2.0.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/clk.h>
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#include <linux/crypto.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <crypto/engine.h>
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#include <crypto/hash.h>
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#include <crypto/md5.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/sha.h>
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#include <crypto/internal/hash.h>
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#define HASH_CR 0x00
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#define HASH_DIN 0x04
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#define HASH_STR 0x08
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#define HASH_IMR 0x20
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#define HASH_SR 0x24
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#define HASH_CSR(x) (0x0F8 + ((x) * 0x04))
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#define HASH_HREG(x) (0x310 + ((x) * 0x04))
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#define HASH_HWCFGR 0x3F0
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#define HASH_VER 0x3F4
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#define HASH_ID 0x3F8
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/* Control Register */
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#define HASH_CR_INIT BIT(2)
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#define HASH_CR_DMAE BIT(3)
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#define HASH_CR_DATATYPE_POS 4
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#define HASH_CR_MODE BIT(6)
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#define HASH_CR_MDMAT BIT(13)
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#define HASH_CR_DMAA BIT(14)
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#define HASH_CR_LKEY BIT(16)
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#define HASH_CR_ALGO_SHA1 0x0
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#define HASH_CR_ALGO_MD5 0x80
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#define HASH_CR_ALGO_SHA224 0x40000
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#define HASH_CR_ALGO_SHA256 0x40080
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/* Interrupt */
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#define HASH_DINIE BIT(0)
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#define HASH_DCIE BIT(1)
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/* Interrupt Mask */
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#define HASH_MASK_CALC_COMPLETION BIT(0)
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#define HASH_MASK_DATA_INPUT BIT(1)
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/* Context swap register */
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#define HASH_CSR_REGISTER_NUMBER 53
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/* Status Flags */
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#define HASH_SR_DATA_INPUT_READY BIT(0)
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#define HASH_SR_OUTPUT_READY BIT(1)
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#define HASH_SR_DMA_ACTIVE BIT(2)
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#define HASH_SR_BUSY BIT(3)
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/* STR Register */
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#define HASH_STR_NBLW_MASK GENMASK(4, 0)
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#define HASH_STR_DCAL BIT(8)
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#define HASH_FLAGS_INIT BIT(0)
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#define HASH_FLAGS_OUTPUT_READY BIT(1)
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#define HASH_FLAGS_CPU BIT(2)
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#define HASH_FLAGS_DMA_READY BIT(3)
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#define HASH_FLAGS_DMA_ACTIVE BIT(4)
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#define HASH_FLAGS_HMAC_INIT BIT(5)
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#define HASH_FLAGS_HMAC_FINAL BIT(6)
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#define HASH_FLAGS_HMAC_KEY BIT(7)
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#define HASH_FLAGS_FINAL BIT(15)
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#define HASH_FLAGS_FINUP BIT(16)
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#define HASH_FLAGS_ALGO_MASK GENMASK(21, 18)
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#define HASH_FLAGS_MD5 BIT(18)
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#define HASH_FLAGS_SHA1 BIT(19)
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#define HASH_FLAGS_SHA224 BIT(20)
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#define HASH_FLAGS_SHA256 BIT(21)
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#define HASH_FLAGS_ERRORS BIT(22)
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#define HASH_FLAGS_HMAC BIT(23)
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#define HASH_OP_UPDATE 1
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#define HASH_OP_FINAL 2
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enum stm32_hash_data_format {
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HASH_DATA_32_BITS = 0x0,
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HASH_DATA_16_BITS = 0x1,
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HASH_DATA_8_BITS = 0x2,
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HASH_DATA_1_BIT = 0x3
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};
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#define HASH_BUFLEN 256
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#define HASH_LONG_KEY 64
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#define HASH_MAX_KEY_SIZE (SHA256_BLOCK_SIZE * 8)
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#define HASH_QUEUE_LENGTH 16
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#define HASH_DMA_THRESHOLD 50
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#define HASH_AUTOSUSPEND_DELAY 50
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struct stm32_hash_ctx {
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struct crypto_engine_ctx enginectx;
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struct stm32_hash_dev *hdev;
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unsigned long flags;
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u8 key[HASH_MAX_KEY_SIZE];
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int keylen;
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};
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struct stm32_hash_request_ctx {
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struct stm32_hash_dev *hdev;
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unsigned long flags;
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unsigned long op;
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u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
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size_t digcnt;
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size_t bufcnt;
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size_t buflen;
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/* DMA */
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struct scatterlist *sg;
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unsigned int offset;
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unsigned int total;
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struct scatterlist sg_key;
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dma_addr_t dma_addr;
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size_t dma_ct;
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int nents;
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u8 data_type;
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u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32));
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/* Export Context */
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u32 *hw_context;
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};
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struct stm32_hash_algs_info {
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struct ahash_alg *algs_list;
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size_t size;
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};
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struct stm32_hash_pdata {
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struct stm32_hash_algs_info *algs_info;
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size_t algs_info_size;
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};
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struct stm32_hash_dev {
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struct list_head list;
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struct device *dev;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *io_base;
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phys_addr_t phys_base;
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u32 dma_mode;
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u32 dma_maxburst;
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spinlock_t lock; /* lock to protect queue */
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struct ahash_request *req;
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struct crypto_engine *engine;
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int err;
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unsigned long flags;
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struct dma_chan *dma_lch;
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struct completion dma_completion;
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const struct stm32_hash_pdata *pdata;
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};
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struct stm32_hash_drv {
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struct list_head dev_list;
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spinlock_t lock; /* List protection access */
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};
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static struct stm32_hash_drv stm32_hash = {
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.dev_list = LIST_HEAD_INIT(stm32_hash.dev_list),
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.lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock),
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};
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static void stm32_hash_dma_callback(void *param);
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static inline u32 stm32_hash_read(struct stm32_hash_dev *hdev, u32 offset)
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{
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return readl_relaxed(hdev->io_base + offset);
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}
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static inline void stm32_hash_write(struct stm32_hash_dev *hdev,
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u32 offset, u32 value)
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{
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writel_relaxed(value, hdev->io_base + offset);
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}
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static inline int stm32_hash_wait_busy(struct stm32_hash_dev *hdev)
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{
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u32 status;
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return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
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!(status & HASH_SR_BUSY), 10, 10000);
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}
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static void stm32_hash_set_nblw(struct stm32_hash_dev *hdev, int length)
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{
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u32 reg;
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reg = stm32_hash_read(hdev, HASH_STR);
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reg &= ~(HASH_STR_NBLW_MASK);
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reg |= (8U * ((length) % 4U));
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stm32_hash_write(hdev, HASH_STR, reg);
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}
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static int stm32_hash_write_key(struct stm32_hash_dev *hdev)
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{
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
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struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
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u32 reg;
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int keylen = ctx->keylen;
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void *key = ctx->key;
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if (keylen) {
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stm32_hash_set_nblw(hdev, keylen);
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while (keylen > 0) {
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stm32_hash_write(hdev, HASH_DIN, *(u32 *)key);
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keylen -= 4;
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key += 4;
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}
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reg = stm32_hash_read(hdev, HASH_STR);
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reg |= HASH_STR_DCAL;
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stm32_hash_write(hdev, HASH_STR, reg);
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return -EINPROGRESS;
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}
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return 0;
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}
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static void stm32_hash_write_ctrl(struct stm32_hash_dev *hdev)
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{
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struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
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struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
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u32 reg = HASH_CR_INIT;
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if (!(hdev->flags & HASH_FLAGS_INIT)) {
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switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
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case HASH_FLAGS_MD5:
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reg |= HASH_CR_ALGO_MD5;
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break;
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case HASH_FLAGS_SHA1:
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reg |= HASH_CR_ALGO_SHA1;
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break;
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case HASH_FLAGS_SHA224:
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reg |= HASH_CR_ALGO_SHA224;
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break;
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case HASH_FLAGS_SHA256:
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reg |= HASH_CR_ALGO_SHA256;
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break;
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default:
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reg |= HASH_CR_ALGO_MD5;
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}
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reg |= (rctx->data_type << HASH_CR_DATATYPE_POS);
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if (rctx->flags & HASH_FLAGS_HMAC) {
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hdev->flags |= HASH_FLAGS_HMAC;
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reg |= HASH_CR_MODE;
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if (ctx->keylen > HASH_LONG_KEY)
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reg |= HASH_CR_LKEY;
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}
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stm32_hash_write(hdev, HASH_IMR, HASH_DCIE);
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stm32_hash_write(hdev, HASH_CR, reg);
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hdev->flags |= HASH_FLAGS_INIT;
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dev_dbg(hdev->dev, "Write Control %x\n", reg);
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}
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}
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static void stm32_hash_append_sg(struct stm32_hash_request_ctx *rctx)
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{
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size_t count;
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while ((rctx->bufcnt < rctx->buflen) && rctx->total) {
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count = min(rctx->sg->length - rctx->offset, rctx->total);
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count = min(count, rctx->buflen - rctx->bufcnt);
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if (count <= 0) {
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if ((rctx->sg->length == 0) && !sg_is_last(rctx->sg)) {
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rctx->sg = sg_next(rctx->sg);
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continue;
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} else {
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break;
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}
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}
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scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, rctx->sg,
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rctx->offset, count, 0);
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rctx->bufcnt += count;
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rctx->offset += count;
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rctx->total -= count;
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if (rctx->offset == rctx->sg->length) {
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rctx->sg = sg_next(rctx->sg);
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if (rctx->sg)
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rctx->offset = 0;
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else
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rctx->total = 0;
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}
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}
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}
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static int stm32_hash_xmit_cpu(struct stm32_hash_dev *hdev,
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const u8 *buf, size_t length, int final)
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{
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unsigned int count, len32;
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const u32 *buffer = (const u32 *)buf;
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u32 reg;
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if (final)
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hdev->flags |= HASH_FLAGS_FINAL;
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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dev_dbg(hdev->dev, "%s: length: %d, final: %x len32 %i\n",
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__func__, length, final, len32);
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hdev->flags |= HASH_FLAGS_CPU;
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stm32_hash_write_ctrl(hdev);
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if (stm32_hash_wait_busy(hdev))
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return -ETIMEDOUT;
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if ((hdev->flags & HASH_FLAGS_HMAC) &&
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(hdev->flags & ~HASH_FLAGS_HMAC_KEY)) {
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hdev->flags |= HASH_FLAGS_HMAC_KEY;
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stm32_hash_write_key(hdev);
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if (stm32_hash_wait_busy(hdev))
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return -ETIMEDOUT;
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}
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for (count = 0; count < len32; count++)
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stm32_hash_write(hdev, HASH_DIN, buffer[count]);
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if (final) {
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stm32_hash_set_nblw(hdev, length);
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reg = stm32_hash_read(hdev, HASH_STR);
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reg |= HASH_STR_DCAL;
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stm32_hash_write(hdev, HASH_STR, reg);
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if (hdev->flags & HASH_FLAGS_HMAC) {
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if (stm32_hash_wait_busy(hdev))
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return -ETIMEDOUT;
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stm32_hash_write_key(hdev);
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}
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return -EINPROGRESS;
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}
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return 0;
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}
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static int stm32_hash_update_cpu(struct stm32_hash_dev *hdev)
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{
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struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
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int bufcnt, err = 0, final;
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dev_dbg(hdev->dev, "%s flags %lx\n", __func__, rctx->flags);
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final = (rctx->flags & HASH_FLAGS_FINUP);
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while ((rctx->total >= rctx->buflen) ||
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(rctx->bufcnt + rctx->total >= rctx->buflen)) {
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stm32_hash_append_sg(rctx);
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bufcnt = rctx->bufcnt;
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rctx->bufcnt = 0;
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err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 0);
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}
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stm32_hash_append_sg(rctx);
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if (final) {
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bufcnt = rctx->bufcnt;
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rctx->bufcnt = 0;
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err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt,
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(rctx->flags & HASH_FLAGS_FINUP));
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}
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return err;
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}
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static int stm32_hash_xmit_dma(struct stm32_hash_dev *hdev,
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struct scatterlist *sg, int length, int mdma)
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{
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struct dma_async_tx_descriptor *in_desc;
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dma_cookie_t cookie;
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u32 reg;
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int err;
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in_desc = dmaengine_prep_slave_sg(hdev->dma_lch, sg, 1,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT |
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DMA_CTRL_ACK);
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if (!in_desc) {
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dev_err(hdev->dev, "dmaengine_prep_slave error\n");
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return -ENOMEM;
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}
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reinit_completion(&hdev->dma_completion);
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in_desc->callback = stm32_hash_dma_callback;
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in_desc->callback_param = hdev;
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hdev->flags |= HASH_FLAGS_FINAL;
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hdev->flags |= HASH_FLAGS_DMA_ACTIVE;
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reg = stm32_hash_read(hdev, HASH_CR);
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if (mdma)
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reg |= HASH_CR_MDMAT;
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else
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reg &= ~HASH_CR_MDMAT;
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reg |= HASH_CR_DMAE;
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stm32_hash_write(hdev, HASH_CR, reg);
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stm32_hash_set_nblw(hdev, length);
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cookie = dmaengine_submit(in_desc);
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err = dma_submit_error(cookie);
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if (err)
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return -ENOMEM;
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dma_async_issue_pending(hdev->dma_lch);
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if (!wait_for_completion_interruptible_timeout(&hdev->dma_completion,
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msecs_to_jiffies(100)))
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err = -ETIMEDOUT;
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if (dma_async_is_tx_complete(hdev->dma_lch, cookie,
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NULL, NULL) != DMA_COMPLETE)
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err = -ETIMEDOUT;
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if (err) {
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dev_err(hdev->dev, "DMA Error %i\n", err);
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dmaengine_terminate_all(hdev->dma_lch);
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return err;
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}
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return -EINPROGRESS;
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}
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static void stm32_hash_dma_callback(void *param)
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{
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struct stm32_hash_dev *hdev = param;
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complete(&hdev->dma_completion);
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hdev->flags |= HASH_FLAGS_DMA_READY;
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}
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static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev)
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{
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struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
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struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
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int err;
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if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) {
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err = stm32_hash_write_key(hdev);
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if (stm32_hash_wait_busy(hdev))
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return -ETIMEDOUT;
|
|
} else {
|
|
if (!(hdev->flags & HASH_FLAGS_HMAC_KEY))
|
|
sg_init_one(&rctx->sg_key, ctx->key,
|
|
ALIGN(ctx->keylen, sizeof(u32)));
|
|
|
|
rctx->dma_ct = dma_map_sg(hdev->dev, &rctx->sg_key, 1,
|
|
DMA_TO_DEVICE);
|
|
if (rctx->dma_ct == 0) {
|
|
dev_err(hdev->dev, "dma_map_sg error\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
err = stm32_hash_xmit_dma(hdev, &rctx->sg_key, ctx->keylen, 0);
|
|
|
|
dma_unmap_sg(hdev->dev, &rctx->sg_key, 1, DMA_TO_DEVICE);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int stm32_hash_dma_init(struct stm32_hash_dev *hdev)
|
|
{
|
|
struct dma_slave_config dma_conf;
|
|
int err;
|
|
|
|
memset(&dma_conf, 0, sizeof(dma_conf));
|
|
|
|
dma_conf.direction = DMA_MEM_TO_DEV;
|
|
dma_conf.dst_addr = hdev->phys_base + HASH_DIN;
|
|
dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
dma_conf.src_maxburst = hdev->dma_maxburst;
|
|
dma_conf.dst_maxburst = hdev->dma_maxburst;
|
|
dma_conf.device_fc = false;
|
|
|
|
hdev->dma_lch = dma_request_slave_channel(hdev->dev, "in");
|
|
if (!hdev->dma_lch) {
|
|
dev_err(hdev->dev, "Couldn't acquire a slave DMA channel.\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
err = dmaengine_slave_config(hdev->dma_lch, &dma_conf);
|
|
if (err) {
|
|
dma_release_channel(hdev->dma_lch);
|
|
hdev->dma_lch = NULL;
|
|
dev_err(hdev->dev, "Couldn't configure DMA slave.\n");
|
|
return err;
|
|
}
|
|
|
|
init_completion(&hdev->dma_completion);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
|
|
struct scatterlist sg[1], *tsg;
|
|
int err = 0, len = 0, reg, ncp = 0;
|
|
unsigned int i;
|
|
u32 *buffer = (void *)rctx->buffer;
|
|
|
|
rctx->sg = hdev->req->src;
|
|
rctx->total = hdev->req->nbytes;
|
|
|
|
rctx->nents = sg_nents(rctx->sg);
|
|
|
|
if (rctx->nents < 0)
|
|
return -EINVAL;
|
|
|
|
stm32_hash_write_ctrl(hdev);
|
|
|
|
if (hdev->flags & HASH_FLAGS_HMAC) {
|
|
err = stm32_hash_hmac_dma_send(hdev);
|
|
if (err != -EINPROGRESS)
|
|
return err;
|
|
}
|
|
|
|
for_each_sg(rctx->sg, tsg, rctx->nents, i) {
|
|
len = sg->length;
|
|
|
|
sg[0] = *tsg;
|
|
if (sg_is_last(sg)) {
|
|
if (hdev->dma_mode == 1) {
|
|
len = (ALIGN(sg->length, 16) - 16);
|
|
|
|
ncp = sg_pcopy_to_buffer(
|
|
rctx->sg, rctx->nents,
|
|
rctx->buffer, sg->length - len,
|
|
rctx->total - sg->length + len);
|
|
|
|
sg->length = len;
|
|
} else {
|
|
if (!(IS_ALIGNED(sg->length, sizeof(u32)))) {
|
|
len = sg->length;
|
|
sg->length = ALIGN(sg->length,
|
|
sizeof(u32));
|
|
}
|
|
}
|
|
}
|
|
|
|
rctx->dma_ct = dma_map_sg(hdev->dev, sg, 1,
|
|
DMA_TO_DEVICE);
|
|
if (rctx->dma_ct == 0) {
|
|
dev_err(hdev->dev, "dma_map_sg error\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
err = stm32_hash_xmit_dma(hdev, sg, len,
|
|
!sg_is_last(sg));
|
|
|
|
dma_unmap_sg(hdev->dev, sg, 1, DMA_TO_DEVICE);
|
|
|
|
if (err == -ENOMEM)
|
|
return err;
|
|
}
|
|
|
|
if (hdev->dma_mode == 1) {
|
|
if (stm32_hash_wait_busy(hdev))
|
|
return -ETIMEDOUT;
|
|
reg = stm32_hash_read(hdev, HASH_CR);
|
|
reg &= ~HASH_CR_DMAE;
|
|
reg |= HASH_CR_DMAA;
|
|
stm32_hash_write(hdev, HASH_CR, reg);
|
|
|
|
if (ncp) {
|
|
memset(buffer + ncp, 0,
|
|
DIV_ROUND_UP(ncp, sizeof(u32)) - ncp);
|
|
writesl(hdev->io_base + HASH_DIN, buffer,
|
|
DIV_ROUND_UP(ncp, sizeof(u32)));
|
|
}
|
|
stm32_hash_set_nblw(hdev, ncp);
|
|
reg = stm32_hash_read(hdev, HASH_STR);
|
|
reg |= HASH_STR_DCAL;
|
|
stm32_hash_write(hdev, HASH_STR, reg);
|
|
err = -EINPROGRESS;
|
|
}
|
|
|
|
if (hdev->flags & HASH_FLAGS_HMAC) {
|
|
if (stm32_hash_wait_busy(hdev))
|
|
return -ETIMEDOUT;
|
|
err = stm32_hash_hmac_dma_send(hdev);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static struct stm32_hash_dev *stm32_hash_find_dev(struct stm32_hash_ctx *ctx)
|
|
{
|
|
struct stm32_hash_dev *hdev = NULL, *tmp;
|
|
|
|
spin_lock_bh(&stm32_hash.lock);
|
|
if (!ctx->hdev) {
|
|
list_for_each_entry(tmp, &stm32_hash.dev_list, list) {
|
|
hdev = tmp;
|
|
break;
|
|
}
|
|
ctx->hdev = hdev;
|
|
} else {
|
|
hdev = ctx->hdev;
|
|
}
|
|
|
|
spin_unlock_bh(&stm32_hash.lock);
|
|
|
|
return hdev;
|
|
}
|
|
|
|
static bool stm32_hash_dma_aligned_data(struct ahash_request *req)
|
|
{
|
|
struct scatterlist *sg;
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
int i;
|
|
|
|
if (req->nbytes <= HASH_DMA_THRESHOLD)
|
|
return false;
|
|
|
|
if (sg_nents(req->src) > 1) {
|
|
if (hdev->dma_mode == 1)
|
|
return false;
|
|
for_each_sg(req->src, sg, sg_nents(req->src), i) {
|
|
if ((!IS_ALIGNED(sg->length, sizeof(u32))) &&
|
|
(!sg_is_last(sg)))
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (req->src->offset % 4)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static int stm32_hash_init(struct ahash_request *req)
|
|
{
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
rctx->hdev = hdev;
|
|
|
|
rctx->flags = HASH_FLAGS_CPU;
|
|
|
|
rctx->digcnt = crypto_ahash_digestsize(tfm);
|
|
switch (rctx->digcnt) {
|
|
case MD5_DIGEST_SIZE:
|
|
rctx->flags |= HASH_FLAGS_MD5;
|
|
break;
|
|
case SHA1_DIGEST_SIZE:
|
|
rctx->flags |= HASH_FLAGS_SHA1;
|
|
break;
|
|
case SHA224_DIGEST_SIZE:
|
|
rctx->flags |= HASH_FLAGS_SHA224;
|
|
break;
|
|
case SHA256_DIGEST_SIZE:
|
|
rctx->flags |= HASH_FLAGS_SHA256;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
rctx->bufcnt = 0;
|
|
rctx->buflen = HASH_BUFLEN;
|
|
rctx->total = 0;
|
|
rctx->offset = 0;
|
|
rctx->data_type = HASH_DATA_8_BITS;
|
|
|
|
memset(rctx->buffer, 0, HASH_BUFLEN);
|
|
|
|
if (ctx->flags & HASH_FLAGS_HMAC)
|
|
rctx->flags |= HASH_FLAGS_HMAC;
|
|
|
|
dev_dbg(hdev->dev, "%s Flags %lx\n", __func__, rctx->flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_update_req(struct stm32_hash_dev *hdev)
|
|
{
|
|
return stm32_hash_update_cpu(hdev);
|
|
}
|
|
|
|
static int stm32_hash_final_req(struct stm32_hash_dev *hdev)
|
|
{
|
|
struct ahash_request *req = hdev->req;
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
int err;
|
|
int buflen = rctx->bufcnt;
|
|
|
|
rctx->bufcnt = 0;
|
|
|
|
if (!(rctx->flags & HASH_FLAGS_CPU))
|
|
err = stm32_hash_dma_send(hdev);
|
|
else
|
|
err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1);
|
|
|
|
|
|
return err;
|
|
}
|
|
|
|
static void stm32_hash_copy_hash(struct ahash_request *req)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
u32 *hash = (u32 *)rctx->digest;
|
|
unsigned int i, hashsize;
|
|
|
|
switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
|
|
case HASH_FLAGS_MD5:
|
|
hashsize = MD5_DIGEST_SIZE;
|
|
break;
|
|
case HASH_FLAGS_SHA1:
|
|
hashsize = SHA1_DIGEST_SIZE;
|
|
break;
|
|
case HASH_FLAGS_SHA224:
|
|
hashsize = SHA224_DIGEST_SIZE;
|
|
break;
|
|
case HASH_FLAGS_SHA256:
|
|
hashsize = SHA256_DIGEST_SIZE;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < hashsize / sizeof(u32); i++)
|
|
hash[i] = be32_to_cpu(stm32_hash_read(rctx->hdev,
|
|
HASH_HREG(i)));
|
|
}
|
|
|
|
static int stm32_hash_finish(struct ahash_request *req)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
if (!req->result)
|
|
return -EINVAL;
|
|
|
|
memcpy(req->result, rctx->digest, rctx->digcnt);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void stm32_hash_finish_req(struct ahash_request *req, int err)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
struct stm32_hash_dev *hdev = rctx->hdev;
|
|
|
|
if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {
|
|
stm32_hash_copy_hash(req);
|
|
err = stm32_hash_finish(req);
|
|
hdev->flags &= ~(HASH_FLAGS_FINAL | HASH_FLAGS_CPU |
|
|
HASH_FLAGS_INIT | HASH_FLAGS_DMA_READY |
|
|
HASH_FLAGS_OUTPUT_READY | HASH_FLAGS_HMAC |
|
|
HASH_FLAGS_HMAC_INIT | HASH_FLAGS_HMAC_FINAL |
|
|
HASH_FLAGS_HMAC_KEY);
|
|
} else {
|
|
rctx->flags |= HASH_FLAGS_ERRORS;
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(hdev->dev);
|
|
pm_runtime_put_autosuspend(hdev->dev);
|
|
|
|
crypto_finalize_hash_request(hdev->engine, req, err);
|
|
}
|
|
|
|
static int stm32_hash_hw_init(struct stm32_hash_dev *hdev,
|
|
struct stm32_hash_request_ctx *rctx)
|
|
{
|
|
pm_runtime_get_sync(hdev->dev);
|
|
|
|
if (!(HASH_FLAGS_INIT & hdev->flags)) {
|
|
stm32_hash_write(hdev, HASH_CR, HASH_CR_INIT);
|
|
stm32_hash_write(hdev, HASH_STR, 0);
|
|
stm32_hash_write(hdev, HASH_DIN, 0);
|
|
stm32_hash_write(hdev, HASH_IMR, 0);
|
|
hdev->err = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_one_request(struct crypto_engine *engine, void *areq);
|
|
static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq);
|
|
|
|
static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
|
|
struct ahash_request *req)
|
|
{
|
|
return crypto_transfer_hash_request_to_engine(hdev->engine, req);
|
|
}
|
|
|
|
static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq)
|
|
{
|
|
struct ahash_request *req = container_of(areq, struct ahash_request,
|
|
base);
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
struct stm32_hash_request_ctx *rctx;
|
|
|
|
if (!hdev)
|
|
return -ENODEV;
|
|
|
|
hdev->req = req;
|
|
|
|
rctx = ahash_request_ctx(req);
|
|
|
|
dev_dbg(hdev->dev, "processing new req, op: %lu, nbytes %d\n",
|
|
rctx->op, req->nbytes);
|
|
|
|
return stm32_hash_hw_init(hdev, rctx);
|
|
}
|
|
|
|
static int stm32_hash_one_request(struct crypto_engine *engine, void *areq)
|
|
{
|
|
struct ahash_request *req = container_of(areq, struct ahash_request,
|
|
base);
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
struct stm32_hash_request_ctx *rctx;
|
|
int err = 0;
|
|
|
|
if (!hdev)
|
|
return -ENODEV;
|
|
|
|
hdev->req = req;
|
|
|
|
rctx = ahash_request_ctx(req);
|
|
|
|
if (rctx->op == HASH_OP_UPDATE)
|
|
err = stm32_hash_update_req(hdev);
|
|
else if (rctx->op == HASH_OP_FINAL)
|
|
err = stm32_hash_final_req(hdev);
|
|
|
|
if (err != -EINPROGRESS)
|
|
/* done task will not finish it, so do it here */
|
|
stm32_hash_finish_req(req, err);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_enqueue(struct ahash_request *req, unsigned int op)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
|
|
struct stm32_hash_dev *hdev = ctx->hdev;
|
|
|
|
rctx->op = op;
|
|
|
|
return stm32_hash_handle_queue(hdev, req);
|
|
}
|
|
|
|
static int stm32_hash_update(struct ahash_request *req)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
|
|
return 0;
|
|
|
|
rctx->total = req->nbytes;
|
|
rctx->sg = req->src;
|
|
rctx->offset = 0;
|
|
|
|
if ((rctx->bufcnt + rctx->total < rctx->buflen)) {
|
|
stm32_hash_append_sg(rctx);
|
|
return 0;
|
|
}
|
|
|
|
return stm32_hash_enqueue(req, HASH_OP_UPDATE);
|
|
}
|
|
|
|
static int stm32_hash_final(struct ahash_request *req)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
rctx->flags |= HASH_FLAGS_FINUP;
|
|
|
|
return stm32_hash_enqueue(req, HASH_OP_FINAL);
|
|
}
|
|
|
|
static int stm32_hash_finup(struct ahash_request *req)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
int err1, err2;
|
|
|
|
rctx->flags |= HASH_FLAGS_FINUP;
|
|
|
|
if (hdev->dma_lch && stm32_hash_dma_aligned_data(req))
|
|
rctx->flags &= ~HASH_FLAGS_CPU;
|
|
|
|
err1 = stm32_hash_update(req);
|
|
|
|
if (err1 == -EINPROGRESS || err1 == -EBUSY)
|
|
return err1;
|
|
|
|
/*
|
|
* final() has to be always called to cleanup resources
|
|
* even if update() failed, except EINPROGRESS
|
|
*/
|
|
err2 = stm32_hash_final(req);
|
|
|
|
return err1 ?: err2;
|
|
}
|
|
|
|
static int stm32_hash_digest(struct ahash_request *req)
|
|
{
|
|
return stm32_hash_init(req) ?: stm32_hash_finup(req);
|
|
}
|
|
|
|
static int stm32_hash_export(struct ahash_request *req, void *out)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
u32 *preg;
|
|
unsigned int i;
|
|
|
|
pm_runtime_get_sync(hdev->dev);
|
|
|
|
while (!(stm32_hash_read(hdev, HASH_SR) & HASH_SR_DATA_INPUT_READY))
|
|
cpu_relax();
|
|
|
|
rctx->hw_context = kmalloc_array(3 + HASH_CSR_REGISTER_NUMBER,
|
|
sizeof(u32),
|
|
GFP_KERNEL);
|
|
|
|
preg = rctx->hw_context;
|
|
|
|
*preg++ = stm32_hash_read(hdev, HASH_IMR);
|
|
*preg++ = stm32_hash_read(hdev, HASH_STR);
|
|
*preg++ = stm32_hash_read(hdev, HASH_CR);
|
|
for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
|
|
*preg++ = stm32_hash_read(hdev, HASH_CSR(i));
|
|
|
|
pm_runtime_mark_last_busy(hdev->dev);
|
|
pm_runtime_put_autosuspend(hdev->dev);
|
|
|
|
memcpy(out, rctx, sizeof(*rctx));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_import(struct ahash_request *req, const void *in)
|
|
{
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
const u32 *preg = in;
|
|
u32 reg;
|
|
unsigned int i;
|
|
|
|
memcpy(rctx, in, sizeof(*rctx));
|
|
|
|
preg = rctx->hw_context;
|
|
|
|
pm_runtime_get_sync(hdev->dev);
|
|
|
|
stm32_hash_write(hdev, HASH_IMR, *preg++);
|
|
stm32_hash_write(hdev, HASH_STR, *preg++);
|
|
stm32_hash_write(hdev, HASH_CR, *preg);
|
|
reg = *preg++ | HASH_CR_INIT;
|
|
stm32_hash_write(hdev, HASH_CR, reg);
|
|
|
|
for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
|
|
stm32_hash_write(hdev, HASH_CSR(i), *preg++);
|
|
|
|
pm_runtime_mark_last_busy(hdev->dev);
|
|
pm_runtime_put_autosuspend(hdev->dev);
|
|
|
|
kfree(rctx->hw_context);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_setkey(struct crypto_ahash *tfm,
|
|
const u8 *key, unsigned int keylen)
|
|
{
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
if (keylen <= HASH_MAX_KEY_SIZE) {
|
|
memcpy(ctx->key, key, keylen);
|
|
ctx->keylen = keylen;
|
|
} else {
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_cra_init_algs(struct crypto_tfm *tfm,
|
|
const char *algs_hmac_name)
|
|
{
|
|
struct stm32_hash_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
sizeof(struct stm32_hash_request_ctx));
|
|
|
|
ctx->keylen = 0;
|
|
|
|
if (algs_hmac_name)
|
|
ctx->flags |= HASH_FLAGS_HMAC;
|
|
|
|
ctx->enginectx.op.do_one_request = stm32_hash_one_request;
|
|
ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
|
|
ctx->enginectx.op.unprepare_request = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_cra_init(struct crypto_tfm *tfm)
|
|
{
|
|
return stm32_hash_cra_init_algs(tfm, NULL);
|
|
}
|
|
|
|
static int stm32_hash_cra_md5_init(struct crypto_tfm *tfm)
|
|
{
|
|
return stm32_hash_cra_init_algs(tfm, "md5");
|
|
}
|
|
|
|
static int stm32_hash_cra_sha1_init(struct crypto_tfm *tfm)
|
|
{
|
|
return stm32_hash_cra_init_algs(tfm, "sha1");
|
|
}
|
|
|
|
static int stm32_hash_cra_sha224_init(struct crypto_tfm *tfm)
|
|
{
|
|
return stm32_hash_cra_init_algs(tfm, "sha224");
|
|
}
|
|
|
|
static int stm32_hash_cra_sha256_init(struct crypto_tfm *tfm)
|
|
{
|
|
return stm32_hash_cra_init_algs(tfm, "sha256");
|
|
}
|
|
|
|
static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
|
|
{
|
|
struct stm32_hash_dev *hdev = dev_id;
|
|
|
|
if (HASH_FLAGS_CPU & hdev->flags) {
|
|
if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
|
|
hdev->flags &= ~HASH_FLAGS_OUTPUT_READY;
|
|
goto finish;
|
|
}
|
|
} else if (HASH_FLAGS_DMA_READY & hdev->flags) {
|
|
if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) {
|
|
hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE;
|
|
goto finish;
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
finish:
|
|
/* Finish current request */
|
|
stm32_hash_finish_req(hdev->req, 0);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t stm32_hash_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct stm32_hash_dev *hdev = dev_id;
|
|
u32 reg;
|
|
|
|
reg = stm32_hash_read(hdev, HASH_SR);
|
|
if (reg & HASH_SR_OUTPUT_READY) {
|
|
reg &= ~HASH_SR_OUTPUT_READY;
|
|
stm32_hash_write(hdev, HASH_SR, reg);
|
|
hdev->flags |= HASH_FLAGS_OUTPUT_READY;
|
|
/* Disable IT*/
|
|
stm32_hash_write(hdev, HASH_IMR, 0);
|
|
return IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static struct ahash_alg algs_md5_sha1[] = {
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.halg = {
|
|
.digestsize = MD5_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "md5",
|
|
.cra_driver_name = "stm32-md5",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.setkey = stm32_hash_setkey,
|
|
.halg = {
|
|
.digestsize = MD5_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "hmac(md5)",
|
|
.cra_driver_name = "stm32-hmac-md5",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_md5_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.halg = {
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "sha1",
|
|
.cra_driver_name = "stm32-sha1",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.setkey = stm32_hash_setkey,
|
|
.halg = {
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "hmac(sha1)",
|
|
.cra_driver_name = "stm32-hmac-sha1",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_sha1_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
};
|
|
|
|
static struct ahash_alg algs_sha224_sha256[] = {
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.halg = {
|
|
.digestsize = SHA224_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "sha224",
|
|
.cra_driver_name = "stm32-sha224",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.setkey = stm32_hash_setkey,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.halg = {
|
|
.digestsize = SHA224_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "hmac(sha224)",
|
|
.cra_driver_name = "stm32-hmac-sha224",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_sha224_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.halg = {
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "sha256",
|
|
.cra_driver_name = "stm32-sha256",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
{
|
|
.init = stm32_hash_init,
|
|
.update = stm32_hash_update,
|
|
.final = stm32_hash_final,
|
|
.finup = stm32_hash_finup,
|
|
.digest = stm32_hash_digest,
|
|
.export = stm32_hash_export,
|
|
.import = stm32_hash_import,
|
|
.setkey = stm32_hash_setkey,
|
|
.halg = {
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
.base = {
|
|
.cra_name = "hmac(sha256)",
|
|
.cra_driver_name = "stm32-hmac-sha256",
|
|
.cra_priority = 200,
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
.cra_alignmask = 3,
|
|
.cra_init = stm32_hash_cra_sha256_init,
|
|
.cra_module = THIS_MODULE,
|
|
}
|
|
}
|
|
},
|
|
};
|
|
|
|
static int stm32_hash_register_algs(struct stm32_hash_dev *hdev)
|
|
{
|
|
unsigned int i, j;
|
|
int err;
|
|
|
|
for (i = 0; i < hdev->pdata->algs_info_size; i++) {
|
|
for (j = 0; j < hdev->pdata->algs_info[i].size; j++) {
|
|
err = crypto_register_ahash(
|
|
&hdev->pdata->algs_info[i].algs_list[j]);
|
|
if (err)
|
|
goto err_algs;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
err_algs:
|
|
dev_err(hdev->dev, "Algo %d : %d failed\n", i, j);
|
|
for (; i--; ) {
|
|
for (; j--;)
|
|
crypto_unregister_ahash(
|
|
&hdev->pdata->algs_info[i].algs_list[j]);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int stm32_hash_unregister_algs(struct stm32_hash_dev *hdev)
|
|
{
|
|
unsigned int i, j;
|
|
|
|
for (i = 0; i < hdev->pdata->algs_info_size; i++) {
|
|
for (j = 0; j < hdev->pdata->algs_info[i].size; j++)
|
|
crypto_unregister_ahash(
|
|
&hdev->pdata->algs_info[i].algs_list[j]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f4[] = {
|
|
{
|
|
.algs_list = algs_md5_sha1,
|
|
.size = ARRAY_SIZE(algs_md5_sha1),
|
|
},
|
|
};
|
|
|
|
static const struct stm32_hash_pdata stm32_hash_pdata_stm32f4 = {
|
|
.algs_info = stm32_hash_algs_info_stm32f4,
|
|
.algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f4),
|
|
};
|
|
|
|
static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f7[] = {
|
|
{
|
|
.algs_list = algs_md5_sha1,
|
|
.size = ARRAY_SIZE(algs_md5_sha1),
|
|
},
|
|
{
|
|
.algs_list = algs_sha224_sha256,
|
|
.size = ARRAY_SIZE(algs_sha224_sha256),
|
|
},
|
|
};
|
|
|
|
static const struct stm32_hash_pdata stm32_hash_pdata_stm32f7 = {
|
|
.algs_info = stm32_hash_algs_info_stm32f7,
|
|
.algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f7),
|
|
};
|
|
|
|
static const struct of_device_id stm32_hash_of_match[] = {
|
|
{
|
|
.compatible = "st,stm32f456-hash",
|
|
.data = &stm32_hash_pdata_stm32f4,
|
|
},
|
|
{
|
|
.compatible = "st,stm32f756-hash",
|
|
.data = &stm32_hash_pdata_stm32f7,
|
|
},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
|
|
|
|
static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
|
|
struct device *dev)
|
|
{
|
|
hdev->pdata = of_device_get_match_data(dev);
|
|
if (!hdev->pdata) {
|
|
dev_err(dev, "no compatible OF match\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (of_property_read_u32(dev->of_node, "dma-maxburst",
|
|
&hdev->dma_maxburst)) {
|
|
dev_info(dev, "dma-maxburst not specified, using 0\n");
|
|
hdev->dma_maxburst = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_probe(struct platform_device *pdev)
|
|
{
|
|
struct stm32_hash_dev *hdev;
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
int ret, irq;
|
|
|
|
hdev = devm_kzalloc(dev, sizeof(*hdev), GFP_KERNEL);
|
|
if (!hdev)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
hdev->io_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(hdev->io_base))
|
|
return PTR_ERR(hdev->io_base);
|
|
|
|
hdev->phys_base = res->start;
|
|
|
|
ret = stm32_hash_get_of_match(hdev, dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "Cannot get IRQ resource\n");
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, stm32_hash_irq_handler,
|
|
stm32_hash_irq_thread, IRQF_ONESHOT,
|
|
dev_name(dev), hdev);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot grab IRQ\n");
|
|
return ret;
|
|
}
|
|
|
|
hdev->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(hdev->clk)) {
|
|
dev_err(dev, "failed to get clock for hash (%lu)\n",
|
|
PTR_ERR(hdev->clk));
|
|
return PTR_ERR(hdev->clk);
|
|
}
|
|
|
|
ret = clk_prepare_enable(hdev->clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable hash clock (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, HASH_AUTOSUSPEND_DELAY);
|
|
pm_runtime_use_autosuspend(dev);
|
|
|
|
pm_runtime_get_noresume(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
hdev->rst = devm_reset_control_get(&pdev->dev, NULL);
|
|
if (!IS_ERR(hdev->rst)) {
|
|
reset_control_assert(hdev->rst);
|
|
udelay(2);
|
|
reset_control_deassert(hdev->rst);
|
|
}
|
|
|
|
hdev->dev = dev;
|
|
|
|
platform_set_drvdata(pdev, hdev);
|
|
|
|
ret = stm32_hash_dma_init(hdev);
|
|
if (ret)
|
|
dev_dbg(dev, "DMA mode not available\n");
|
|
|
|
spin_lock(&stm32_hash.lock);
|
|
list_add_tail(&hdev->list, &stm32_hash.dev_list);
|
|
spin_unlock(&stm32_hash.lock);
|
|
|
|
/* Initialize crypto engine */
|
|
hdev->engine = crypto_engine_alloc_init(dev, 1);
|
|
if (!hdev->engine) {
|
|
ret = -ENOMEM;
|
|
goto err_engine;
|
|
}
|
|
|
|
ret = crypto_engine_start(hdev->engine);
|
|
if (ret)
|
|
goto err_engine_start;
|
|
|
|
hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR);
|
|
|
|
/* Register algos */
|
|
ret = stm32_hash_register_algs(hdev);
|
|
if (ret)
|
|
goto err_algs;
|
|
|
|
dev_info(dev, "Init HASH done HW ver %x DMA mode %u\n",
|
|
stm32_hash_read(hdev, HASH_VER), hdev->dma_mode);
|
|
|
|
pm_runtime_put_sync(dev);
|
|
|
|
return 0;
|
|
|
|
err_algs:
|
|
err_engine_start:
|
|
crypto_engine_exit(hdev->engine);
|
|
err_engine:
|
|
spin_lock(&stm32_hash.lock);
|
|
list_del(&hdev->list);
|
|
spin_unlock(&stm32_hash.lock);
|
|
|
|
if (hdev->dma_lch)
|
|
dma_release_channel(hdev->dma_lch);
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_put_noidle(dev);
|
|
|
|
clk_disable_unprepare(hdev->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_hash_remove(struct platform_device *pdev)
|
|
{
|
|
static struct stm32_hash_dev *hdev;
|
|
int ret;
|
|
|
|
hdev = platform_get_drvdata(pdev);
|
|
if (!hdev)
|
|
return -ENODEV;
|
|
|
|
ret = pm_runtime_get_sync(hdev->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
stm32_hash_unregister_algs(hdev);
|
|
|
|
crypto_engine_exit(hdev->engine);
|
|
|
|
spin_lock(&stm32_hash.lock);
|
|
list_del(&hdev->list);
|
|
spin_unlock(&stm32_hash.lock);
|
|
|
|
if (hdev->dma_lch)
|
|
dma_release_channel(hdev->dma_lch);
|
|
|
|
pm_runtime_disable(hdev->dev);
|
|
pm_runtime_put_noidle(hdev->dev);
|
|
|
|
clk_disable_unprepare(hdev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int stm32_hash_runtime_suspend(struct device *dev)
|
|
{
|
|
struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(hdev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_hash_runtime_resume(struct device *dev)
|
|
{
|
|
struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(hdev->clk);
|
|
if (ret) {
|
|
dev_err(hdev->dev, "Failed to prepare_enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops stm32_hash_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(stm32_hash_runtime_suspend,
|
|
stm32_hash_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver stm32_hash_driver = {
|
|
.probe = stm32_hash_probe,
|
|
.remove = stm32_hash_remove,
|
|
.driver = {
|
|
.name = "stm32-hash",
|
|
.pm = &stm32_hash_pm_ops,
|
|
.of_match_table = stm32_hash_of_match,
|
|
}
|
|
};
|
|
|
|
module_platform_driver(stm32_hash_driver);
|
|
|
|
MODULE_DESCRIPTION("STM32 SHA1/224/256 & MD5 (HMAC) hw accelerator driver");
|
|
MODULE_AUTHOR("Lionel Debieve <lionel.debieve@st.com>");
|
|
MODULE_LICENSE("GPL v2");
|