mirror of https://gitee.com/openkylin/linux.git
495 lines
14 KiB
C
495 lines
14 KiB
C
/*
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* Copyright (C) 2012 Russell King
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* Rewritten from the dovefb driver, and Armada510 manuals.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include "armada_crtc.h"
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#include "armada_drm.h"
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#include "armada_fb.h"
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#include "armada_gem.h"
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#include "armada_hw.h"
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#include <drm/armada_drm.h>
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#include "armada_ioctlP.h"
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#include "armada_trace.h"
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struct armada_ovl_plane_properties {
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uint32_t colorkey_yr;
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uint32_t colorkey_ug;
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uint32_t colorkey_vb;
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#define K2R(val) (((val) >> 0) & 0xff)
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#define K2G(val) (((val) >> 8) & 0xff)
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#define K2B(val) (((val) >> 16) & 0xff)
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int16_t brightness;
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uint16_t contrast;
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uint16_t saturation;
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uint32_t colorkey_mode;
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uint32_t colorkey_enable;
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};
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struct armada_ovl_plane {
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struct armada_plane base;
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struct armada_ovl_plane_properties prop;
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};
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#define drm_to_armada_ovl_plane(p) \
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container_of(p, struct armada_ovl_plane, base.base)
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static void
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armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
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struct armada_crtc *dcrtc)
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{
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writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
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writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
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writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
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writel_relaxed(prop->brightness << 16 | prop->contrast,
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dcrtc->base + LCD_SPU_CONTRAST);
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/* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
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writel_relaxed(prop->saturation << 16,
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dcrtc->base + LCD_SPU_SATURATION);
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writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
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spin_lock_irq(&dcrtc->irq_lock);
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armada_updatel(prop->colorkey_mode,
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CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
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dcrtc->base + LCD_SPU_DMA_CTRL1);
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if (dcrtc->variant->has_spu_adv_reg)
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armada_updatel(prop->colorkey_enable,
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ADV_GRACOLORKEY | ADV_VIDCOLORKEY,
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dcrtc->base + LCD_SPU_ADV_REG);
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spin_unlock_irq(&dcrtc->irq_lock);
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}
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/* === Plane support === */
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static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
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struct armada_plane_work *work)
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{
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unsigned long flags;
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trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane);
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spin_lock_irqsave(&dcrtc->irq_lock, flags);
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armada_drm_crtc_update_regs(dcrtc, work->regs);
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spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
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}
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static void armada_ovl_plane_update_state(struct drm_plane_state *state,
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struct armada_regs *regs)
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{
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struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(state->plane);
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struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
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const struct drm_format_info *format;
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unsigned int idx = 0;
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bool fb_changed;
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u32 val, ctrl0;
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u16 src_x, src_y;
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ctrl0 = CFG_DMA_FMT(dfb->fmt) | CFG_DMA_MOD(dfb->mod) | CFG_CBSH_ENA;
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if (state->visible)
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ctrl0 |= CFG_DMA_ENA;
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if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
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ctrl0 |= CFG_DMA_HSMOOTH;
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/*
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* Shifting a YUV packed format image by one pixel causes the U/V
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* planes to swap. Compensate for it by also toggling the UV swap.
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*/
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format = dfb->fb.format;
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if (format->num_planes == 1 && state->src.x1 >> 16 & (format->hsub - 1))
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ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
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if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
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/* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
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armada_reg_queue_mod(regs, idx,
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0, CFG_PDWN16x66 | CFG_PDWN32x66,
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LCD_SPU_SRAM_PARA1);
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}
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fb_changed = dplane->base.base.fb != &dfb->fb ||
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dplane->base.state.src_x != state->src.x1 >> 16 ||
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dplane->base.state.src_y != state->src.y1 >> 16;
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dplane->base.state.vsync_update = fb_changed;
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/* FIXME: overlay on an interlaced display */
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if (fb_changed) {
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u32 addrs[3];
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dplane->base.state.src_y = src_y = state->src.y1 >> 16;
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dplane->base.state.src_x = src_x = state->src.x1 >> 16;
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armada_drm_plane_calc_addrs(addrs, &dfb->fb, src_x, src_y);
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armada_reg_queue_set(regs, idx, addrs[0],
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LCD_SPU_DMA_START_ADDR_Y0);
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armada_reg_queue_set(regs, idx, addrs[1],
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LCD_SPU_DMA_START_ADDR_U0);
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armada_reg_queue_set(regs, idx, addrs[2],
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LCD_SPU_DMA_START_ADDR_V0);
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armada_reg_queue_set(regs, idx, addrs[0],
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LCD_SPU_DMA_START_ADDR_Y1);
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armada_reg_queue_set(regs, idx, addrs[1],
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LCD_SPU_DMA_START_ADDR_U1);
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armada_reg_queue_set(regs, idx, addrs[2],
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LCD_SPU_DMA_START_ADDR_V1);
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val = dfb->fb.pitches[0] << 16 | dfb->fb.pitches[0];
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_PITCH_YC);
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val = dfb->fb.pitches[1] << 16 | dfb->fb.pitches[2];
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_PITCH_UV);
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}
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val = armada_rect_hw_fp(&state->src);
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if (dplane->base.state.src_hw != val) {
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dplane->base.state.src_hw = val;
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_HPXL_VLN);
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}
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val = armada_rect_hw(&state->dst);
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if (dplane->base.state.dst_hw != val) {
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dplane->base.state.dst_hw = val;
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DZM_HPXL_VLN);
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}
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val = armada_rect_yx(&state->dst);
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if (dplane->base.state.dst_yx != val) {
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dplane->base.state.dst_yx = val;
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_OVSA_HPXL_VLN);
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}
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if (dplane->base.state.ctrl0 != ctrl0) {
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dplane->base.state.ctrl0 = ctrl0;
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armada_reg_queue_mod(regs, idx, ctrl0,
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CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
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CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
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CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
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CFG_YUV2RGB) | CFG_DMA_ENA,
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LCD_SPU_DMA_CTRL0);
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dplane->base.state.vsync_update = true;
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}
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dplane->base.state.changed = idx != 0;
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armada_reg_queue_end(regs, idx);
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}
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static int
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armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
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uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
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struct drm_modeset_acquire_ctx *ctx)
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{
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struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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struct armada_plane_work *work;
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struct drm_plane_state state = {
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.plane = plane,
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.crtc = crtc,
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.fb = fb,
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.src_x = src_x,
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.src_y = src_y,
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.src_w = src_w,
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.src_h = src_h,
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.crtc_x = crtc_x,
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.crtc_y = crtc_y,
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.crtc_w = crtc_w,
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.crtc_h = crtc_h,
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.rotation = DRM_MODE_ROTATE_0,
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};
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struct drm_crtc_state crtc_state = {
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.crtc = crtc,
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.enable = crtc->enabled,
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.mode = crtc->mode,
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};
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int ret;
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trace_armada_ovl_plane_update(plane, crtc, fb,
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crtc_x, crtc_y, crtc_w, crtc_h,
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src_x, src_y, src_w, src_h);
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ret = drm_atomic_helper_check_plane_state(&state, &crtc_state, 0,
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INT_MAX, true, false);
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if (ret)
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return ret;
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work = &dplane->base.works[dplane->base.next_work];
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if (plane->fb != fb) {
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/*
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* Take a reference on the new framebuffer - we want to
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* hold on to it while the hardware is displaying it.
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*/
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drm_framebuffer_reference(fb);
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work->old_fb = plane->fb;
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} else {
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work->old_fb = NULL;
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}
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armada_ovl_plane_update_state(&state, work->regs);
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if (!dplane->base.state.changed)
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return 0;
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/* Wait for pending work to complete */
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if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
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armada_drm_plane_work_cancel(dcrtc, &dplane->base);
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/* Just updating the position/size? */
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if (!dplane->base.state.vsync_update) {
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armada_ovl_plane_work(dcrtc, work);
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return 0;
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}
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if (!dcrtc->plane) {
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dcrtc->plane = plane;
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armada_ovl_update_attr(&dplane->prop, dcrtc);
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}
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/* Queue it for update on the next interrupt if we are enabled */
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ret = armada_drm_plane_work_queue(dcrtc, work);
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if (ret)
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DRM_ERROR("failed to queue plane work: %d\n", ret);
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dplane->base.next_work = !dplane->base.next_work;
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return 0;
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}
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static void armada_ovl_plane_destroy(struct drm_plane *plane)
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{
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struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
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drm_plane_cleanup(plane);
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kfree(dplane);
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}
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static int armada_ovl_plane_set_property(struct drm_plane *plane,
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struct drm_property *property, uint64_t val)
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{
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struct armada_private *priv = plane->dev->dev_private;
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struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
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bool update_attr = false;
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if (property == priv->colorkey_prop) {
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#define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
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dplane->prop.colorkey_yr = CCC(K2R(val));
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dplane->prop.colorkey_ug = CCC(K2G(val));
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dplane->prop.colorkey_vb = CCC(K2B(val));
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#undef CCC
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update_attr = true;
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} else if (property == priv->colorkey_min_prop) {
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dplane->prop.colorkey_yr &= ~0x00ff0000;
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dplane->prop.colorkey_yr |= K2R(val) << 16;
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dplane->prop.colorkey_ug &= ~0x00ff0000;
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dplane->prop.colorkey_ug |= K2G(val) << 16;
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dplane->prop.colorkey_vb &= ~0x00ff0000;
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dplane->prop.colorkey_vb |= K2B(val) << 16;
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update_attr = true;
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} else if (property == priv->colorkey_max_prop) {
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dplane->prop.colorkey_yr &= ~0xff000000;
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dplane->prop.colorkey_yr |= K2R(val) << 24;
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dplane->prop.colorkey_ug &= ~0xff000000;
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dplane->prop.colorkey_ug |= K2G(val) << 24;
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dplane->prop.colorkey_vb &= ~0xff000000;
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dplane->prop.colorkey_vb |= K2B(val) << 24;
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update_attr = true;
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} else if (property == priv->colorkey_val_prop) {
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dplane->prop.colorkey_yr &= ~0x0000ff00;
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dplane->prop.colorkey_yr |= K2R(val) << 8;
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dplane->prop.colorkey_ug &= ~0x0000ff00;
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dplane->prop.colorkey_ug |= K2G(val) << 8;
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dplane->prop.colorkey_vb &= ~0x0000ff00;
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dplane->prop.colorkey_vb |= K2B(val) << 8;
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update_attr = true;
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} else if (property == priv->colorkey_alpha_prop) {
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dplane->prop.colorkey_yr &= ~0x000000ff;
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dplane->prop.colorkey_yr |= K2R(val);
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dplane->prop.colorkey_ug &= ~0x000000ff;
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dplane->prop.colorkey_ug |= K2G(val);
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dplane->prop.colorkey_vb &= ~0x000000ff;
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dplane->prop.colorkey_vb |= K2B(val);
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update_attr = true;
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} else if (property == priv->colorkey_mode_prop) {
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if (val == CKMODE_DISABLE) {
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dplane->prop.colorkey_mode =
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CFG_CKMODE(CKMODE_DISABLE) |
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CFG_ALPHAM_CFG | CFG_ALPHA(255);
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dplane->prop.colorkey_enable = 0;
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} else {
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dplane->prop.colorkey_mode =
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CFG_CKMODE(val) |
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CFG_ALPHAM_GRA | CFG_ALPHA(0);
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dplane->prop.colorkey_enable = ADV_GRACOLORKEY;
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}
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update_attr = true;
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} else if (property == priv->brightness_prop) {
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dplane->prop.brightness = val - 256;
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update_attr = true;
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} else if (property == priv->contrast_prop) {
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dplane->prop.contrast = val;
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update_attr = true;
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} else if (property == priv->saturation_prop) {
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dplane->prop.saturation = val;
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update_attr = true;
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}
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if (update_attr && dplane->base.base.crtc)
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armada_ovl_update_attr(&dplane->prop,
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drm_to_armada_crtc(dplane->base.base.crtc));
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return 0;
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}
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static const struct drm_plane_funcs armada_ovl_plane_funcs = {
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.update_plane = armada_ovl_plane_update,
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.disable_plane = armada_drm_plane_disable,
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.destroy = armada_ovl_plane_destroy,
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.set_property = armada_ovl_plane_set_property,
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};
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static const uint32_t armada_ovl_formats[] = {
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DRM_FORMAT_UYVY,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_YUV420,
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DRM_FORMAT_YVU420,
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DRM_FORMAT_YUV422,
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DRM_FORMAT_YVU422,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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};
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static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
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{ CKMODE_DISABLE, "disabled" },
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{ CKMODE_Y, "Y component" },
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{ CKMODE_U, "U component" },
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{ CKMODE_V, "V component" },
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{ CKMODE_RGB, "RGB" },
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{ CKMODE_R, "R component" },
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{ CKMODE_G, "G component" },
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{ CKMODE_B, "B component" },
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};
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static int armada_overlay_create_properties(struct drm_device *dev)
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{
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struct armada_private *priv = dev->dev_private;
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if (priv->colorkey_prop)
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return 0;
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priv->colorkey_prop = drm_property_create_range(dev, 0,
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"colorkey", 0, 0xffffff);
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priv->colorkey_min_prop = drm_property_create_range(dev, 0,
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"colorkey_min", 0, 0xffffff);
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priv->colorkey_max_prop = drm_property_create_range(dev, 0,
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"colorkey_max", 0, 0xffffff);
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priv->colorkey_val_prop = drm_property_create_range(dev, 0,
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"colorkey_val", 0, 0xffffff);
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priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
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"colorkey_alpha", 0, 0xffffff);
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priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
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"colorkey_mode",
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armada_drm_colorkey_enum_list,
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ARRAY_SIZE(armada_drm_colorkey_enum_list));
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priv->brightness_prop = drm_property_create_range(dev, 0,
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"brightness", 0, 256 + 255);
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priv->contrast_prop = drm_property_create_range(dev, 0,
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"contrast", 0, 0x7fff);
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priv->saturation_prop = drm_property_create_range(dev, 0,
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"saturation", 0, 0x7fff);
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if (!priv->colorkey_prop)
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return -ENOMEM;
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return 0;
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}
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int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
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{
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struct armada_private *priv = dev->dev_private;
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struct drm_mode_object *mobj;
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struct armada_ovl_plane *dplane;
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int ret;
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ret = armada_overlay_create_properties(dev);
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if (ret)
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return ret;
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dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
|
|
if (!dplane)
|
|
return -ENOMEM;
|
|
|
|
ret = armada_drm_plane_init(&dplane->base);
|
|
if (ret) {
|
|
kfree(dplane);
|
|
return ret;
|
|
}
|
|
|
|
dplane->base.works[0].fn = armada_ovl_plane_work;
|
|
dplane->base.works[1].fn = armada_ovl_plane_work;
|
|
|
|
ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
|
|
&armada_ovl_plane_funcs,
|
|
armada_ovl_formats,
|
|
ARRAY_SIZE(armada_ovl_formats),
|
|
NULL,
|
|
DRM_PLANE_TYPE_OVERLAY, NULL);
|
|
if (ret) {
|
|
kfree(dplane);
|
|
return ret;
|
|
}
|
|
|
|
dplane->prop.colorkey_yr = 0xfefefe00;
|
|
dplane->prop.colorkey_ug = 0x01010100;
|
|
dplane->prop.colorkey_vb = 0x01010100;
|
|
dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
|
|
CFG_ALPHAM_GRA | CFG_ALPHA(0);
|
|
dplane->prop.colorkey_enable = ADV_GRACOLORKEY;
|
|
dplane->prop.brightness = 0;
|
|
dplane->prop.contrast = 0x4000;
|
|
dplane->prop.saturation = 0x4000;
|
|
|
|
mobj = &dplane->base.base.base;
|
|
drm_object_attach_property(mobj, priv->colorkey_prop,
|
|
0x0101fe);
|
|
drm_object_attach_property(mobj, priv->colorkey_min_prop,
|
|
0x0101fe);
|
|
drm_object_attach_property(mobj, priv->colorkey_max_prop,
|
|
0x0101fe);
|
|
drm_object_attach_property(mobj, priv->colorkey_val_prop,
|
|
0x0101fe);
|
|
drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
|
|
0x000000);
|
|
drm_object_attach_property(mobj, priv->colorkey_mode_prop,
|
|
CKMODE_RGB);
|
|
drm_object_attach_property(mobj, priv->brightness_prop, 256);
|
|
drm_object_attach_property(mobj, priv->contrast_prop,
|
|
dplane->prop.contrast);
|
|
drm_object_attach_property(mobj, priv->saturation_prop,
|
|
dplane->prop.saturation);
|
|
|
|
return 0;
|
|
}
|