mirror of https://gitee.com/openkylin/linux.git
828 lines
24 KiB
C
828 lines
24 KiB
C
/*
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* Copyright (C) 2009 Francisco Jerez.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm_crtc_helper.h"
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#include "nouveau_drv.h"
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#include "nouveau_encoder.h"
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#include "nouveau_connector.h"
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#include "nouveau_crtc.h"
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#include "nouveau_hw.h"
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#include "nv17_tv.h"
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static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
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uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
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uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
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fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
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uint32_t sample = 0;
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int head;
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#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
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testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
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if (dev_priv->vbios.tvdactestval)
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testval = dev_priv->vbios.tvdactestval;
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dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
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head = (dacclk & 0x100) >> 8;
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/* Save the previous state. */
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gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
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gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
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fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
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fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
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fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
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fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
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test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
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ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
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ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
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ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
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/* Prepare the DAC for load detection. */
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gpio->set(dev, DCB_GPIO_TVDAC1, true);
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gpio->set(dev, DCB_GPIO_TVDAC0, true);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
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NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
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NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
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NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
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NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
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NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
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(dacclk & ~0xff) | 0x22);
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msleep(1);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
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(dacclk & ~0xff) | 0x21);
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NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
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NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
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/* Sample pin 0x4 (usually S-video luma). */
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NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
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msleep(20);
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sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
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& 0x4 << 28;
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/* Sample the remaining pins. */
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NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
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msleep(20);
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sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
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& 0xa << 28;
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/* Restore the previous state. */
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NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
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NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
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NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
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gpio->set(dev, DCB_GPIO_TVDAC1, gpio1);
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gpio->set(dev, DCB_GPIO_TVDAC0, gpio0);
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return sample;
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}
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static bool
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get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
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{
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/* Zotac FX5200 */
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if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
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nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
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*pin_mask = 0xc;
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return false;
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}
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/* MSI nForce2 IGP */
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if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
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*pin_mask = 0xc;
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return false;
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}
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return true;
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}
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static enum drm_connector_status
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nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_mode_config *conf = &dev->mode_config;
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struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
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struct dcb_entry *dcb = tv_enc->base.dcb;
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bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
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if (nv04_dac_in_use(encoder))
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return connector_status_disconnected;
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if (reliable) {
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if (dev_priv->chipset == 0x42 ||
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dev_priv->chipset == 0x43)
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tv_enc->pin_mask =
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nv42_tv_sample_load(encoder) >> 28 & 0xe;
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else
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tv_enc->pin_mask =
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nv17_dac_sample_load(encoder) >> 28 & 0xe;
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}
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switch (tv_enc->pin_mask) {
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case 0x2:
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case 0x4:
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tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
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break;
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case 0xc:
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tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
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break;
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case 0xe:
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if (dcb->tvconf.has_component_output)
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tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
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else
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tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
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break;
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default:
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tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
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break;
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}
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drm_connector_property_set_value(connector,
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conf->tv_subconnector_property,
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tv_enc->subconnector);
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if (!reliable) {
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return connector_status_unknown;
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} else if (tv_enc->subconnector) {
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NV_INFO(dev, "Load detected on output %c\n",
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'@' + ffs(dcb->or));
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return connector_status_connected;
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} else {
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return connector_status_disconnected;
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}
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}
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static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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struct drm_display_mode *mode, *tv_mode;
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int n = 0;
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for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
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mode = drm_mode_duplicate(encoder->dev, tv_mode);
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mode->clock = tv_norm->tv_enc_mode.vrefresh *
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mode->htotal / 1000 *
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mode->vtotal / 1000;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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mode->clock *= 2;
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if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
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mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
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mode->type |= DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, mode);
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n++;
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}
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return n;
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}
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static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
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struct drm_display_mode *mode;
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const struct {
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int hdisplay;
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int vdisplay;
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} modes[] = {
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{ 640, 400 },
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{ 640, 480 },
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{ 720, 480 },
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{ 720, 576 },
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{ 800, 600 },
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{ 1024, 768 },
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{ 1280, 720 },
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{ 1280, 1024 },
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{ 1920, 1080 }
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};
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int i, n = 0;
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for (i = 0; i < ARRAY_SIZE(modes); i++) {
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if (modes[i].hdisplay > output_mode->hdisplay ||
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modes[i].vdisplay > output_mode->vdisplay)
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continue;
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if (modes[i].hdisplay == output_mode->hdisplay &&
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modes[i].vdisplay == output_mode->vdisplay) {
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mode = drm_mode_duplicate(encoder->dev, output_mode);
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mode->type |= DRM_MODE_TYPE_PREFERRED;
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} else {
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mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
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modes[i].vdisplay, 60, false,
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(output_mode->flags &
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DRM_MODE_FLAG_INTERLACE), false);
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}
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/* CVT modes are sometimes unsuitable... */
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if (output_mode->hdisplay <= 720
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|| output_mode->hdisplay >= 1920) {
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mode->htotal = output_mode->htotal;
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mode->hsync_start = (mode->hdisplay + (mode->htotal
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- mode->hdisplay) * 9 / 10) & ~7;
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mode->hsync_end = mode->hsync_start + 8;
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}
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if (output_mode->vdisplay >= 1024) {
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mode->vtotal = output_mode->vtotal;
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mode->vsync_start = output_mode->vsync_start;
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mode->vsync_end = output_mode->vsync_end;
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}
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mode->type |= DRM_MODE_TYPE_DRIVER;
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drm_mode_probed_add(connector, mode);
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n++;
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}
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return n;
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}
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static int nv17_tv_get_modes(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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if (tv_norm->kind == CTV_ENC_MODE)
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return nv17_tv_get_hd_modes(encoder, connector);
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else
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return nv17_tv_get_ld_modes(encoder, connector);
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}
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static int nv17_tv_mode_valid(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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if (tv_norm->kind == CTV_ENC_MODE) {
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struct drm_display_mode *output_mode =
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&tv_norm->ctv_enc_mode.mode;
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if (mode->clock > 400000)
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return MODE_CLOCK_HIGH;
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if (mode->hdisplay > output_mode->hdisplay ||
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mode->vdisplay > output_mode->vdisplay)
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return MODE_BAD;
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if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
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(output_mode->flags & DRM_MODE_FLAG_INTERLACE))
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return MODE_NO_INTERLACE;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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return MODE_NO_DBLESCAN;
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} else {
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const int vsync_tolerance = 600;
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if (mode->clock > 70000)
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return MODE_CLOCK_HIGH;
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if (abs(drm_mode_vrefresh(mode) * 1000 -
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tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
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return MODE_VSYNC;
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/* The encoder takes care of the actual interlacing */
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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return MODE_NO_INTERLACE;
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}
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return MODE_OK;
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}
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static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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if (nv04_dac_in_use(encoder))
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return false;
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if (tv_norm->kind == CTV_ENC_MODE)
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adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
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else
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adjusted_mode->clock = 90000;
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return true;
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}
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static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
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struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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if (nouveau_encoder(encoder)->last_dpms == mode)
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return;
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nouveau_encoder(encoder)->last_dpms = mode;
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NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
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mode, nouveau_encoder(encoder)->dcb->index);
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regs->ptv_200 &= ~1;
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if (tv_norm->kind == CTV_ENC_MODE) {
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nv04_dfp_update_fp_control(encoder, mode);
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} else {
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nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
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if (mode == DRM_MODE_DPMS_ON)
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regs->ptv_200 |= 1;
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}
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nv_load_ptv(dev, regs, 200);
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gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
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gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
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nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
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}
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static void nv17_tv_prepare(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_encoder_helper_funcs *helper = encoder->helper_private;
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struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
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int head = nouveau_crtc(encoder->crtc)->index;
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uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
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NV_CIO_CRE_LCD__INDEX];
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uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
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nv04_dac_output_offset(encoder);
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uint32_t dacclk;
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helper->dpms(encoder, DRM_MODE_DPMS_OFF);
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nv04_dfp_disable(dev, head);
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/* Unbind any FP encoders from this head if we need the FP
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* stuff enabled. */
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if (tv_norm->kind == CTV_ENC_MODE) {
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struct drm_encoder *enc;
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list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
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struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
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if ((dcb->type == OUTPUT_TMDS ||
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dcb->type == OUTPUT_LVDS) &&
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!enc->crtc &&
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nv04_dfp_get_bound_head(dev, dcb) == head) {
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nv04_dfp_bind_head(dev, dcb, head ^ 1,
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dev_priv->vbios.fp.dual_link);
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}
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}
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}
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if (tv_norm->kind == CTV_ENC_MODE)
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*cr_lcd = 0x1 | (head ? 0x0 : 0x8);
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else
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*cr_lcd = 0;
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/* Set the DACCLK register */
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dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
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if (dev_priv->card_type == NV_40)
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dacclk |= 0x1a << 16;
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if (tv_norm->kind == CTV_ENC_MODE) {
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dacclk |= 0x20;
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if (head)
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dacclk |= 0x100;
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else
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dacclk &= ~0x100;
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} else {
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dacclk |= 0x10;
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}
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NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
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}
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static void nv17_tv_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *drm_mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int head = nouveau_crtc(encoder->crtc)->index;
|
|
struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
|
|
struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
|
|
struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
|
|
int i;
|
|
|
|
regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
|
|
regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
|
|
regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
|
|
regs->tv_setup = 1;
|
|
regs->ramdac_8c0 = 0x0;
|
|
|
|
if (tv_norm->kind == TV_ENC_MODE) {
|
|
tv_regs->ptv_200 = 0x13111100;
|
|
if (head)
|
|
tv_regs->ptv_200 |= 0x10;
|
|
|
|
tv_regs->ptv_20c = 0x808010;
|
|
tv_regs->ptv_304 = 0x2d00000;
|
|
tv_regs->ptv_600 = 0x0;
|
|
tv_regs->ptv_60c = 0x0;
|
|
tv_regs->ptv_610 = 0x1e00000;
|
|
|
|
if (tv_norm->tv_enc_mode.vdisplay == 576) {
|
|
tv_regs->ptv_508 = 0x1200000;
|
|
tv_regs->ptv_614 = 0x33;
|
|
|
|
} else if (tv_norm->tv_enc_mode.vdisplay == 480) {
|
|
tv_regs->ptv_508 = 0xf00000;
|
|
tv_regs->ptv_614 = 0x13;
|
|
}
|
|
|
|
if (dev_priv->card_type >= NV_30) {
|
|
tv_regs->ptv_500 = 0xe8e0;
|
|
tv_regs->ptv_504 = 0x1710;
|
|
tv_regs->ptv_604 = 0x0;
|
|
tv_regs->ptv_608 = 0x0;
|
|
} else {
|
|
if (tv_norm->tv_enc_mode.vdisplay == 576) {
|
|
tv_regs->ptv_604 = 0x20;
|
|
tv_regs->ptv_608 = 0x10;
|
|
tv_regs->ptv_500 = 0x19710;
|
|
tv_regs->ptv_504 = 0x68f0;
|
|
|
|
} else if (tv_norm->tv_enc_mode.vdisplay == 480) {
|
|
tv_regs->ptv_604 = 0x10;
|
|
tv_regs->ptv_608 = 0x20;
|
|
tv_regs->ptv_500 = 0x4b90;
|
|
tv_regs->ptv_504 = 0x1b480;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 0x40; i++)
|
|
tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
|
|
|
|
} else {
|
|
struct drm_display_mode *output_mode =
|
|
&tv_norm->ctv_enc_mode.mode;
|
|
|
|
/* The registers in PRAMDAC+0xc00 control some timings and CSC
|
|
* parameters for the CTV encoder (It's only used for "HD" TV
|
|
* modes, I don't think I have enough working to guess what
|
|
* they exactly mean...), it's probably connected at the
|
|
* output of the FP encoder, but it also needs the analog
|
|
* encoder in its OR enabled and routed to the head it's
|
|
* using. It's enabled with the DACCLK register, bits [5:4].
|
|
*/
|
|
for (i = 0; i < 38; i++)
|
|
regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
|
|
|
|
regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
|
|
regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
|
|
regs->fp_horiz_regs[FP_SYNC_START] =
|
|
output_mode->hsync_start - 1;
|
|
regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
|
|
regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
|
|
max((output_mode->hdisplay-600)/40 - 1, 1);
|
|
|
|
regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
|
|
regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
|
|
regs->fp_vert_regs[FP_SYNC_START] =
|
|
output_mode->vsync_start - 1;
|
|
regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
|
|
regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
|
|
|
|
regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
|
|
NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
|
|
NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
|
|
|
|
if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
|
|
if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
|
|
|
|
regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
|
|
NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
|
|
NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
|
|
NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
|
|
NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
|
|
NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
|
|
NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
|
|
|
|
regs->fp_debug_2 = 0;
|
|
|
|
regs->fp_margin_color = 0x801080;
|
|
|
|
}
|
|
}
|
|
|
|
static void nv17_tv_commit(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
struct drm_encoder_helper_funcs *helper = encoder->helper_private;
|
|
|
|
if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
|
|
nv17_tv_update_rescaler(encoder);
|
|
nv17_tv_update_properties(encoder);
|
|
} else {
|
|
nv17_ctv_update_rescaler(encoder);
|
|
}
|
|
|
|
nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
|
|
|
|
/* This could use refinement for flatpanels, but it should work */
|
|
if (dev_priv->chipset < 0x44)
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
|
|
nv04_dac_output_offset(encoder),
|
|
0xf0000000);
|
|
else
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
|
|
nv04_dac_output_offset(encoder),
|
|
0x00100000);
|
|
|
|
helper->dpms(encoder, DRM_MODE_DPMS_ON);
|
|
|
|
NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
|
|
drm_get_connector_name(
|
|
&nouveau_encoder_connector_get(nv_encoder)->base),
|
|
nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
|
|
}
|
|
|
|
static void nv17_tv_save(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
|
|
|
|
nouveau_encoder(encoder)->restore.output =
|
|
NVReadRAMDAC(dev, 0,
|
|
NV_PRAMDAC_DACCLK +
|
|
nv04_dac_output_offset(encoder));
|
|
|
|
nv17_tv_state_save(dev, &tv_enc->saved_state);
|
|
|
|
tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
|
|
}
|
|
|
|
static void nv17_tv_restore(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
|
|
nv04_dac_output_offset(encoder),
|
|
nouveau_encoder(encoder)->restore.output);
|
|
|
|
nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
|
|
|
|
nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
|
|
}
|
|
|
|
static int nv17_tv_create_resources(struct drm_encoder *encoder,
|
|
struct drm_connector *connector)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_mode_config *conf = &dev->mode_config;
|
|
struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
|
|
struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
|
|
int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
|
|
NUM_LD_TV_NORMS;
|
|
int i;
|
|
|
|
if (nouveau_tv_norm) {
|
|
for (i = 0; i < num_tv_norms; i++) {
|
|
if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
|
|
tv_enc->tv_norm = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i == num_tv_norms)
|
|
NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
|
|
nouveau_tv_norm);
|
|
}
|
|
|
|
drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
|
|
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_select_subconnector_property,
|
|
tv_enc->select_subconnector);
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_subconnector_property,
|
|
tv_enc->subconnector);
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_mode_property,
|
|
tv_enc->tv_norm);
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_flicker_reduction_property,
|
|
tv_enc->flicker);
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_saturation_property,
|
|
tv_enc->saturation);
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_hue_property,
|
|
tv_enc->hue);
|
|
drm_connector_attach_property(connector,
|
|
conf->tv_overscan_property,
|
|
tv_enc->overscan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nv17_tv_set_property(struct drm_encoder *encoder,
|
|
struct drm_connector *connector,
|
|
struct drm_property *property,
|
|
uint64_t val)
|
|
{
|
|
struct drm_mode_config *conf = &encoder->dev->mode_config;
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
|
|
struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
|
|
bool modes_changed = false;
|
|
|
|
if (property == conf->tv_overscan_property) {
|
|
tv_enc->overscan = val;
|
|
if (encoder->crtc) {
|
|
if (tv_norm->kind == CTV_ENC_MODE)
|
|
nv17_ctv_update_rescaler(encoder);
|
|
else
|
|
nv17_tv_update_rescaler(encoder);
|
|
}
|
|
|
|
} else if (property == conf->tv_saturation_property) {
|
|
if (tv_norm->kind != TV_ENC_MODE)
|
|
return -EINVAL;
|
|
|
|
tv_enc->saturation = val;
|
|
nv17_tv_update_properties(encoder);
|
|
|
|
} else if (property == conf->tv_hue_property) {
|
|
if (tv_norm->kind != TV_ENC_MODE)
|
|
return -EINVAL;
|
|
|
|
tv_enc->hue = val;
|
|
nv17_tv_update_properties(encoder);
|
|
|
|
} else if (property == conf->tv_flicker_reduction_property) {
|
|
if (tv_norm->kind != TV_ENC_MODE)
|
|
return -EINVAL;
|
|
|
|
tv_enc->flicker = val;
|
|
if (encoder->crtc)
|
|
nv17_tv_update_rescaler(encoder);
|
|
|
|
} else if (property == conf->tv_mode_property) {
|
|
if (connector->dpms != DRM_MODE_DPMS_OFF)
|
|
return -EINVAL;
|
|
|
|
tv_enc->tv_norm = val;
|
|
|
|
modes_changed = true;
|
|
|
|
} else if (property == conf->tv_select_subconnector_property) {
|
|
if (tv_norm->kind != TV_ENC_MODE)
|
|
return -EINVAL;
|
|
|
|
tv_enc->select_subconnector = val;
|
|
nv17_tv_update_properties(encoder);
|
|
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (modes_changed) {
|
|
drm_helper_probe_single_connector_modes(connector, 0, 0);
|
|
|
|
/* Disable the crtc to ensure a full modeset is
|
|
* performed whenever it's turned on again. */
|
|
if (crtc) {
|
|
struct drm_mode_set modeset = {
|
|
.crtc = crtc,
|
|
};
|
|
|
|
crtc->funcs->set_config(&modeset);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nv17_tv_destroy(struct drm_encoder *encoder)
|
|
{
|
|
struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
|
|
|
|
NV_DEBUG_KMS(encoder->dev, "\n");
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(tv_enc);
|
|
}
|
|
|
|
static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
|
|
.dpms = nv17_tv_dpms,
|
|
.save = nv17_tv_save,
|
|
.restore = nv17_tv_restore,
|
|
.mode_fixup = nv17_tv_mode_fixup,
|
|
.prepare = nv17_tv_prepare,
|
|
.commit = nv17_tv_commit,
|
|
.mode_set = nv17_tv_mode_set,
|
|
.detect = nv17_tv_detect,
|
|
};
|
|
|
|
static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
|
|
.get_modes = nv17_tv_get_modes,
|
|
.mode_valid = nv17_tv_mode_valid,
|
|
.create_resources = nv17_tv_create_resources,
|
|
.set_property = nv17_tv_set_property,
|
|
};
|
|
|
|
static struct drm_encoder_funcs nv17_tv_funcs = {
|
|
.destroy = nv17_tv_destroy,
|
|
};
|
|
|
|
int
|
|
nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
|
|
{
|
|
struct drm_device *dev = connector->dev;
|
|
struct drm_encoder *encoder;
|
|
struct nv17_tv_encoder *tv_enc = NULL;
|
|
|
|
tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
|
|
if (!tv_enc)
|
|
return -ENOMEM;
|
|
|
|
tv_enc->overscan = 50;
|
|
tv_enc->flicker = 50;
|
|
tv_enc->saturation = 50;
|
|
tv_enc->hue = 0;
|
|
tv_enc->tv_norm = TV_NORM_PAL;
|
|
tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
|
|
tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
|
|
tv_enc->pin_mask = 0;
|
|
|
|
encoder = to_drm_encoder(&tv_enc->base);
|
|
|
|
tv_enc->base.dcb = entry;
|
|
tv_enc->base.or = ffs(entry->or) - 1;
|
|
|
|
drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
|
|
drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
|
|
to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
|
|
|
|
encoder->possible_crtcs = entry->heads;
|
|
encoder->possible_clones = 0;
|
|
|
|
nv17_tv_create_resources(encoder, connector);
|
|
drm_mode_connector_attach_encoder(connector, encoder);
|
|
return 0;
|
|
}
|