mirror of https://gitee.com/openkylin/linux.git
755 lines
17 KiB
C
755 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Tegra20 External Memory Controller driver
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*
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* Author: Dmitry Osipenko <digetx@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/completion.h>
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#include <linux/debugfs.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/sort.h>
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#include <linux/types.h>
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#include <soc/tegra/fuse.h>
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#define EMC_INTSTATUS 0x000
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#define EMC_INTMASK 0x004
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#define EMC_DBG 0x008
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#define EMC_TIMING_CONTROL 0x028
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#define EMC_RC 0x02c
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#define EMC_RFC 0x030
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#define EMC_RAS 0x034
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#define EMC_RP 0x038
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#define EMC_R2W 0x03c
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#define EMC_W2R 0x040
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#define EMC_R2P 0x044
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#define EMC_W2P 0x048
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#define EMC_RD_RCD 0x04c
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#define EMC_WR_RCD 0x050
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#define EMC_RRD 0x054
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#define EMC_REXT 0x058
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#define EMC_WDV 0x05c
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#define EMC_QUSE 0x060
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#define EMC_QRST 0x064
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#define EMC_QSAFE 0x068
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#define EMC_RDV 0x06c
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#define EMC_REFRESH 0x070
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#define EMC_BURST_REFRESH_NUM 0x074
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#define EMC_PDEX2WR 0x078
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#define EMC_PDEX2RD 0x07c
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#define EMC_PCHG2PDEN 0x080
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#define EMC_ACT2PDEN 0x084
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#define EMC_AR2PDEN 0x088
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#define EMC_RW2PDEN 0x08c
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#define EMC_TXSR 0x090
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#define EMC_TCKE 0x094
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#define EMC_TFAW 0x098
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#define EMC_TRPAB 0x09c
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#define EMC_TCLKSTABLE 0x0a0
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#define EMC_TCLKSTOP 0x0a4
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#define EMC_TREFBW 0x0a8
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#define EMC_QUSE_EXTRA 0x0ac
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#define EMC_ODT_WRITE 0x0b0
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#define EMC_ODT_READ 0x0b4
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#define EMC_FBIO_CFG5 0x104
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#define EMC_FBIO_CFG6 0x114
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#define EMC_AUTO_CAL_INTERVAL 0x2a8
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#define EMC_CFG_2 0x2b8
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#define EMC_CFG_DIG_DLL 0x2bc
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#define EMC_DLL_XFORM_DQS 0x2c0
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#define EMC_DLL_XFORM_QUSE 0x2c4
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#define EMC_ZCAL_REF_CNT 0x2e0
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#define EMC_ZCAL_WAIT_CNT 0x2e4
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#define EMC_CFG_CLKTRIM_0 0x2d0
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#define EMC_CFG_CLKTRIM_1 0x2d4
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#define EMC_CFG_CLKTRIM_2 0x2d8
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#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
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#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
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#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
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#define EMC_TIMING_UPDATE BIT(0)
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#define EMC_REFRESH_OVERFLOW_INT BIT(3)
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#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
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#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
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#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
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#define EMC_DBG_FORCE_UPDATE BIT(2)
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#define EMC_DBG_READ_DQM_CTRL BIT(9)
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#define EMC_DBG_CFG_PRIORITY BIT(24)
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static const u16 emc_timing_registers[] = {
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EMC_RC,
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EMC_RFC,
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EMC_RAS,
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EMC_RP,
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EMC_R2W,
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EMC_W2R,
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EMC_R2P,
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EMC_W2P,
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EMC_RD_RCD,
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EMC_WR_RCD,
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EMC_RRD,
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EMC_REXT,
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EMC_WDV,
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EMC_QUSE,
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EMC_QRST,
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EMC_QSAFE,
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EMC_RDV,
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EMC_REFRESH,
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EMC_BURST_REFRESH_NUM,
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EMC_PDEX2WR,
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EMC_PDEX2RD,
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EMC_PCHG2PDEN,
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EMC_ACT2PDEN,
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EMC_AR2PDEN,
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EMC_RW2PDEN,
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EMC_TXSR,
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EMC_TCKE,
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EMC_TFAW,
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EMC_TRPAB,
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EMC_TCLKSTABLE,
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EMC_TCLKSTOP,
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EMC_TREFBW,
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EMC_QUSE_EXTRA,
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EMC_FBIO_CFG6,
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EMC_ODT_WRITE,
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EMC_ODT_READ,
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EMC_FBIO_CFG5,
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EMC_CFG_DIG_DLL,
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EMC_DLL_XFORM_DQS,
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EMC_DLL_XFORM_QUSE,
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EMC_ZCAL_REF_CNT,
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EMC_ZCAL_WAIT_CNT,
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EMC_AUTO_CAL_INTERVAL,
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EMC_CFG_CLKTRIM_0,
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EMC_CFG_CLKTRIM_1,
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EMC_CFG_CLKTRIM_2,
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};
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struct emc_timing {
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unsigned long rate;
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u32 data[ARRAY_SIZE(emc_timing_registers)];
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};
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struct tegra_emc {
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struct device *dev;
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struct completion clk_handshake_complete;
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struct notifier_block clk_nb;
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struct clk *clk;
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void __iomem *regs;
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struct emc_timing *timings;
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unsigned int num_timings;
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struct {
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struct dentry *root;
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unsigned long min_rate;
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unsigned long max_rate;
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} debugfs;
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};
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static irqreturn_t tegra_emc_isr(int irq, void *data)
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{
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struct tegra_emc *emc = data;
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u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
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u32 status;
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status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
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if (!status)
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return IRQ_NONE;
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/* notify about EMC-CAR handshake completion */
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if (status & EMC_CLKCHANGE_COMPLETE_INT)
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complete(&emc->clk_handshake_complete);
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/* notify about HW problem */
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if (status & EMC_REFRESH_OVERFLOW_INT)
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dev_err_ratelimited(emc->dev,
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"refresh request overflow timeout\n");
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/* clear interrupts */
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writel_relaxed(status, emc->regs + EMC_INTSTATUS);
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return IRQ_HANDLED;
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}
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static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
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unsigned long rate)
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{
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struct emc_timing *timing = NULL;
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unsigned int i;
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for (i = 0; i < emc->num_timings; i++) {
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if (emc->timings[i].rate >= rate) {
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timing = &emc->timings[i];
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break;
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}
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}
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if (!timing) {
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dev_err(emc->dev, "no timing for rate %lu\n", rate);
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return NULL;
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}
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return timing;
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}
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static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
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{
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struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
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unsigned int i;
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if (!timing)
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return -EINVAL;
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dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
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__func__, timing->rate, rate);
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/* program shadow registers */
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for (i = 0; i < ARRAY_SIZE(timing->data); i++)
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writel_relaxed(timing->data[i],
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emc->regs + emc_timing_registers[i]);
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/* wait until programming has settled */
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readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
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reinit_completion(&emc->clk_handshake_complete);
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return 0;
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}
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static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
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{
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unsigned long timeout;
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dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
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if (flush) {
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/* manually initiate memory timing update */
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writel_relaxed(EMC_TIMING_UPDATE,
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emc->regs + EMC_TIMING_CONTROL);
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return 0;
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}
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timeout = wait_for_completion_timeout(&emc->clk_handshake_complete,
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msecs_to_jiffies(100));
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if (timeout == 0) {
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dev_err(emc->dev, "EMC-CAR handshake failed\n");
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return -EIO;
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}
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return 0;
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}
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static int tegra_emc_clk_change_notify(struct notifier_block *nb,
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unsigned long msg, void *data)
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{
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struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
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struct clk_notifier_data *cnd = data;
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int err;
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switch (msg) {
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case PRE_RATE_CHANGE:
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err = emc_prepare_timing_change(emc, cnd->new_rate);
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break;
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case ABORT_RATE_CHANGE:
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err = emc_prepare_timing_change(emc, cnd->old_rate);
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if (err)
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break;
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err = emc_complete_timing_change(emc, true);
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break;
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case POST_RATE_CHANGE:
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err = emc_complete_timing_change(emc, false);
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break;
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default:
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return NOTIFY_DONE;
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}
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return notifier_from_errno(err);
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}
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static int load_one_timing_from_dt(struct tegra_emc *emc,
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struct emc_timing *timing,
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struct device_node *node)
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{
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u32 rate;
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int err;
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if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
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dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
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return -EINVAL;
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}
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err = of_property_read_u32(node, "clock-frequency", &rate);
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if (err) {
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dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
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node, err);
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return err;
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}
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err = of_property_read_u32_array(node, "nvidia,emc-registers",
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timing->data,
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ARRAY_SIZE(emc_timing_registers));
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if (err) {
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dev_err(emc->dev,
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"timing %pOF: failed to read emc timing data: %d\n",
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node, err);
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return err;
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}
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/*
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* The EMC clock rate is twice the bus rate, and the bus rate is
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* measured in kHz.
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*/
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timing->rate = rate * 2 * 1000;
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dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
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__func__, node, timing->rate);
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return 0;
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}
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static int cmp_timings(const void *_a, const void *_b)
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{
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const struct emc_timing *a = _a;
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const struct emc_timing *b = _b;
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if (a->rate < b->rate)
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return -1;
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if (a->rate > b->rate)
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return 1;
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return 0;
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}
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static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
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struct device_node *node)
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{
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struct device_node *child;
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struct emc_timing *timing;
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int child_count;
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int err;
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child_count = of_get_child_count(node);
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if (!child_count) {
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dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
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return -EINVAL;
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}
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emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
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GFP_KERNEL);
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if (!emc->timings)
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return -ENOMEM;
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emc->num_timings = child_count;
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timing = emc->timings;
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for_each_child_of_node(node, child) {
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err = load_one_timing_from_dt(emc, timing++, child);
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if (err) {
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of_node_put(child);
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return err;
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}
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}
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sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
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NULL);
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dev_info(emc->dev,
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"got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
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emc->num_timings,
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tegra_read_ram_code(),
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emc->timings[0].rate / 1000000,
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emc->timings[emc->num_timings - 1].rate / 1000000);
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return 0;
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}
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static struct device_node *
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tegra_emc_find_node_by_ram_code(struct device *dev)
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{
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struct device_node *np;
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u32 value, ram_code;
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int err;
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if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
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return of_node_get(dev->of_node);
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ram_code = tegra_read_ram_code();
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for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
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np = of_find_node_by_name(np, "emc-tables")) {
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err = of_property_read_u32(np, "nvidia,ram-code", &value);
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if (err || value != ram_code) {
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of_node_put(np);
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continue;
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}
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return np;
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}
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dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
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ram_code);
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return NULL;
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}
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static int emc_setup_hw(struct tegra_emc *emc)
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{
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u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
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u32 emc_cfg, emc_dbg;
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emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
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/*
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* Depending on a memory type, DRAM should enter either self-refresh
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* or power-down state on EMC clock change.
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*/
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if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
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!(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
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dev_err(emc->dev,
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"bootloader didn't specify DRAM auto-suspend mode\n");
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return -EINVAL;
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}
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/* enable EMC and CAR to handshake on PLL divider/source changes */
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emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
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writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
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/* initialize interrupt */
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writel_relaxed(intmask, emc->regs + EMC_INTMASK);
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writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
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/* ensure that unwanted debug features are disabled */
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emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
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emc_dbg |= EMC_DBG_CFG_PRIORITY;
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emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
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emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
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emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
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writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
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return 0;
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}
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static long emc_round_rate(unsigned long rate,
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unsigned long min_rate,
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unsigned long max_rate,
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void *arg)
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{
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struct emc_timing *timing = NULL;
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struct tegra_emc *emc = arg;
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unsigned int i;
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min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
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for (i = 0; i < emc->num_timings; i++) {
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if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
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continue;
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if (emc->timings[i].rate > max_rate) {
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i = max(i, 1u) - 1;
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if (emc->timings[i].rate < min_rate)
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break;
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}
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if (emc->timings[i].rate < min_rate)
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continue;
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timing = &emc->timings[i];
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break;
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}
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if (!timing) {
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dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
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rate, min_rate, max_rate);
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return -EINVAL;
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}
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return timing->rate;
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}
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/*
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* debugfs interface
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*
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* The memory controller driver exposes some files in debugfs that can be used
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* to control the EMC frequency. The top-level directory can be found here:
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*
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* /sys/kernel/debug/emc
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*
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* It contains the following files:
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*
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* - available_rates: This file contains a list of valid, space-separated
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* EMC frequencies.
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*
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* - min_rate: Writing a value to this file sets the given frequency as the
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* floor of the permitted range. If this is higher than the currently
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* configured EMC frequency, this will cause the frequency to be
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* increased so that it stays within the valid range.
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*
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* - max_rate: Similarily to the min_rate file, writing a value to this file
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* sets the given frequency as the ceiling of the permitted range. If
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* the value is lower than the currently configured EMC frequency, this
|
|
* will cause the frequency to be decreased so that it stays within the
|
|
* valid range.
|
|
*/
|
|
|
|
static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < emc->num_timings; i++)
|
|
if (rate == emc->timings[i].rate)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
|
|
{
|
|
struct tegra_emc *emc = s->private;
|
|
const char *prefix = "";
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < emc->num_timings; i++) {
|
|
seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
|
|
prefix = " ";
|
|
}
|
|
|
|
seq_puts(s, "\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_emc_debug_available_rates_open(struct inode *inode,
|
|
struct file *file)
|
|
{
|
|
return single_open(file, tegra_emc_debug_available_rates_show,
|
|
inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations tegra_emc_debug_available_rates_fops = {
|
|
.open = tegra_emc_debug_available_rates_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
|
|
{
|
|
struct tegra_emc *emc = data;
|
|
|
|
*rate = emc->debugfs.min_rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
|
|
{
|
|
struct tegra_emc *emc = data;
|
|
int err;
|
|
|
|
if (!tegra_emc_validate_rate(emc, rate))
|
|
return -EINVAL;
|
|
|
|
err = clk_set_min_rate(emc->clk, rate);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
emc->debugfs.min_rate = rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
|
|
tegra_emc_debug_min_rate_get,
|
|
tegra_emc_debug_min_rate_set, "%llu\n");
|
|
|
|
static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
|
|
{
|
|
struct tegra_emc *emc = data;
|
|
|
|
*rate = emc->debugfs.max_rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
|
|
{
|
|
struct tegra_emc *emc = data;
|
|
int err;
|
|
|
|
if (!tegra_emc_validate_rate(emc, rate))
|
|
return -EINVAL;
|
|
|
|
err = clk_set_max_rate(emc->clk, rate);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
emc->debugfs.max_rate = rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
|
|
tegra_emc_debug_max_rate_get,
|
|
tegra_emc_debug_max_rate_set, "%llu\n");
|
|
|
|
static void tegra_emc_debugfs_init(struct tegra_emc *emc)
|
|
{
|
|
struct device *dev = emc->dev;
|
|
unsigned int i;
|
|
int err;
|
|
|
|
emc->debugfs.min_rate = ULONG_MAX;
|
|
emc->debugfs.max_rate = 0;
|
|
|
|
for (i = 0; i < emc->num_timings; i++) {
|
|
if (emc->timings[i].rate < emc->debugfs.min_rate)
|
|
emc->debugfs.min_rate = emc->timings[i].rate;
|
|
|
|
if (emc->timings[i].rate > emc->debugfs.max_rate)
|
|
emc->debugfs.max_rate = emc->timings[i].rate;
|
|
}
|
|
|
|
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
|
|
emc->debugfs.max_rate);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
|
|
emc->debugfs.min_rate, emc->debugfs.max_rate,
|
|
emc->clk);
|
|
}
|
|
|
|
emc->debugfs.root = debugfs_create_dir("emc", NULL);
|
|
if (!emc->debugfs.root) {
|
|
dev_err(emc->dev, "failed to create debugfs directory\n");
|
|
return;
|
|
}
|
|
|
|
debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root,
|
|
emc, &tegra_emc_debug_available_rates_fops);
|
|
debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
|
|
emc, &tegra_emc_debug_min_rate_fops);
|
|
debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
|
|
emc, &tegra_emc_debug_max_rate_fops);
|
|
}
|
|
|
|
static int tegra_emc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np;
|
|
struct tegra_emc *emc;
|
|
struct resource *res;
|
|
int irq, err;
|
|
|
|
/* driver has nothing to do in a case of memory timing absence */
|
|
if (of_get_child_count(pdev->dev.of_node) == 0) {
|
|
dev_info(&pdev->dev,
|
|
"EMC device tree node doesn't have memory timings\n");
|
|
return 0;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "interrupt not specified\n");
|
|
dev_err(&pdev->dev, "please update your device tree\n");
|
|
return irq;
|
|
}
|
|
|
|
np = tegra_emc_find_node_by_ram_code(&pdev->dev);
|
|
if (!np)
|
|
return -EINVAL;
|
|
|
|
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
|
|
if (!emc) {
|
|
of_node_put(np);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
init_completion(&emc->clk_handshake_complete);
|
|
emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
|
|
emc->dev = &pdev->dev;
|
|
|
|
err = tegra_emc_load_timings_from_dt(emc, np);
|
|
of_node_put(np);
|
|
if (err)
|
|
return err;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
emc->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(emc->regs))
|
|
return PTR_ERR(emc->regs);
|
|
|
|
err = emc_setup_hw(emc);
|
|
if (err)
|
|
return err;
|
|
|
|
err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
|
|
dev_name(&pdev->dev), emc);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err);
|
|
return err;
|
|
}
|
|
|
|
tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
|
|
|
|
emc->clk = devm_clk_get(&pdev->dev, "emc");
|
|
if (IS_ERR(emc->clk)) {
|
|
err = PTR_ERR(emc->clk);
|
|
dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
|
|
goto unset_cb;
|
|
}
|
|
|
|
err = clk_notifier_register(emc->clk, &emc->clk_nb);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
|
|
err);
|
|
goto unset_cb;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, emc);
|
|
tegra_emc_debugfs_init(emc);
|
|
|
|
return 0;
|
|
|
|
unset_cb:
|
|
tegra20_clk_set_emc_round_callback(NULL, NULL);
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id tegra_emc_of_match[] = {
|
|
{ .compatible = "nvidia,tegra20-emc", },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver tegra_emc_driver = {
|
|
.probe = tegra_emc_probe,
|
|
.driver = {
|
|
.name = "tegra20-emc",
|
|
.of_match_table = tegra_emc_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
|
|
static int __init tegra_emc_init(void)
|
|
{
|
|
return platform_driver_register(&tegra_emc_driver);
|
|
}
|
|
subsys_initcall(tegra_emc_init);
|