mirror of https://gitee.com/openkylin/linux.git
1069 lines
28 KiB
C
1069 lines
28 KiB
C
/*
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* Freescale MPC85xx Memory Controller kenel module
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/ctype.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/edac.h>
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#include <linux/smp.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include "edac_module.h"
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#include "edac_core.h"
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#include "mpc85xx_edac.h"
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static int edac_dev_idx;
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static int edac_pci_idx;
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static int edac_mc_idx;
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static u32 orig_ddr_err_disable;
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static u32 orig_ddr_err_sbe;
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/*
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* PCI Err defines
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*/
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#ifdef CONFIG_PCI
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static u32 orig_pci_err_cap_dr;
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static u32 orig_pci_err_en;
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#endif
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static u32 orig_l2_err_disable;
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static u32 orig_hid1[2];
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/************************ MC SYSFS parts ***********************************/
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static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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MPC85XX_MC_DATA_ERR_INJECT_HI));
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}
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static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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MPC85XX_MC_DATA_ERR_INJECT_LO));
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}
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static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
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}
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static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
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{
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.attr = {
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.name = "inject_data_hi",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_mc_inject_data_hi_show,
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.store = mpc85xx_mc_inject_data_hi_store},
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{
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.attr = {
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.name = "inject_data_lo",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_mc_inject_data_lo_show,
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.store = mpc85xx_mc_inject_data_lo_store},
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{
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.attr = {
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.name = "inject_ctrl",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_mc_inject_ctrl_show,
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.store = mpc85xx_mc_inject_ctrl_store},
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/* End of list */
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{
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.attr = {.name = NULL}
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}
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};
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static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
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{
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mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
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}
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/**************************** PCI Err device ***************************/
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#ifdef CONFIG_PCI
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static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
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{
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
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/* master aborts can happen during PCI config cycles */
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if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
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return;
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}
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printk(KERN_ERR "PCI error(s) detected\n");
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printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
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printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
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printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
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printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
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printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
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printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
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if (err_detect & PCI_EDE_PERR_MASK)
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edac_pci_handle_pe(pci, pci->ctl_name);
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if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
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edac_pci_handle_npe(pci, pci->ctl_name);
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}
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static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
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{
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struct edac_pci_ctl_info *pci = dev_id;
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
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if (!err_detect)
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return IRQ_NONE;
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mpc85xx_pci_check(pci);
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return IRQ_HANDLED;
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}
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static int __devinit mpc85xx_pci_err_probe(struct of_device *op,
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const struct of_device_id *match)
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{
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struct edac_pci_ctl_info *pci;
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struct mpc85xx_pci_pdata *pdata;
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struct resource r;
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int res = 0;
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if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
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return -ENOMEM;
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pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
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if (!pci)
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return -ENOMEM;
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pdata = pci->pvt_info;
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pdata->name = "mpc85xx_pci_err";
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pdata->irq = NO_IRQ;
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dev_set_drvdata(&op->dev, pci);
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pci->dev = &op->dev;
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pci->mod_name = EDAC_MOD_STR;
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pci->ctl_name = pdata->name;
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pci->dev_name = op->dev.bus_id;
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if (edac_op_state == EDAC_OPSTATE_POLL)
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pci->edac_check = mpc85xx_pci_check;
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pdata->edac_idx = edac_pci_idx++;
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res = of_address_to_resource(op->node, 0, &r);
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if (res) {
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printk(KERN_ERR "%s: Unable to get resource for "
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"PCI err regs\n", __func__);
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goto err;
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}
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/* we only need the error registers */
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r.start += 0xe00;
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if (!devm_request_mem_region(&op->dev, r.start,
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r.end - r.start + 1, pdata->name)) {
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printk(KERN_ERR "%s: Error while requesting mem region\n",
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__func__);
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res = -EBUSY;
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goto err;
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}
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pdata->pci_vbase = devm_ioremap(&op->dev, r.start,
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r.end - r.start + 1);
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if (!pdata->pci_vbase) {
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printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
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res = -ENOMEM;
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goto err;
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}
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orig_pci_err_cap_dr =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
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/* PCI master abort is expected during config cycles */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
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orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
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/* disable master abort reporting */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
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if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
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debugf3("%s(): failed edac_pci_add_device()\n", __func__);
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goto err;
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}
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if (edac_op_state == EDAC_OPSTATE_INT) {
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pdata->irq = irq_of_parse_and_map(op->node, 0);
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res = devm_request_irq(&op->dev, pdata->irq,
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mpc85xx_pci_isr, IRQF_DISABLED,
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"[EDAC] PCI err", pci);
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if (res < 0) {
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printk(KERN_ERR
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"%s: Unable to requiest irq %d for "
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"MPC85xx PCI err\n", __func__, pdata->irq);
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irq_dispose_mapping(pdata->irq);
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res = -ENODEV;
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goto err2;
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}
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printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
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pdata->irq);
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}
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devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
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debugf3("%s(): success\n", __func__);
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printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
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return 0;
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err2:
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edac_pci_del_device(&op->dev);
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err:
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edac_pci_free_ctl_info(pci);
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devres_release_group(&op->dev, mpc85xx_pci_err_probe);
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return res;
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}
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static int mpc85xx_pci_err_remove(struct of_device *op)
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{
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struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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debugf0("%s()\n", __func__);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
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orig_pci_err_cap_dr);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
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edac_pci_del_device(pci->dev);
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if (edac_op_state == EDAC_OPSTATE_INT)
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irq_dispose_mapping(pdata->irq);
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edac_pci_free_ctl_info(pci);
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return 0;
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}
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static struct of_device_id mpc85xx_pci_err_of_match[] = {
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{
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.compatible = "fsl,mpc8540-pcix",
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},
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{
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.compatible = "fsl,mpc8540-pci",
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},
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{},
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};
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static struct of_platform_driver mpc85xx_pci_err_driver = {
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.owner = THIS_MODULE,
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.name = "mpc85xx_pci_err",
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.match_table = mpc85xx_pci_err_of_match,
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.probe = mpc85xx_pci_err_probe,
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.remove = __devexit_p(mpc85xx_pci_err_remove),
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.driver = {
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.name = "mpc85xx_pci_err",
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.owner = THIS_MODULE,
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},
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};
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#endif /* CONFIG_PCI */
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/**************************** L2 Err device ***************************/
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/************************ L2 SYSFS parts ***********************************/
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static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
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*edac_dev, char *data)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
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}
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static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
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*edac_dev, char *data)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
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}
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static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
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*edac_dev, char *data)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
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}
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static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
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*edac_dev, const char *data,
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size_t count)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
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*edac_dev, const char *data,
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size_t count)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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|
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static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
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*edac_dev, const char *data,
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size_t count)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
|
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|
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static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
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{
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.attr = {
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.name = "inject_data_hi",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_l2_inject_data_hi_show,
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.store = mpc85xx_l2_inject_data_hi_store},
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{
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.attr = {
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.name = "inject_data_lo",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_l2_inject_data_lo_show,
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.store = mpc85xx_l2_inject_data_lo_store},
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{
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.attr = {
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.name = "inject_ctrl",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_l2_inject_ctrl_show,
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.store = mpc85xx_l2_inject_ctrl_store},
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/* End of list */
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{
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.attr = {.name = NULL}
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}
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};
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|
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static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
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*edac_dev)
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{
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edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
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}
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|
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/***************************** L2 ops ***********************************/
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|
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static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
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if (!(err_detect & L2_EDE_MASK))
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return;
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|
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printk(KERN_ERR "ECC Error in CPU L2 cache\n");
|
|
printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
|
|
printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
|
|
printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
|
|
printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
|
|
printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
|
|
printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
|
|
|
|
/* clear error detect register */
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
|
|
|
|
if (err_detect & L2_EDE_CE_MASK)
|
|
edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
|
|
|
|
if (err_detect & L2_EDE_UE_MASK)
|
|
edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
|
|
}
|
|
|
|
static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
|
|
{
|
|
struct edac_device_ctl_info *edac_dev = dev_id;
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
u32 err_detect;
|
|
|
|
err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
|
|
|
|
if (!(err_detect & L2_EDE_MASK))
|
|
return IRQ_NONE;
|
|
|
|
mpc85xx_l2_check(edac_dev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
|
|
const struct of_device_id *match)
|
|
{
|
|
struct edac_device_ctl_info *edac_dev;
|
|
struct mpc85xx_l2_pdata *pdata;
|
|
struct resource r;
|
|
int res;
|
|
|
|
if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
|
|
"cpu", 1, "L", 1, 2, NULL, 0,
|
|
edac_dev_idx);
|
|
if (!edac_dev) {
|
|
devres_release_group(&op->dev, mpc85xx_l2_err_probe);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pdata = edac_dev->pvt_info;
|
|
pdata->name = "mpc85xx_l2_err";
|
|
pdata->irq = NO_IRQ;
|
|
edac_dev->dev = &op->dev;
|
|
dev_set_drvdata(edac_dev->dev, edac_dev);
|
|
edac_dev->ctl_name = pdata->name;
|
|
edac_dev->dev_name = pdata->name;
|
|
|
|
res = of_address_to_resource(op->node, 0, &r);
|
|
if (res) {
|
|
printk(KERN_ERR "%s: Unable to get resource for "
|
|
"L2 err regs\n", __func__);
|
|
goto err;
|
|
}
|
|
|
|
/* we only need the error registers */
|
|
r.start += 0xe00;
|
|
|
|
if (!devm_request_mem_region(&op->dev, r.start,
|
|
r.end - r.start + 1, pdata->name)) {
|
|
printk(KERN_ERR "%s: Error while requesting mem region\n",
|
|
__func__);
|
|
res = -EBUSY;
|
|
goto err;
|
|
}
|
|
|
|
pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
|
|
if (!pdata->l2_vbase) {
|
|
printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
|
|
res = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
|
|
|
|
orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
|
|
|
|
/* clear the err_dis */
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
|
|
|
|
edac_dev->mod_name = EDAC_MOD_STR;
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL)
|
|
edac_dev->edac_check = mpc85xx_l2_check;
|
|
|
|
mpc85xx_set_l2_sysfs_attributes(edac_dev);
|
|
|
|
pdata->edac_idx = edac_dev_idx++;
|
|
|
|
if (edac_device_add_device(edac_dev) > 0) {
|
|
debugf3("%s(): failed edac_device_add_device()\n", __func__);
|
|
goto err;
|
|
}
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
pdata->irq = irq_of_parse_and_map(op->node, 0);
|
|
res = devm_request_irq(&op->dev, pdata->irq,
|
|
mpc85xx_l2_isr, IRQF_DISABLED,
|
|
"[EDAC] L2 err", edac_dev);
|
|
if (res < 0) {
|
|
printk(KERN_ERR
|
|
"%s: Unable to requiest irq %d for "
|
|
"MPC85xx L2 err\n", __func__, pdata->irq);
|
|
irq_dispose_mapping(pdata->irq);
|
|
res = -ENODEV;
|
|
goto err2;
|
|
}
|
|
|
|
printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
|
|
pdata->irq);
|
|
|
|
edac_dev->op_state = OP_RUNNING_INTERRUPT;
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
|
|
}
|
|
|
|
devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
|
|
|
|
debugf3("%s(): success\n", __func__);
|
|
printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
edac_device_del_device(&op->dev);
|
|
err:
|
|
devres_release_group(&op->dev, mpc85xx_l2_err_probe);
|
|
edac_device_free_ctl_info(edac_dev);
|
|
return res;
|
|
}
|
|
|
|
static int mpc85xx_l2_err_remove(struct of_device *op)
|
|
{
|
|
struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
debugf0("%s()\n", __func__);
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
|
|
irq_dispose_mapping(pdata->irq);
|
|
}
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
|
|
edac_device_del_device(&op->dev);
|
|
edac_device_free_ctl_info(edac_dev);
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id mpc85xx_l2_err_of_match[] = {
|
|
/* deprecate the fsl,85.. forms in the future, 2.6.30? */
|
|
{ .compatible = "fsl,8540-l2-cache-controller", },
|
|
{ .compatible = "fsl,8541-l2-cache-controller", },
|
|
{ .compatible = "fsl,8544-l2-cache-controller", },
|
|
{ .compatible = "fsl,8548-l2-cache-controller", },
|
|
{ .compatible = "fsl,8555-l2-cache-controller", },
|
|
{ .compatible = "fsl,8568-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8536-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8540-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8541-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8544-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8548-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8555-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8560-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8568-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8572-l2-cache-controller", },
|
|
{},
|
|
};
|
|
|
|
static struct of_platform_driver mpc85xx_l2_err_driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "mpc85xx_l2_err",
|
|
.match_table = mpc85xx_l2_err_of_match,
|
|
.probe = mpc85xx_l2_err_probe,
|
|
.remove = mpc85xx_l2_err_remove,
|
|
.driver = {
|
|
.name = "mpc85xx_l2_err",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
/**************************** MC Err device ***************************/
|
|
|
|
static void mpc85xx_mc_check(struct mem_ctl_info *mci)
|
|
{
|
|
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
|
|
struct csrow_info *csrow;
|
|
u32 err_detect;
|
|
u32 syndrome;
|
|
u32 err_addr;
|
|
u32 pfn;
|
|
int row_index;
|
|
|
|
err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
|
|
if (err_detect)
|
|
return;
|
|
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
|
|
err_detect);
|
|
|
|
/* no more processing if not ECC bit errors */
|
|
if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
|
|
return;
|
|
}
|
|
|
|
syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
|
|
err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
|
|
pfn = err_addr >> PAGE_SHIFT;
|
|
|
|
for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
|
|
csrow = &mci->csrows[row_index];
|
|
if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
|
|
break;
|
|
}
|
|
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n",
|
|
in_be32(pdata->mc_vbase +
|
|
MPC85XX_MC_CAPTURE_DATA_HI));
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n",
|
|
in_be32(pdata->mc_vbase +
|
|
MPC85XX_MC_CAPTURE_DATA_LO));
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome);
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr);
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
|
|
|
|
/* we are out of range */
|
|
if (row_index == mci->nr_csrows)
|
|
mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
|
|
|
|
if (err_detect & DDR_EDE_SBE)
|
|
edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
|
|
syndrome, row_index, 0, mci->ctl_name);
|
|
|
|
if (err_detect & DDR_EDE_MBE)
|
|
edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
|
|
row_index, mci->ctl_name);
|
|
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
|
|
}
|
|
|
|
static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
|
|
{
|
|
struct mem_ctl_info *mci = dev_id;
|
|
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
|
|
u32 err_detect;
|
|
|
|
err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
|
|
if (!err_detect)
|
|
return IRQ_NONE;
|
|
|
|
mpc85xx_mc_check(mci);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
|
|
{
|
|
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
|
|
struct csrow_info *csrow;
|
|
u32 sdram_ctl;
|
|
u32 sdtype;
|
|
enum mem_type mtype;
|
|
u32 cs_bnds;
|
|
int index;
|
|
|
|
sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
|
|
|
|
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
|
|
if (sdram_ctl & DSC_RD_EN) {
|
|
switch (sdtype) {
|
|
case DSC_SDTYPE_DDR:
|
|
mtype = MEM_RDDR;
|
|
break;
|
|
case DSC_SDTYPE_DDR2:
|
|
mtype = MEM_RDDR2;
|
|
break;
|
|
default:
|
|
mtype = MEM_UNKNOWN;
|
|
break;
|
|
}
|
|
} else {
|
|
switch (sdtype) {
|
|
case DSC_SDTYPE_DDR:
|
|
mtype = MEM_DDR;
|
|
break;
|
|
case DSC_SDTYPE_DDR2:
|
|
mtype = MEM_DDR2;
|
|
break;
|
|
default:
|
|
mtype = MEM_UNKNOWN;
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (index = 0; index < mci->nr_csrows; index++) {
|
|
u32 start;
|
|
u32 end;
|
|
|
|
csrow = &mci->csrows[index];
|
|
cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
|
|
(index * MPC85XX_MC_CS_BNDS_OFS));
|
|
start = (cs_bnds & 0xfff0000) << 4;
|
|
end = ((cs_bnds & 0xfff) << 20);
|
|
if (start)
|
|
start |= 0xfffff;
|
|
if (end)
|
|
end |= 0xfffff;
|
|
|
|
if (start == end)
|
|
continue; /* not populated */
|
|
|
|
csrow->first_page = start >> PAGE_SHIFT;
|
|
csrow->last_page = end >> PAGE_SHIFT;
|
|
csrow->nr_pages = csrow->last_page + 1 - csrow->first_page;
|
|
csrow->grain = 8;
|
|
csrow->mtype = mtype;
|
|
csrow->dtype = DEV_UNKNOWN;
|
|
if (sdram_ctl & DSC_X32_EN)
|
|
csrow->dtype = DEV_X32;
|
|
csrow->edac_mode = EDAC_SECDED;
|
|
}
|
|
}
|
|
|
|
static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
|
|
const struct of_device_id *match)
|
|
{
|
|
struct mem_ctl_info *mci;
|
|
struct mpc85xx_mc_pdata *pdata;
|
|
struct resource r;
|
|
u32 sdram_ctl;
|
|
int res;
|
|
|
|
if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
|
|
if (!mci) {
|
|
devres_release_group(&op->dev, mpc85xx_mc_err_probe);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pdata = mci->pvt_info;
|
|
pdata->name = "mpc85xx_mc_err";
|
|
pdata->irq = NO_IRQ;
|
|
mci->dev = &op->dev;
|
|
pdata->edac_idx = edac_mc_idx++;
|
|
dev_set_drvdata(mci->dev, mci);
|
|
mci->ctl_name = pdata->name;
|
|
mci->dev_name = pdata->name;
|
|
|
|
res = of_address_to_resource(op->node, 0, &r);
|
|
if (res) {
|
|
printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
|
|
__func__);
|
|
goto err;
|
|
}
|
|
|
|
if (!devm_request_mem_region(&op->dev, r.start,
|
|
r.end - r.start + 1, pdata->name)) {
|
|
printk(KERN_ERR "%s: Error while requesting mem region\n",
|
|
__func__);
|
|
res = -EBUSY;
|
|
goto err;
|
|
}
|
|
|
|
pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
|
|
if (!pdata->mc_vbase) {
|
|
printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
|
|
res = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
|
|
if (!(sdram_ctl & DSC_ECC_EN)) {
|
|
/* no ECC */
|
|
printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
|
|
res = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
debugf3("%s(): init mci\n", __func__);
|
|
mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
|
|
MEM_FLAG_DDR | MEM_FLAG_DDR2;
|
|
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
|
mci->edac_cap = EDAC_FLAG_SECDED;
|
|
mci->mod_name = EDAC_MOD_STR;
|
|
mci->mod_ver = MPC85XX_REVISION;
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL)
|
|
mci->edac_check = mpc85xx_mc_check;
|
|
|
|
mci->ctl_page_to_phys = NULL;
|
|
|
|
mci->scrub_mode = SCRUB_SW_SRC;
|
|
|
|
mpc85xx_set_mc_sysfs_attributes(mci);
|
|
|
|
mpc85xx_init_csrows(mci);
|
|
|
|
#ifdef CONFIG_EDAC_DEBUG
|
|
edac_mc_register_mcidev_debug((struct attribute **)debug_attr);
|
|
#endif
|
|
|
|
/* store the original error disable bits */
|
|
orig_ddr_err_disable =
|
|
in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
|
|
|
|
/* clear all error bits */
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
|
|
|
|
if (edac_mc_add_mc(mci)) {
|
|
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
|
|
goto err;
|
|
}
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
|
|
DDR_EIE_MBEE | DDR_EIE_SBEE);
|
|
|
|
/* store the original error management threshold */
|
|
orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
|
|
MPC85XX_MC_ERR_SBE) & 0xff0000;
|
|
|
|
/* set threshold to 1 error per interrupt */
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
|
|
|
|
/* register interrupts */
|
|
pdata->irq = irq_of_parse_and_map(op->node, 0);
|
|
res = devm_request_irq(&op->dev, pdata->irq,
|
|
mpc85xx_mc_isr,
|
|
IRQF_DISABLED | IRQF_SHARED,
|
|
"[EDAC] MC err", mci);
|
|
if (res < 0) {
|
|
printk(KERN_ERR "%s: Unable to request irq %d for "
|
|
"MPC85xx DRAM ERR\n", __func__, pdata->irq);
|
|
irq_dispose_mapping(pdata->irq);
|
|
res = -ENODEV;
|
|
goto err2;
|
|
}
|
|
|
|
printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
|
|
pdata->irq);
|
|
}
|
|
|
|
devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
|
|
debugf3("%s(): success\n", __func__);
|
|
printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
edac_mc_del_mc(&op->dev);
|
|
err:
|
|
devres_release_group(&op->dev, mpc85xx_mc_err_probe);
|
|
edac_mc_free(mci);
|
|
return res;
|
|
}
|
|
|
|
static int mpc85xx_mc_err_remove(struct of_device *op)
|
|
{
|
|
struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
|
|
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
|
|
|
|
debugf0("%s()\n", __func__);
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
|
|
irq_dispose_mapping(pdata->irq);
|
|
}
|
|
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
|
|
orig_ddr_err_disable);
|
|
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
|
|
|
|
edac_mc_del_mc(&op->dev);
|
|
edac_mc_free(mci);
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id mpc85xx_mc_err_of_match[] = {
|
|
/* deprecate the fsl,85.. forms in the future, 2.6.30? */
|
|
{ .compatible = "fsl,8540-memory-controller", },
|
|
{ .compatible = "fsl,8541-memory-controller", },
|
|
{ .compatible = "fsl,8544-memory-controller", },
|
|
{ .compatible = "fsl,8548-memory-controller", },
|
|
{ .compatible = "fsl,8555-memory-controller", },
|
|
{ .compatible = "fsl,8568-memory-controller", },
|
|
{ .compatible = "fsl,mpc8536-memory-controller", },
|
|
{ .compatible = "fsl,mpc8540-memory-controller", },
|
|
{ .compatible = "fsl,mpc8541-memory-controller", },
|
|
{ .compatible = "fsl,mpc8544-memory-controller", },
|
|
{ .compatible = "fsl,mpc8548-memory-controller", },
|
|
{ .compatible = "fsl,mpc8555-memory-controller", },
|
|
{ .compatible = "fsl,mpc8560-memory-controller", },
|
|
{ .compatible = "fsl,mpc8568-memory-controller", },
|
|
{ .compatible = "fsl,mpc8572-memory-controller", },
|
|
{},
|
|
};
|
|
|
|
static struct of_platform_driver mpc85xx_mc_err_driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "mpc85xx_mc_err",
|
|
.match_table = mpc85xx_mc_err_of_match,
|
|
.probe = mpc85xx_mc_err_probe,
|
|
.remove = mpc85xx_mc_err_remove,
|
|
.driver = {
|
|
.name = "mpc85xx_mc_err",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
|
|
static void __init mpc85xx_mc_clear_rfxe(void *data)
|
|
{
|
|
orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
|
|
mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
|
|
}
|
|
|
|
|
|
static int __init mpc85xx_mc_init(void)
|
|
{
|
|
int res = 0;
|
|
|
|
printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
|
|
"(C) 2006 Montavista Software\n");
|
|
|
|
/* make sure error reporting method is sane */
|
|
switch (edac_op_state) {
|
|
case EDAC_OPSTATE_POLL:
|
|
case EDAC_OPSTATE_INT:
|
|
break;
|
|
default:
|
|
edac_op_state = EDAC_OPSTATE_INT;
|
|
break;
|
|
}
|
|
|
|
res = of_register_platform_driver(&mpc85xx_mc_err_driver);
|
|
if (res)
|
|
printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
|
|
|
|
res = of_register_platform_driver(&mpc85xx_l2_err_driver);
|
|
if (res)
|
|
printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
|
|
|
|
#ifdef CONFIG_PCI
|
|
res = of_register_platform_driver(&mpc85xx_pci_err_driver);
|
|
if (res)
|
|
printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
|
|
#endif
|
|
|
|
/*
|
|
* need to clear HID1[RFXE] to disable machine check int
|
|
* so we can catch it
|
|
*/
|
|
if (edac_op_state == EDAC_OPSTATE_INT)
|
|
on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
module_init(mpc85xx_mc_init);
|
|
|
|
static void __exit mpc85xx_mc_restore_hid1(void *data)
|
|
{
|
|
mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
|
|
}
|
|
|
|
static void __exit mpc85xx_mc_exit(void)
|
|
{
|
|
on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
|
|
#ifdef CONFIG_PCI
|
|
of_unregister_platform_driver(&mpc85xx_pci_err_driver);
|
|
#endif
|
|
of_unregister_platform_driver(&mpc85xx_l2_err_driver);
|
|
of_unregister_platform_driver(&mpc85xx_mc_err_driver);
|
|
}
|
|
|
|
module_exit(mpc85xx_mc_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Montavista Software, Inc.");
|
|
module_param(edac_op_state, int, 0444);
|
|
MODULE_PARM_DESC(edac_op_state,
|
|
"EDAC Error Reporting state: 0=Poll, 2=Interrupt");
|