Andy Shevchenko 827e1579e1 pinctrl: baytrail: Rectify debounce support (part 2) ... The commit 04ff5a095d ("pinctrl: baytrail: Rectify debounce support") almost fixes the logic of debuonce but missed couple of things, i.e. typo in mask when disabling debounce and lack of enabling it back. This patch addresses above issues. Reported-by: Jean Delvare <jdelvare@suse.de> Fixes: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2017-01-30 15:46:33 +01:00
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Kconfig	pinctrl: intel: Add Intel Merrifield pin controller support	2016-06-29 09:59:35 +02:00
Makefile	pinctrl: intel: Add Intel Merrifield pin controller support	2016-06-29 09:59:35 +02:00
pinctrl-baytrail.c	pinctrl: baytrail: Rectify debounce support (part 2)	2017-01-30 15:46:33 +01:00
pinctrl-broxton.c	pinctrl: broxton: Use correct PADCFGLOCK offset	2017-01-11 13:47:11 +01:00
pinctrl-cherryview.c	Bulk pin control changes for the v4.10 kernel cycle:	2016-12-13 07:59:10 -08:00
pinctrl-intel.c	pinctrl: intel: Set pin direction properly	2017-01-11 13:49:05 +01:00
pinctrl-intel.h	pinctrl: intel: fix bug of register offset calculation	2015-12-10 23:01:41 +01:00
pinctrl-merrifield.c	pinctrl: intel: merrifield: Add missed check in mrfld_config_set()	2017-01-30 09:15:10 +01:00
pinctrl-sunrisepoint.c	pinctrl: intel: fix bug of register offset calculation	2015-12-10 23:01:41 +01:00