mirror of https://gitee.com/openkylin/linux.git
453 lines
12 KiB
C
453 lines
12 KiB
C
/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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const struct arm64_midr_revidr *fix;
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u32 midr = read_cpuid_id(), revidr;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (!MIDR_IS_CPU_MODEL_RANGE(midr, entry->midr_model,
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entry->midr_range_min,
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entry->midr_range_max))
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return false;
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midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
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revidr = read_cpuid(REVIDR_EL1);
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for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
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if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
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return false;
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return true;
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}
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static bool __maybe_unused
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is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
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{
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u32 model;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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model = read_cpuid_id();
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model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
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MIDR_ARCHITECTURE_MASK;
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return model == entry->midr_model;
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}
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static bool
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has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
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}
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static void
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
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{
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/* Clear SCTLR_EL1.UCT */
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config_sctlr_el1(SCTLR_EL1_UCT, 0);
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}
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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#ifdef CONFIG_KVM
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extern char __qcom_hyp_sanitize_link_stack_start[];
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extern char __qcom_hyp_sanitize_link_stack_end[];
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extern char __smccc_workaround_1_smc_start[];
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extern char __smccc_workaround_1_smc_end[];
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extern char __smccc_workaround_1_hvc_start[];
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extern char __smccc_workaround_1_hvc_end[];
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static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
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int i;
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for (i = 0; i < SZ_2K; i += 0x80)
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memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
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flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
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}
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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static int last_slot = -1;
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static DEFINE_SPINLOCK(bp_lock);
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int cpu, slot = -1;
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spin_lock(&bp_lock);
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for_each_possible_cpu(cpu) {
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if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
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slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
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break;
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}
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}
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if (slot == -1) {
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last_slot++;
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BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
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/ SZ_2K) <= last_slot);
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slot = last_slot;
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__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
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}
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.fn, fn);
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spin_unlock(&bp_lock);
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}
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#else
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#define __qcom_hyp_sanitize_link_stack_start NULL
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#define __qcom_hyp_sanitize_link_stack_end NULL
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#define __smccc_workaround_1_smc_start NULL
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#define __smccc_workaround_1_smc_end NULL
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#define __smccc_workaround_1_hvc_start NULL
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#define __smccc_workaround_1_hvc_end NULL
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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__this_cpu_write(bp_hardening_data.fn, fn);
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}
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#endif /* CONFIG_KVM */
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static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
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bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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u64 pfr0;
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
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return;
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__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
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}
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#include <uapi/linux/psci.h>
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#include <linux/arm-smccc.h>
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#include <linux/psci.h>
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static void call_smc_arch_workaround_1(void)
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{
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void call_hvc_arch_workaround_1(void)
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{
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void
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enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
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{
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bp_hardening_cb_t cb;
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void *smccc_start, *smccc_end;
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struct arm_smccc_res res;
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
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return;
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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if (res.a0)
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return;
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cb = call_hvc_arch_workaround_1;
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smccc_start = __smccc_workaround_1_hvc_start;
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smccc_end = __smccc_workaround_1_hvc_end;
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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if (res.a0)
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return;
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cb = call_smc_arch_workaround_1;
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smccc_start = __smccc_workaround_1_smc_start;
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smccc_end = __smccc_workaround_1_smc_end;
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break;
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default:
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return;
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}
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install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
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return;
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}
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static void qcom_link_stack_sanitization(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static void
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qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
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{
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install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
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__qcom_hyp_sanitize_link_stack_start,
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__qcom_hyp_sanitize_link_stack_end);
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#define MIDR_RANGE(model, min, max) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = min, \
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.midr_range_max = max
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#define MIDR_ALL_VERSIONS(model) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = 0, \
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.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
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#define MIDR_FIXED(rev, revidr_mask) \
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.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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defined(CONFIG_ARM64_ERRATUM_824069)
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{
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/* Cortex-A53 r0p[012] */
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.desc = "ARM errata 826319, 827319, 824069",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
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.cpu_enable = cpu_enable_cache_maint_trap,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_819472
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{
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/* Cortex-A53 r0p[01] */
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.desc = "ARM errata 819472",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
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.cpu_enable = cpu_enable_cache_maint_trap,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_832075
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{
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 832075",
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.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
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MIDR_RANGE(MIDR_CORTEX_A57,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 2)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_834220
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{
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 834220",
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.capability = ARM64_WORKAROUND_834220,
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MIDR_RANGE(MIDR_CORTEX_A57,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 2)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_843419
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{
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 843419",
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.capability = ARM64_WORKAROUND_843419,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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MIDR_FIXED(0x4, BIT(8)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_845719
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{
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 845719",
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.capability = ARM64_WORKAROUND_845719,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_23154
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{
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/* Cavium ThunderX, pass 1.x */
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.desc = "Cavium erratum 23154",
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.capability = ARM64_WORKAROUND_CAVIUM_23154,
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MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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{
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/* Cavium ThunderX, T88 pass 1.x - 2.1 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 1)),
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},
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{
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/* Cavium ThunderX, T81 pass 1.0 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_30115
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{
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/* Cavium ThunderX, T88 pass 1.x - 2.2 */
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.desc = "Cavium erratum 30115",
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.capability = ARM64_WORKAROUND_CAVIUM_30115,
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MIDR_RANGE(MIDR_THUNDERX, 0x00,
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(1 << MIDR_VARIANT_SHIFT) | 2),
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},
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{
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/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
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.desc = "Cavium erratum 30115",
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.capability = ARM64_WORKAROUND_CAVIUM_30115,
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MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
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},
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{
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/* Cavium ThunderX, T83 pass 1.0 */
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.desc = "Cavium erratum 30115",
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.capability = ARM64_WORKAROUND_CAVIUM_30115,
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MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
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},
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#endif
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{
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.desc = "Mismatched cache line size",
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.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
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.matches = has_mismatched_cache_line_size,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.cpu_enable = cpu_enable_trap_ctr_access,
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},
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
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{
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.desc = "Qualcomm Technologies Falkor erratum 1003",
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.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
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MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(0, 0)),
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},
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{
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.desc = "Qualcomm Technologies Kryo erratum 1003",
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.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.midr_model = MIDR_QCOM_KRYO,
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.matches = is_kryo_midr,
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},
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#endif
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
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{
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.desc = "Qualcomm Technologies Falkor erratum 1009",
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.capability = ARM64_WORKAROUND_REPEAT_TLBI,
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MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(0, 0)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_858921
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{
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/* Cortex-A73 all versions */
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.desc = "ARM erratum 858921",
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.capability = ARM64_WORKAROUND_858921,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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},
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#endif
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
|
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.cpu_enable = enable_smccc_arch_workaround_1,
|
|
},
|
|
#endif
|
|
{
|
|
}
|
|
};
|