mirror of https://gitee.com/openkylin/linux.git
1201 lines
28 KiB
C
1201 lines
28 KiB
C
/*
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* SuperH FLCTL nand controller
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*
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* Copyright (c) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Atom Create Engineering Co., Ltd.
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*
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* Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_mtd.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sh_dma.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/sh_flctl.h>
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static struct nand_ecclayout flctl_4secc_oob_16 = {
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.eccbytes = 10,
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.eccpos = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
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.oobfree = {
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{.offset = 12,
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. length = 4} },
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};
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static struct nand_ecclayout flctl_4secc_oob_64 = {
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.eccbytes = 4 * 10,
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.eccpos = {
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6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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54, 55, 56, 57, 58, 59, 60, 61, 62, 63 },
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.oobfree = {
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{.offset = 2, .length = 4},
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{.offset = 16, .length = 6},
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{.offset = 32, .length = 6},
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{.offset = 48, .length = 6} },
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};
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr flctl_4secc_smallpage = {
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.options = NAND_BBT_SCAN2NDPAGE,
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.offs = 11,
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.len = 1,
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.pattern = scan_ff_pattern,
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};
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static struct nand_bbt_descr flctl_4secc_largepage = {
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.options = NAND_BBT_SCAN2NDPAGE,
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.offs = 0,
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.len = 2,
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.pattern = scan_ff_pattern,
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};
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static void empty_fifo(struct sh_flctl *flctl)
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{
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writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl));
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writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
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}
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static void start_translation(struct sh_flctl *flctl)
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{
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writeb(TRSTRT, FLTRCR(flctl));
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}
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static void timeout_error(struct sh_flctl *flctl, const char *str)
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{
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dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str);
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}
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static void wait_completion(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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if (readb(FLTRCR(flctl)) & TREND) {
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writeb(0x0, FLTRCR(flctl));
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return;
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}
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udelay(1);
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}
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timeout_error(flctl, __func__);
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writeb(0x0, FLTRCR(flctl));
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}
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static void flctl_dma_complete(void *param)
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{
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struct sh_flctl *flctl = param;
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complete(&flctl->dma_complete);
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}
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static void flctl_release_dma(struct sh_flctl *flctl)
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{
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if (flctl->chan_fifo0_rx) {
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dma_release_channel(flctl->chan_fifo0_rx);
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flctl->chan_fifo0_rx = NULL;
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}
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if (flctl->chan_fifo0_tx) {
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dma_release_channel(flctl->chan_fifo0_tx);
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flctl->chan_fifo0_tx = NULL;
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}
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}
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static void flctl_setup_dma(struct sh_flctl *flctl)
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{
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dma_cap_mask_t mask;
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struct dma_slave_config cfg;
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struct platform_device *pdev = flctl->pdev;
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struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev);
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int ret;
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if (!pdata)
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return;
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if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
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return;
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/* We can only either use DMA for both Tx and Rx or not use it at all */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
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(void *)(uintptr_t)pdata->slave_id_fifo0_tx);
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dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
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flctl->chan_fifo0_tx);
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if (!flctl->chan_fifo0_tx)
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return;
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memset(&cfg, 0, sizeof(cfg));
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cfg.direction = DMA_MEM_TO_DEV;
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cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
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cfg.src_addr = 0;
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ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
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if (ret < 0)
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goto err;
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flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
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(void *)(uintptr_t)pdata->slave_id_fifo0_rx);
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dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
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flctl->chan_fifo0_rx);
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if (!flctl->chan_fifo0_rx)
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goto err;
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cfg.direction = DMA_DEV_TO_MEM;
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cfg.dst_addr = 0;
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cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
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ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
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if (ret < 0)
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goto err;
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init_completion(&flctl->dma_complete);
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return;
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err:
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flctl_release_dma(flctl);
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}
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static void set_addr(struct mtd_info *mtd, int column, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t addr = 0;
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if (column == -1) {
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addr = page_addr; /* ERASE1 */
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} else if (page_addr != -1) {
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/* SEQIN, READ0, etc.. */
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if (flctl->chip.options & NAND_BUSWIDTH_16)
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column >>= 1;
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if (flctl->page_size) {
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addr = column & 0x0FFF;
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addr |= (page_addr & 0xff) << 16;
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addr |= ((page_addr >> 8) & 0xff) << 24;
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/* big than 128MB */
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if (flctl->rw_ADRCNT == ADRCNT2_E) {
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uint32_t addr2;
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addr2 = (page_addr >> 16) & 0xff;
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writel(addr2, FLADR2(flctl));
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}
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} else {
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addr = column;
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addr |= (page_addr & 0xff) << 8;
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addr |= ((page_addr >> 8) & 0xff) << 16;
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addr |= ((page_addr >> 16) & 0xff) << 24;
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}
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}
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writel(addr, FLADR(flctl));
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}
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static void wait_rfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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uint32_t val;
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/* check FIFO */
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val = readl(FLDTCNTR(flctl)) >> 16;
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if (val & 0xFF)
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return;
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udelay(1);
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}
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timeout_error(flctl, __func__);
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}
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static void wait_wfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t len, timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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/* check FIFO */
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len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
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if (len >= 4)
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return;
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udelay(1);
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}
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timeout_error(flctl, __func__);
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}
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static enum flctl_ecc_res_t wait_recfifo_ready
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(struct sh_flctl *flctl, int sector_number)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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void __iomem *ecc_reg[4];
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int i;
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int state = FL_SUCCESS;
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uint32_t data, size;
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/*
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* First this loops checks in FLDTCNTR if we are ready to read out the
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* oob data. This is the case if either all went fine without errors or
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* if the bottom part of the loop corrected the errors or marked them as
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* uncorrectable and the controller is given time to push the data into
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* the FIFO.
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*/
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while (timeout--) {
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/* check if all is ok and we can read out the OOB */
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size = readl(FLDTCNTR(flctl)) >> 24;
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if ((size & 0xFF) == 4)
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return state;
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/* check if a correction code has been calculated */
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if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) {
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/*
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* either we wait for the fifo to be filled or a
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* correction pattern is being generated
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*/
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udelay(1);
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continue;
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}
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/* check for an uncorrectable error */
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if (readl(FL4ECCCR(flctl)) & _4ECCFA) {
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/* check if we face a non-empty page */
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for (i = 0; i < 512; i++) {
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if (flctl->done_buff[i] != 0xff) {
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state = FL_ERROR; /* can't correct */
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break;
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}
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}
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if (state == FL_SUCCESS)
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dev_dbg(&flctl->pdev->dev,
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"reading empty sector %d, ecc error ignored\n",
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sector_number);
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writel(0, FL4ECCCR(flctl));
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continue;
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}
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/* start error correction */
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ecc_reg[0] = FL4ECCRESULT0(flctl);
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ecc_reg[1] = FL4ECCRESULT1(flctl);
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ecc_reg[2] = FL4ECCRESULT2(flctl);
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ecc_reg[3] = FL4ECCRESULT3(flctl);
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for (i = 0; i < 3; i++) {
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uint8_t org;
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unsigned int index;
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data = readl(ecc_reg[i]);
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if (flctl->page_size)
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index = (512 * sector_number) +
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(data >> 16);
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else
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index = data >> 16;
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org = flctl->done_buff[index];
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flctl->done_buff[index] = org ^ (data & 0xFF);
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}
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state = FL_REPAIRABLE;
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writel(0, FL4ECCCR(flctl));
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}
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timeout_error(flctl, __func__);
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return FL_TIMEOUT; /* timeout */
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}
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static void wait_wecfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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uint32_t len;
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while (timeout--) {
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/* check FLECFIFO */
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len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
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if (len >= 4)
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return;
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udelay(1);
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}
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timeout_error(flctl, __func__);
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}
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static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
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int len, enum dma_data_direction dir)
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{
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struct dma_async_tx_descriptor *desc = NULL;
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struct dma_chan *chan;
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enum dma_transfer_direction tr_dir;
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dma_addr_t dma_addr;
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dma_cookie_t cookie = -EINVAL;
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uint32_t reg;
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int ret;
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if (dir == DMA_FROM_DEVICE) {
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chan = flctl->chan_fifo0_rx;
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tr_dir = DMA_DEV_TO_MEM;
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} else {
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chan = flctl->chan_fifo0_tx;
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tr_dir = DMA_MEM_TO_DEV;
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}
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dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
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if (dma_addr)
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desc = dmaengine_prep_slave_single(chan, dma_addr, len,
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tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (desc) {
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reg = readl(FLINTDMACR(flctl));
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reg |= DREQ0EN;
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writel(reg, FLINTDMACR(flctl));
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desc->callback = flctl_dma_complete;
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desc->callback_param = flctl;
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cookie = dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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} else {
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/* DMA failed, fall back to PIO */
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flctl_release_dma(flctl);
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dev_warn(&flctl->pdev->dev,
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"DMA failed, falling back to PIO\n");
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ret = -EIO;
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goto out;
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}
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ret =
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wait_for_completion_timeout(&flctl->dma_complete,
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msecs_to_jiffies(3000));
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if (ret <= 0) {
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dmaengine_terminate_all(chan);
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dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
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}
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out:
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reg = readl(FLINTDMACR(flctl));
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reg &= ~DREQ0EN;
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writel(reg, FLINTDMACR(flctl));
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dma_unmap_single(chan->device->dev, dma_addr, len, dir);
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/* ret > 0 is success */
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return ret;
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}
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static void read_datareg(struct sh_flctl *flctl, int offset)
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{
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unsigned long data;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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wait_completion(flctl);
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data = readl(FLDATAR(flctl));
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*buf = le32_to_cpu(data);
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}
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static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
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{
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int i, len_4align;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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len_4align = (rlen + 3) / 4;
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/* initiate DMA transfer */
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if (flctl->chan_fifo0_rx && rlen >= 32 &&
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flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM) > 0)
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goto convert; /* DMA success */
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/* do polling transfer */
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for (i = 0; i < len_4align; i++) {
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wait_rfifo_ready(flctl);
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buf[i] = readl(FLDTFIFO(flctl));
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}
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convert:
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for (i = 0; i < len_4align; i++)
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buf[i] = be32_to_cpu(buf[i]);
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}
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static enum flctl_ecc_res_t read_ecfiforeg
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(struct sh_flctl *flctl, uint8_t *buff, int sector)
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{
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int i;
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enum flctl_ecc_res_t res;
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unsigned long *ecc_buf = (unsigned long *)buff;
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res = wait_recfifo_ready(flctl , sector);
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if (res != FL_ERROR) {
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for (i = 0; i < 4; i++) {
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ecc_buf[i] = readl(FLECFIFO(flctl));
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ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
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}
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}
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return res;
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}
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static void write_fiforeg(struct sh_flctl *flctl, int rlen,
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unsigned int offset)
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{
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int i, len_4align;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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len_4align = (rlen + 3) / 4;
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for (i = 0; i < len_4align; i++) {
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wait_wfifo_ready(flctl);
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writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
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}
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}
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|
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static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
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unsigned int offset)
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{
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int i, len_4align;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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|
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len_4align = (rlen + 3) / 4;
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for (i = 0; i < len_4align; i++)
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buf[i] = cpu_to_be32(buf[i]);
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|
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/* initiate DMA transfer */
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if (flctl->chan_fifo0_tx && rlen >= 32 &&
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flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV) > 0)
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return; /* DMA success */
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|
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/* do polling transfer */
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for (i = 0; i < len_4align; i++) {
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wait_wecfifo_ready(flctl);
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writel(buf[i], FLECFIFO(flctl));
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}
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}
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|
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static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT;
|
|
uint32_t flcmdcr_val, addr_len_bytes = 0;
|
|
|
|
/* Set SNAND bit if page size is 2048byte */
|
|
if (flctl->page_size)
|
|
flcmncr_val |= SNAND_E;
|
|
else
|
|
flcmncr_val &= ~SNAND_E;
|
|
|
|
/* default FLCMDCR val */
|
|
flcmdcr_val = DOCMD1_E | DOADR_E;
|
|
|
|
/* Set for FLCMDCR */
|
|
switch (cmd) {
|
|
case NAND_CMD_ERASE1:
|
|
addr_len_bytes = flctl->erase_ADRCNT;
|
|
flcmdcr_val |= DOCMD2_E;
|
|
break;
|
|
case NAND_CMD_READ0:
|
|
case NAND_CMD_READOOB:
|
|
case NAND_CMD_RNDOUT:
|
|
addr_len_bytes = flctl->rw_ADRCNT;
|
|
flcmdcr_val |= CDSRC_E;
|
|
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
|
flcmncr_val |= SEL_16BIT;
|
|
break;
|
|
case NAND_CMD_SEQIN:
|
|
/* This case is that cmd is READ0 or READ1 or READ00 */
|
|
flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
|
|
break;
|
|
case NAND_CMD_PAGEPROG:
|
|
addr_len_bytes = flctl->rw_ADRCNT;
|
|
flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
|
|
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
|
flcmncr_val |= SEL_16BIT;
|
|
break;
|
|
case NAND_CMD_READID:
|
|
flcmncr_val &= ~SNAND_E;
|
|
flcmdcr_val |= CDSRC_E;
|
|
addr_len_bytes = ADRCNT_1;
|
|
break;
|
|
case NAND_CMD_STATUS:
|
|
case NAND_CMD_RESET:
|
|
flcmncr_val &= ~SNAND_E;
|
|
flcmdcr_val &= ~(DOADR_E | DOSR_E);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Set address bytes parameter */
|
|
flcmdcr_val |= addr_len_bytes;
|
|
|
|
/* Now actually write */
|
|
writel(flcmncr_val, FLCMNCR(flctl));
|
|
writel(flcmdcr_val, FLCMDCR(flctl));
|
|
writel(flcmcdr_val, FLCMCDR(flctl));
|
|
}
|
|
|
|
static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint8_t *buf, int oob_required, int page)
|
|
{
|
|
chip->read_buf(mtd, buf, mtd->writesize);
|
|
if (oob_required)
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
return 0;
|
|
}
|
|
|
|
static int flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
|
const uint8_t *buf, int oob_required)
|
|
{
|
|
chip->write_buf(mtd, buf, mtd->writesize);
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
return 0;
|
|
}
|
|
|
|
static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int sector, page_sectors;
|
|
enum flctl_ecc_res_t ecc_result;
|
|
|
|
page_sectors = flctl->page_size ? 4 : 1;
|
|
|
|
set_cmd_regs(mtd, NAND_CMD_READ0,
|
|
(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
|
|
|
|
writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
|
|
FLCMNCR(flctl));
|
|
writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
|
|
writel(page_addr << 2, FLADR(flctl));
|
|
|
|
empty_fifo(flctl);
|
|
start_translation(flctl);
|
|
|
|
for (sector = 0; sector < page_sectors; sector++) {
|
|
read_fiforeg(flctl, 512, 512 * sector);
|
|
|
|
ecc_result = read_ecfiforeg(flctl,
|
|
&flctl->done_buff[mtd->writesize + 16 * sector],
|
|
sector);
|
|
|
|
switch (ecc_result) {
|
|
case FL_REPAIRABLE:
|
|
dev_info(&flctl->pdev->dev,
|
|
"applied ecc on page 0x%x", page_addr);
|
|
flctl->mtd.ecc_stats.corrected++;
|
|
break;
|
|
case FL_ERROR:
|
|
dev_warn(&flctl->pdev->dev,
|
|
"page 0x%x contains corrupted data\n",
|
|
page_addr);
|
|
flctl->mtd.ecc_stats.failed++;
|
|
break;
|
|
default:
|
|
;
|
|
}
|
|
}
|
|
|
|
wait_completion(flctl);
|
|
|
|
writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
|
|
FLCMNCR(flctl));
|
|
}
|
|
|
|
static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int page_sectors = flctl->page_size ? 4 : 1;
|
|
int i;
|
|
|
|
set_cmd_regs(mtd, NAND_CMD_READ0,
|
|
(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
|
|
|
|
empty_fifo(flctl);
|
|
|
|
for (i = 0; i < page_sectors; i++) {
|
|
set_addr(mtd, (512 + 16) * i + 512 , page_addr);
|
|
writel(16, FLDTCNTR(flctl));
|
|
|
|
start_translation(flctl);
|
|
read_fiforeg(flctl, 16, 16 * i);
|
|
wait_completion(flctl);
|
|
}
|
|
}
|
|
|
|
static void execmd_write_page_sector(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int page_addr = flctl->seqin_page_addr;
|
|
int sector, page_sectors;
|
|
|
|
page_sectors = flctl->page_size ? 4 : 1;
|
|
|
|
set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
|
|
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
|
|
|
|
empty_fifo(flctl);
|
|
writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
|
|
writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
|
|
writel(page_addr << 2, FLADR(flctl));
|
|
start_translation(flctl);
|
|
|
|
for (sector = 0; sector < page_sectors; sector++) {
|
|
write_fiforeg(flctl, 512, 512 * sector);
|
|
write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector);
|
|
}
|
|
|
|
wait_completion(flctl);
|
|
writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
|
|
}
|
|
|
|
static void execmd_write_oob(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int page_addr = flctl->seqin_page_addr;
|
|
int sector, page_sectors;
|
|
|
|
page_sectors = flctl->page_size ? 4 : 1;
|
|
|
|
set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
|
|
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
|
|
|
|
for (sector = 0; sector < page_sectors; sector++) {
|
|
empty_fifo(flctl);
|
|
set_addr(mtd, sector * 528 + 512, page_addr);
|
|
writel(16, FLDTCNTR(flctl)); /* set read size */
|
|
|
|
start_translation(flctl);
|
|
write_fiforeg(flctl, 16, 16 * sector);
|
|
wait_completion(flctl);
|
|
}
|
|
}
|
|
|
|
static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
|
|
int column, int page_addr)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
uint32_t read_cmd = 0;
|
|
|
|
pm_runtime_get_sync(&flctl->pdev->dev);
|
|
|
|
flctl->read_bytes = 0;
|
|
if (command != NAND_CMD_PAGEPROG)
|
|
flctl->index = 0;
|
|
|
|
switch (command) {
|
|
case NAND_CMD_READ1:
|
|
case NAND_CMD_READ0:
|
|
if (flctl->hwecc) {
|
|
/* read page with hwecc */
|
|
execmd_read_page_sector(mtd, page_addr);
|
|
break;
|
|
}
|
|
if (flctl->page_size)
|
|
set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
|
|
| command);
|
|
else
|
|
set_cmd_regs(mtd, command, command);
|
|
|
|
set_addr(mtd, 0, page_addr);
|
|
|
|
flctl->read_bytes = mtd->writesize + mtd->oobsize;
|
|
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
|
column >>= 1;
|
|
flctl->index += column;
|
|
goto read_normal_exit;
|
|
|
|
case NAND_CMD_READOOB:
|
|
if (flctl->hwecc) {
|
|
/* read page with hwecc */
|
|
execmd_read_oob(mtd, page_addr);
|
|
break;
|
|
}
|
|
|
|
if (flctl->page_size) {
|
|
set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
|
|
| NAND_CMD_READ0);
|
|
set_addr(mtd, mtd->writesize, page_addr);
|
|
} else {
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, 0, page_addr);
|
|
}
|
|
flctl->read_bytes = mtd->oobsize;
|
|
goto read_normal_exit;
|
|
|
|
case NAND_CMD_RNDOUT:
|
|
if (flctl->hwecc)
|
|
break;
|
|
|
|
if (flctl->page_size)
|
|
set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8)
|
|
| command);
|
|
else
|
|
set_cmd_regs(mtd, command, command);
|
|
|
|
set_addr(mtd, column, 0);
|
|
|
|
flctl->read_bytes = mtd->writesize + mtd->oobsize - column;
|
|
goto read_normal_exit;
|
|
|
|
case NAND_CMD_READID:
|
|
set_cmd_regs(mtd, command, command);
|
|
|
|
/* READID is always performed using an 8-bit bus */
|
|
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
|
column <<= 1;
|
|
set_addr(mtd, column, 0);
|
|
|
|
flctl->read_bytes = 8;
|
|
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
|
|
empty_fifo(flctl);
|
|
start_translation(flctl);
|
|
read_fiforeg(flctl, flctl->read_bytes, 0);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
case NAND_CMD_ERASE1:
|
|
flctl->erase1_page_addr = page_addr;
|
|
break;
|
|
|
|
case NAND_CMD_ERASE2:
|
|
set_cmd_regs(mtd, NAND_CMD_ERASE1,
|
|
(command << 8) | NAND_CMD_ERASE1);
|
|
set_addr(mtd, -1, flctl->erase1_page_addr);
|
|
start_translation(flctl);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
case NAND_CMD_SEQIN:
|
|
if (!flctl->page_size) {
|
|
/* output read command */
|
|
if (column >= mtd->writesize) {
|
|
column -= mtd->writesize;
|
|
read_cmd = NAND_CMD_READOOB;
|
|
} else if (column < 256) {
|
|
read_cmd = NAND_CMD_READ0;
|
|
} else {
|
|
column -= 256;
|
|
read_cmd = NAND_CMD_READ1;
|
|
}
|
|
}
|
|
flctl->seqin_column = column;
|
|
flctl->seqin_page_addr = page_addr;
|
|
flctl->seqin_read_cmd = read_cmd;
|
|
break;
|
|
|
|
case NAND_CMD_PAGEPROG:
|
|
empty_fifo(flctl);
|
|
if (!flctl->page_size) {
|
|
set_cmd_regs(mtd, NAND_CMD_SEQIN,
|
|
flctl->seqin_read_cmd);
|
|
set_addr(mtd, -1, -1);
|
|
writel(0, FLDTCNTR(flctl)); /* set 0 size */
|
|
start_translation(flctl);
|
|
wait_completion(flctl);
|
|
}
|
|
if (flctl->hwecc) {
|
|
/* write page with hwecc */
|
|
if (flctl->seqin_column == mtd->writesize)
|
|
execmd_write_oob(mtd);
|
|
else if (!flctl->seqin_column)
|
|
execmd_write_page_sector(mtd);
|
|
else
|
|
printk(KERN_ERR "Invalid address !?\n");
|
|
break;
|
|
}
|
|
set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
|
|
set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
|
|
writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
|
|
start_translation(flctl);
|
|
write_fiforeg(flctl, flctl->index, 0);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
case NAND_CMD_STATUS:
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, -1, -1);
|
|
|
|
flctl->read_bytes = 1;
|
|
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
|
|
start_translation(flctl);
|
|
read_datareg(flctl, 0); /* read and end */
|
|
break;
|
|
|
|
case NAND_CMD_RESET:
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, -1, -1);
|
|
|
|
writel(0, FLDTCNTR(flctl)); /* set 0 size */
|
|
start_translation(flctl);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
goto runtime_exit;
|
|
|
|
read_normal_exit:
|
|
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
|
|
empty_fifo(flctl);
|
|
start_translation(flctl);
|
|
read_fiforeg(flctl, flctl->read_bytes, 0);
|
|
wait_completion(flctl);
|
|
runtime_exit:
|
|
pm_runtime_put_sync(&flctl->pdev->dev);
|
|
return;
|
|
}
|
|
|
|
static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int ret;
|
|
|
|
switch (chipnr) {
|
|
case -1:
|
|
flctl->flcmncr_base &= ~CE0_ENABLE;
|
|
|
|
pm_runtime_get_sync(&flctl->pdev->dev);
|
|
writel(flctl->flcmncr_base, FLCMNCR(flctl));
|
|
|
|
if (flctl->qos_request) {
|
|
dev_pm_qos_remove_request(&flctl->pm_qos);
|
|
flctl->qos_request = 0;
|
|
}
|
|
|
|
pm_runtime_put_sync(&flctl->pdev->dev);
|
|
break;
|
|
case 0:
|
|
flctl->flcmncr_base |= CE0_ENABLE;
|
|
|
|
if (!flctl->qos_request) {
|
|
ret = dev_pm_qos_add_request(&flctl->pdev->dev,
|
|
&flctl->pm_qos,
|
|
DEV_PM_QOS_RESUME_LATENCY,
|
|
100);
|
|
if (ret < 0)
|
|
dev_err(&flctl->pdev->dev,
|
|
"PM QoS request failed: %d\n", ret);
|
|
flctl->qos_request = 1;
|
|
}
|
|
|
|
if (flctl->holden) {
|
|
pm_runtime_get_sync(&flctl->pdev->dev);
|
|
writel(HOLDEN, FLHOLDCR(flctl));
|
|
pm_runtime_put_sync(&flctl->pdev->dev);
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
|
|
memcpy(&flctl->done_buff[flctl->index], buf, len);
|
|
flctl->index += len;
|
|
}
|
|
|
|
static uint8_t flctl_read_byte(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
uint8_t data;
|
|
|
|
data = flctl->done_buff[flctl->index];
|
|
flctl->index++;
|
|
return data;
|
|
}
|
|
|
|
static uint16_t flctl_read_word(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
uint16_t *buf = (uint16_t *)&flctl->done_buff[flctl->index];
|
|
|
|
flctl->index += 2;
|
|
return *buf;
|
|
}
|
|
|
|
static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
|
|
memcpy(buf, &flctl->done_buff[flctl->index], len);
|
|
flctl->index += len;
|
|
}
|
|
|
|
static int flctl_chip_init_tail(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
struct nand_chip *chip = &flctl->chip;
|
|
|
|
if (mtd->writesize == 512) {
|
|
flctl->page_size = 0;
|
|
if (chip->chipsize > (32 << 20)) {
|
|
/* big than 32MB */
|
|
flctl->rw_ADRCNT = ADRCNT_4;
|
|
flctl->erase_ADRCNT = ADRCNT_3;
|
|
} else if (chip->chipsize > (2 << 16)) {
|
|
/* big than 128KB */
|
|
flctl->rw_ADRCNT = ADRCNT_3;
|
|
flctl->erase_ADRCNT = ADRCNT_2;
|
|
} else {
|
|
flctl->rw_ADRCNT = ADRCNT_2;
|
|
flctl->erase_ADRCNT = ADRCNT_1;
|
|
}
|
|
} else {
|
|
flctl->page_size = 1;
|
|
if (chip->chipsize > (128 << 20)) {
|
|
/* big than 128MB */
|
|
flctl->rw_ADRCNT = ADRCNT2_E;
|
|
flctl->erase_ADRCNT = ADRCNT_3;
|
|
} else if (chip->chipsize > (8 << 16)) {
|
|
/* big than 512KB */
|
|
flctl->rw_ADRCNT = ADRCNT_4;
|
|
flctl->erase_ADRCNT = ADRCNT_2;
|
|
} else {
|
|
flctl->rw_ADRCNT = ADRCNT_3;
|
|
flctl->erase_ADRCNT = ADRCNT_1;
|
|
}
|
|
}
|
|
|
|
if (flctl->hwecc) {
|
|
if (mtd->writesize == 512) {
|
|
chip->ecc.layout = &flctl_4secc_oob_16;
|
|
chip->badblock_pattern = &flctl_4secc_smallpage;
|
|
} else {
|
|
chip->ecc.layout = &flctl_4secc_oob_64;
|
|
chip->badblock_pattern = &flctl_4secc_largepage;
|
|
}
|
|
|
|
chip->ecc.size = 512;
|
|
chip->ecc.bytes = 10;
|
|
chip->ecc.strength = 4;
|
|
chip->ecc.read_page = flctl_read_page_hwecc;
|
|
chip->ecc.write_page = flctl_write_page_hwecc;
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
|
|
/* 4 symbols ECC enabled */
|
|
flctl->flcmncr_base |= _4ECCEN;
|
|
} else {
|
|
chip->ecc.mode = NAND_ECC_SOFT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
|
|
{
|
|
struct sh_flctl *flctl = dev_id;
|
|
|
|
dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl)));
|
|
writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
struct flctl_soc_config {
|
|
unsigned long flcmncr_val;
|
|
unsigned has_hwecc:1;
|
|
unsigned use_holden:1;
|
|
};
|
|
|
|
static struct flctl_soc_config flctl_sh7372_config = {
|
|
.flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
|
|
.has_hwecc = 1,
|
|
.use_holden = 1,
|
|
};
|
|
|
|
static const struct of_device_id of_flctl_match[] = {
|
|
{ .compatible = "renesas,shmobile-flctl-sh7372",
|
|
.data = &flctl_sh7372_config },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_flctl_match);
|
|
|
|
static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct flctl_soc_config *config;
|
|
struct sh_flctl_platform_data *pdata;
|
|
struct device_node *dn = dev->of_node;
|
|
int ret;
|
|
|
|
match = of_match_device(of_flctl_match, dev);
|
|
if (match)
|
|
config = (struct flctl_soc_config *)match->data;
|
|
else {
|
|
dev_err(dev, "%s: no OF configuration attached\n", __func__);
|
|
return NULL;
|
|
}
|
|
|
|
pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
|
|
GFP_KERNEL);
|
|
if (!pdata)
|
|
return NULL;
|
|
|
|
/* set SoC specific options */
|
|
pdata->flcmncr_val = config->flcmncr_val;
|
|
pdata->has_hwecc = config->has_hwecc;
|
|
pdata->use_holden = config->use_holden;
|
|
|
|
/* parse user defined options */
|
|
ret = of_get_nand_bus_width(dn);
|
|
if (ret == 16)
|
|
pdata->flcmncr_val |= SEL_16BIT;
|
|
else if (ret != 8) {
|
|
dev_err(dev, "%s: invalid bus width\n", __func__);
|
|
return NULL;
|
|
}
|
|
|
|
return pdata;
|
|
}
|
|
|
|
static int flctl_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct sh_flctl *flctl;
|
|
struct mtd_info *flctl_mtd;
|
|
struct nand_chip *nand;
|
|
struct sh_flctl_platform_data *pdata;
|
|
int ret;
|
|
int irq;
|
|
struct mtd_part_parser_data ppdata = {};
|
|
|
|
flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
|
|
if (!flctl)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
flctl->reg = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(flctl->reg))
|
|
return PTR_ERR(flctl->reg);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "failed to get flste irq data\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED,
|
|
"flste", flctl);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "request interrupt failed.\n");
|
|
return ret;
|
|
}
|
|
|
|
if (pdev->dev.of_node)
|
|
pdata = flctl_parse_dt(&pdev->dev);
|
|
else
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "no setup data defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, flctl);
|
|
flctl_mtd = &flctl->mtd;
|
|
nand = &flctl->chip;
|
|
flctl_mtd->priv = nand;
|
|
flctl->pdev = pdev;
|
|
flctl->hwecc = pdata->has_hwecc;
|
|
flctl->holden = pdata->use_holden;
|
|
flctl->flcmncr_base = pdata->flcmncr_val;
|
|
flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
|
|
|
|
/* Set address of hardware control function */
|
|
/* 20 us command delay time */
|
|
nand->chip_delay = 20;
|
|
|
|
nand->read_byte = flctl_read_byte;
|
|
nand->write_buf = flctl_write_buf;
|
|
nand->read_buf = flctl_read_buf;
|
|
nand->select_chip = flctl_select_chip;
|
|
nand->cmdfunc = flctl_cmdfunc;
|
|
|
|
if (pdata->flcmncr_val & SEL_16BIT) {
|
|
nand->options |= NAND_BUSWIDTH_16;
|
|
nand->read_word = flctl_read_word;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_resume(&pdev->dev);
|
|
|
|
flctl_setup_dma(flctl);
|
|
|
|
ret = nand_scan_ident(flctl_mtd, 1, NULL);
|
|
if (ret)
|
|
goto err_chip;
|
|
|
|
ret = flctl_chip_init_tail(flctl_mtd);
|
|
if (ret)
|
|
goto err_chip;
|
|
|
|
ret = nand_scan_tail(flctl_mtd);
|
|
if (ret)
|
|
goto err_chip;
|
|
|
|
ppdata.of_node = pdev->dev.of_node;
|
|
ret = mtd_device_parse_register(flctl_mtd, NULL, &ppdata, pdata->parts,
|
|
pdata->nr_parts);
|
|
|
|
return 0;
|
|
|
|
err_chip:
|
|
flctl_release_dma(flctl);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return ret;
|
|
}
|
|
|
|
static int flctl_remove(struct platform_device *pdev)
|
|
{
|
|
struct sh_flctl *flctl = platform_get_drvdata(pdev);
|
|
|
|
flctl_release_dma(flctl);
|
|
nand_release(&flctl->mtd);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver flctl_driver = {
|
|
.remove = flctl_remove,
|
|
.driver = {
|
|
.name = "sh_flctl",
|
|
.of_match_table = of_match_ptr(of_flctl_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(flctl_driver, flctl_probe);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Yoshihiro Shimoda");
|
|
MODULE_DESCRIPTION("SuperH FLCTL driver");
|
|
MODULE_ALIAS("platform:sh_flctl");
|