mirror of https://gitee.com/openkylin/linux.git
1501 lines
36 KiB
C
1501 lines
36 KiB
C
/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
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*
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* Derived from:
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* https://github.com/yuq/sunxi-nfc-mtd
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* Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
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*
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* https://github.com/hno/Allwinner-Info
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* Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
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*
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* Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
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* Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_mtd.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#define NFC_REG_CTL 0x0000
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#define NFC_REG_ST 0x0004
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#define NFC_REG_INT 0x0008
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#define NFC_REG_TIMING_CTL 0x000C
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#define NFC_REG_TIMING_CFG 0x0010
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#define NFC_REG_ADDR_LOW 0x0014
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#define NFC_REG_ADDR_HIGH 0x0018
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#define NFC_REG_SECTOR_NUM 0x001C
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#define NFC_REG_CNT 0x0020
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#define NFC_REG_CMD 0x0024
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#define NFC_REG_RCMD_SET 0x0028
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#define NFC_REG_WCMD_SET 0x002C
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#define NFC_REG_IO_DATA 0x0030
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#define NFC_REG_ECC_CTL 0x0034
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#define NFC_REG_ECC_ST 0x0038
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#define NFC_REG_DEBUG 0x003C
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#define NFC_REG_ECC_CNT0 0x0040
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#define NFC_REG_ECC_CNT1 0x0044
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#define NFC_REG_ECC_CNT2 0x0048
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#define NFC_REG_ECC_CNT3 0x004c
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#define NFC_REG_USER_DATA_BASE 0x0050
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#define NFC_REG_SPARE_AREA 0x00A0
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#define NFC_RAM0_BASE 0x0400
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#define NFC_RAM1_BASE 0x0800
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/* define bit use in NFC_CTL */
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#define NFC_EN BIT(0)
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#define NFC_RESET BIT(1)
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#define NFC_BUS_WIDYH BIT(2)
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#define NFC_RB_SEL BIT(3)
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#define NFC_CE_SEL GENMASK(26, 24)
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#define NFC_CE_CTL BIT(6)
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#define NFC_CE_CTL1 BIT(7)
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#define NFC_PAGE_SIZE GENMASK(11, 8)
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#define NFC_SAM BIT(12)
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#define NFC_RAM_METHOD BIT(14)
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#define NFC_DEBUG_CTL BIT(31)
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/* define bit use in NFC_ST */
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#define NFC_RB_B2R BIT(0)
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#define NFC_CMD_INT_FLAG BIT(1)
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#define NFC_DMA_INT_FLAG BIT(2)
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#define NFC_CMD_FIFO_STATUS BIT(3)
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#define NFC_STA BIT(4)
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#define NFC_NATCH_INT_FLAG BIT(5)
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#define NFC_RB_STATE0 BIT(8)
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#define NFC_RB_STATE1 BIT(9)
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#define NFC_RB_STATE2 BIT(10)
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#define NFC_RB_STATE3 BIT(11)
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/* define bit use in NFC_INT */
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#define NFC_B2R_INT_ENABLE BIT(0)
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#define NFC_CMD_INT_ENABLE BIT(1)
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#define NFC_DMA_INT_ENABLE BIT(2)
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#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
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NFC_CMD_INT_ENABLE | \
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NFC_DMA_INT_ENABLE)
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/* define bit use in NFC_TIMING_CTL */
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#define NFC_TIMING_CTL_EDO BIT(8)
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/* define NFC_TIMING_CFG register layout */
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#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
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(((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
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(((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
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(((tCAD) & 0x7) << 8))
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/* define bit use in NFC_CMD */
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#define NFC_CMD_LOW_BYTE GENMASK(7, 0)
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#define NFC_CMD_HIGH_BYTE GENMASK(15, 8)
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#define NFC_ADR_NUM GENMASK(18, 16)
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#define NFC_SEND_ADR BIT(19)
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#define NFC_ACCESS_DIR BIT(20)
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#define NFC_DATA_TRANS BIT(21)
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#define NFC_SEND_CMD1 BIT(22)
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#define NFC_WAIT_FLAG BIT(23)
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#define NFC_SEND_CMD2 BIT(24)
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#define NFC_SEQ BIT(25)
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#define NFC_DATA_SWAP_METHOD BIT(26)
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#define NFC_ROW_AUTO_INC BIT(27)
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#define NFC_SEND_CMD3 BIT(28)
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#define NFC_SEND_CMD4 BIT(29)
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#define NFC_CMD_TYPE GENMASK(31, 30)
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/* define bit use in NFC_RCMD_SET */
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#define NFC_READ_CMD GENMASK(7, 0)
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#define NFC_RANDOM_READ_CMD0 GENMASK(15, 8)
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#define NFC_RANDOM_READ_CMD1 GENMASK(23, 16)
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/* define bit use in NFC_WCMD_SET */
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#define NFC_PROGRAM_CMD GENMASK(7, 0)
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#define NFC_RANDOM_WRITE_CMD GENMASK(15, 8)
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#define NFC_READ_CMD0 GENMASK(23, 16)
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#define NFC_READ_CMD1 GENMASK(31, 24)
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/* define bit use in NFC_ECC_CTL */
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#define NFC_ECC_EN BIT(0)
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#define NFC_ECC_PIPELINE BIT(3)
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#define NFC_ECC_EXCEPTION BIT(4)
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#define NFC_ECC_BLOCK_SIZE BIT(5)
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#define NFC_RANDOM_EN BIT(9)
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#define NFC_RANDOM_DIRECTION BIT(10)
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#define NFC_ECC_MODE_SHIFT 12
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#define NFC_ECC_MODE GENMASK(15, 12)
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#define NFC_RANDOM_SEED GENMASK(30, 16)
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#define NFC_DEFAULT_TIMEOUT_MS 1000
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#define NFC_SRAM_SIZE 1024
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#define NFC_MAX_CS 7
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/*
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* Ready/Busy detection type: describes the Ready/Busy detection modes
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*
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* @RB_NONE: no external detection available, rely on STATUS command
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* and software timeouts
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* @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
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* pin of the NAND flash chip must be connected to one of the
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* native NAND R/B pins (those which can be muxed to the NAND
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* Controller)
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* @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
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* pin of the NAND flash chip must be connected to a GPIO capable
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* pin.
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*/
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enum sunxi_nand_rb_type {
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RB_NONE,
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RB_NATIVE,
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RB_GPIO,
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};
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/*
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* Ready/Busy structure: stores information related to Ready/Busy detection
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*
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* @type: the Ready/Busy detection mode
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* @info: information related to the R/B detection mode. Either a gpio
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* id or a native R/B id (those supported by the NAND controller).
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*/
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struct sunxi_nand_rb {
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enum sunxi_nand_rb_type type;
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union {
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int gpio;
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int nativeid;
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} info;
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};
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/*
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* Chip Select structure: stores information related to NAND Chip Select
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*
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* @cs: the NAND CS id used to communicate with a NAND Chip
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* @rb: the Ready/Busy description
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*/
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struct sunxi_nand_chip_sel {
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u8 cs;
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struct sunxi_nand_rb rb;
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};
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/*
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* sunxi HW ECC infos: stores information related to HW ECC support
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*
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* @mode: the sunxi ECC mode field deduced from ECC requirements
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* @layout: the OOB layout depending on the ECC requirements and the
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* selected ECC mode
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*/
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struct sunxi_nand_hw_ecc {
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int mode;
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struct nand_ecclayout layout;
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};
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/*
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* NAND chip structure: stores NAND chip device related information
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*
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* @node: used to store NAND chips into a list
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* @nand: base NAND chip structure
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* @mtd: base MTD structure
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* @clk_rate: clk_rate required for this NAND chip
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* @timing_cfg TIMING_CFG register value for this NAND chip
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* @selected: current active CS
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* @nsels: number of CS lines required by the NAND chip
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* @sels: array of CS lines descriptions
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*/
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struct sunxi_nand_chip {
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struct list_head node;
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struct nand_chip nand;
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struct mtd_info mtd;
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unsigned long clk_rate;
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u32 timing_cfg;
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u32 timing_ctl;
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int selected;
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int nsels;
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struct sunxi_nand_chip_sel sels[0];
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};
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static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
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{
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return container_of(nand, struct sunxi_nand_chip, nand);
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}
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/*
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* NAND Controller structure: stores sunxi NAND controller information
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*
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* @controller: base controller structure
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* @dev: parent device (used to print error messages)
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* @regs: NAND controller registers
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* @ahb_clk: NAND Controller AHB clock
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* @mod_clk: NAND Controller mod clock
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* @assigned_cs: bitmask describing already assigned CS lines
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* @clk_rate: NAND controller current clock rate
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* @chips: a list containing all the NAND chips attached to
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* this NAND controller
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* @complete: a completion object used to wait for NAND
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* controller events
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*/
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struct sunxi_nfc {
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struct nand_hw_control controller;
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struct device *dev;
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void __iomem *regs;
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struct clk *ahb_clk;
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struct clk *mod_clk;
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unsigned long assigned_cs;
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unsigned long clk_rate;
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struct list_head chips;
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struct completion complete;
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};
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static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
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{
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return container_of(ctrl, struct sunxi_nfc, controller);
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}
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static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
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{
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struct sunxi_nfc *nfc = dev_id;
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u32 st = readl(nfc->regs + NFC_REG_ST);
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u32 ien = readl(nfc->regs + NFC_REG_INT);
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if (!(ien & st))
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return IRQ_NONE;
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if ((ien & st) == ien)
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complete(&nfc->complete);
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writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
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writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
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return IRQ_HANDLED;
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}
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static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
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unsigned int timeout_ms)
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{
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init_completion(&nfc->complete);
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writel(flags, nfc->regs + NFC_REG_INT);
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if (!timeout_ms)
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timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
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if (!wait_for_completion_timeout(&nfc->complete,
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msecs_to_jiffies(timeout_ms))) {
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dev_err(nfc->dev, "wait interrupt timedout\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
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{
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unsigned long timeout = jiffies +
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msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
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do {
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if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
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return 0;
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} while (time_before(jiffies, timeout));
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dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
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return -ETIMEDOUT;
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}
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static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
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{
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unsigned long timeout = jiffies +
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msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
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writel(0, nfc->regs + NFC_REG_ECC_CTL);
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writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
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do {
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if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
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return 0;
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} while (time_before(jiffies, timeout));
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dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
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return -ETIMEDOUT;
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}
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static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *nand = mtd->priv;
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struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
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struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
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struct sunxi_nand_rb *rb;
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unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
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int ret;
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if (sunxi_nand->selected < 0)
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return 0;
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rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
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switch (rb->type) {
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case RB_NATIVE:
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ret = !!(readl(nfc->regs + NFC_REG_ST) &
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(NFC_RB_STATE0 << rb->info.nativeid));
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if (ret)
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break;
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sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
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ret = !!(readl(nfc->regs + NFC_REG_ST) &
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(NFC_RB_STATE0 << rb->info.nativeid));
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break;
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case RB_GPIO:
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ret = gpio_get_value(rb->info.gpio);
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break;
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case RB_NONE:
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default:
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ret = 0;
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dev_err(nfc->dev, "cannot check R/B NAND status!\n");
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break;
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}
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return ret;
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}
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static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
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{
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struct nand_chip *nand = mtd->priv;
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struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
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struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
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struct sunxi_nand_chip_sel *sel;
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u32 ctl;
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if (chip > 0 && chip >= sunxi_nand->nsels)
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return;
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if (chip == sunxi_nand->selected)
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return;
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ctl = readl(nfc->regs + NFC_REG_CTL) &
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~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
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if (chip >= 0) {
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sel = &sunxi_nand->sels[chip];
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ctl |= (sel->cs << 24) | NFC_EN |
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(((nand->page_shift - 10) & 0xf) << 8);
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if (sel->rb.type == RB_NONE) {
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nand->dev_ready = NULL;
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} else {
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nand->dev_ready = sunxi_nfc_dev_ready;
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if (sel->rb.type == RB_NATIVE)
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ctl |= (sel->rb.info.nativeid << 3);
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}
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writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
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if (nfc->clk_rate != sunxi_nand->clk_rate) {
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clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
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nfc->clk_rate = sunxi_nand->clk_rate;
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}
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}
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writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
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writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
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writel(ctl, nfc->regs + NFC_REG_CTL);
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sunxi_nand->selected = chip;
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}
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static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct nand_chip *nand = mtd->priv;
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struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
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struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
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int ret;
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int cnt;
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int offs = 0;
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u32 tmp;
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while (len > offs) {
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cnt = min(len - offs, NFC_SRAM_SIZE);
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ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
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if (ret)
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break;
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writel(cnt, nfc->regs + NFC_REG_CNT);
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tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
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writel(tmp, nfc->regs + NFC_REG_CMD);
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ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
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if (ret)
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break;
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if (buf)
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memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
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cnt);
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offs += cnt;
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}
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}
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static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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struct nand_chip *nand = mtd->priv;
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struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
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struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
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int ret;
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int cnt;
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int offs = 0;
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u32 tmp;
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while (len > offs) {
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cnt = min(len - offs, NFC_SRAM_SIZE);
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ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
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if (ret)
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break;
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|
|
writel(cnt, nfc->regs + NFC_REG_CNT);
|
|
memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
|
|
tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
|
|
NFC_ACCESS_DIR;
|
|
writel(tmp, nfc->regs + NFC_REG_CMD);
|
|
|
|
ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
|
|
if (ret)
|
|
break;
|
|
|
|
offs += cnt;
|
|
}
|
|
}
|
|
|
|
static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
|
|
{
|
|
uint8_t ret;
|
|
|
|
sunxi_nfc_read_buf(mtd, &ret, 1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
|
|
unsigned int ctrl)
|
|
{
|
|
struct nand_chip *nand = mtd->priv;
|
|
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
|
|
int ret;
|
|
u32 tmp;
|
|
|
|
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
|
|
if (ret)
|
|
return;
|
|
|
|
if (ctrl & NAND_CTRL_CHANGE) {
|
|
tmp = readl(nfc->regs + NFC_REG_CTL);
|
|
if (ctrl & NAND_NCE)
|
|
tmp |= NFC_CE_CTL;
|
|
else
|
|
tmp &= ~NFC_CE_CTL;
|
|
writel(tmp, nfc->regs + NFC_REG_CTL);
|
|
}
|
|
|
|
if (dat == NAND_CMD_NONE)
|
|
return;
|
|
|
|
if (ctrl & NAND_CLE) {
|
|
writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
|
|
} else {
|
|
writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
|
|
writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
|
|
}
|
|
|
|
sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
|
|
}
|
|
|
|
static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf,
|
|
int oob_required, int page)
|
|
{
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
struct nand_ecclayout *layout = ecc->layout;
|
|
struct sunxi_nand_hw_ecc *data = ecc->priv;
|
|
unsigned int max_bitflips = 0;
|
|
int offset;
|
|
int ret;
|
|
u32 tmp;
|
|
int i;
|
|
int cnt;
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
|
|
tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
|
|
NFC_ECC_EXCEPTION;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
if (i)
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1);
|
|
|
|
offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
|
|
|
|
chip->read_buf(mtd, NULL, ecc->size);
|
|
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
|
|
|
|
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
|
|
writel(tmp, nfc->regs + NFC_REG_CMD);
|
|
|
|
ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
memcpy_fromio(buf + (i * ecc->size),
|
|
nfc->regs + NFC_RAM0_BASE, ecc->size);
|
|
|
|
if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
|
|
mtd->ecc_stats.failed++;
|
|
} else {
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
|
|
mtd->ecc_stats.corrected += tmp;
|
|
max_bitflips = max_t(unsigned int, max_bitflips, tmp);
|
|
}
|
|
|
|
if (oob_required) {
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
|
|
|
|
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
offset -= mtd->writesize;
|
|
chip->read_buf(mtd, chip->oob_poi + offset,
|
|
ecc->bytes + 4);
|
|
}
|
|
}
|
|
|
|
if (oob_required) {
|
|
cnt = ecc->layout->oobfree[ecc->steps].length;
|
|
if (cnt > 0) {
|
|
offset = mtd->writesize +
|
|
ecc->layout->oobfree[ecc->steps].offset;
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
|
|
offset -= mtd->writesize;
|
|
chip->read_buf(mtd, chip->oob_poi + offset, cnt);
|
|
}
|
|
}
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~NFC_ECC_EN;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
return max_bitflips;
|
|
}
|
|
|
|
static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
const uint8_t *buf, int oob_required)
|
|
{
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
struct nand_ecclayout *layout = ecc->layout;
|
|
struct sunxi_nand_hw_ecc *data = ecc->priv;
|
|
int offset;
|
|
int ret;
|
|
u32 tmp;
|
|
int i;
|
|
int cnt;
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
|
|
tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
|
|
NFC_ECC_EXCEPTION;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
if (i)
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1);
|
|
|
|
chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
|
|
|
|
offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize;
|
|
|
|
/* Fill OOB data in */
|
|
if (oob_required) {
|
|
tmp = 0xffffffff;
|
|
memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, &tmp,
|
|
4);
|
|
} else {
|
|
memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE,
|
|
chip->oob_poi + offset - mtd->writesize,
|
|
4);
|
|
}
|
|
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
|
|
|
|
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
|
|
(1 << 30);
|
|
writel(tmp, nfc->regs + NFC_REG_CMD);
|
|
ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (oob_required) {
|
|
cnt = ecc->layout->oobfree[i].length;
|
|
if (cnt > 0) {
|
|
offset = mtd->writesize +
|
|
ecc->layout->oobfree[i].offset;
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
|
|
offset -= mtd->writesize;
|
|
chip->write_buf(mtd, chip->oob_poi + offset, cnt);
|
|
}
|
|
}
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~NFC_ECC_EN;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
uint8_t *buf, int oob_required,
|
|
int page)
|
|
{
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
struct sunxi_nand_hw_ecc *data = ecc->priv;
|
|
unsigned int max_bitflips = 0;
|
|
uint8_t *oob = chip->oob_poi;
|
|
int offset = 0;
|
|
int ret;
|
|
int cnt;
|
|
u32 tmp;
|
|
int i;
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
|
|
tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
|
|
NFC_ECC_EXCEPTION;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
chip->read_buf(mtd, NULL, ecc->size);
|
|
|
|
tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
|
|
writel(tmp, nfc->regs + NFC_REG_CMD);
|
|
|
|
ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size);
|
|
buf += ecc->size;
|
|
offset += ecc->size;
|
|
|
|
if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
|
|
mtd->ecc_stats.failed++;
|
|
} else {
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
|
|
mtd->ecc_stats.corrected += tmp;
|
|
max_bitflips = max_t(unsigned int, max_bitflips, tmp);
|
|
}
|
|
|
|
if (oob_required) {
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
|
|
chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad);
|
|
oob += ecc->bytes + ecc->prepad;
|
|
}
|
|
|
|
offset += ecc->bytes + ecc->prepad;
|
|
}
|
|
|
|
if (oob_required) {
|
|
cnt = mtd->oobsize - (oob - chip->oob_poi);
|
|
if (cnt > 0) {
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
|
|
chip->read_buf(mtd, oob, cnt);
|
|
}
|
|
}
|
|
|
|
writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
|
|
nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
return max_bitflips;
|
|
}
|
|
|
|
static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
const uint8_t *buf,
|
|
int oob_required)
|
|
{
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
struct sunxi_nand_hw_ecc *data = ecc->priv;
|
|
uint8_t *oob = chip->oob_poi;
|
|
int offset = 0;
|
|
int ret;
|
|
int cnt;
|
|
u32 tmp;
|
|
int i;
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
|
|
tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
|
|
NFC_ECC_EXCEPTION;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
|
|
offset += ecc->size;
|
|
|
|
/* Fill OOB data in */
|
|
if (oob_required) {
|
|
tmp = 0xffffffff;
|
|
memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, &tmp,
|
|
4);
|
|
} else {
|
|
memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, oob,
|
|
4);
|
|
}
|
|
|
|
tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
|
|
(1 << 30);
|
|
writel(tmp, nfc->regs + NFC_REG_CMD);
|
|
|
|
ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
offset += ecc->bytes + ecc->prepad;
|
|
oob += ecc->bytes + ecc->prepad;
|
|
}
|
|
|
|
if (oob_required) {
|
|
cnt = mtd->oobsize - (oob - chip->oob_poi);
|
|
if (cnt > 0) {
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
|
|
chip->write_buf(mtd, oob, cnt);
|
|
}
|
|
}
|
|
|
|
tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
|
|
tmp &= ~NFC_ECC_EN;
|
|
|
|
writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const s32 tWB_lut[] = {6, 12, 16, 20};
|
|
static const s32 tRHW_lut[] = {4, 8, 12, 20};
|
|
|
|
static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
|
|
u32 clk_period)
|
|
{
|
|
u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
|
|
int i;
|
|
|
|
for (i = 0; i < lut_size; i++) {
|
|
if (clk_cycles <= lut[i])
|
|
return i;
|
|
}
|
|
|
|
/* Doesn't fit */
|
|
return -EINVAL;
|
|
}
|
|
|
|
#define sunxi_nand_lookup_timing(l, p, c) \
|
|
_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
|
|
|
|
static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
|
|
const struct nand_sdr_timings *timings)
|
|
{
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
|
|
u32 min_clk_period = 0;
|
|
s32 tWB, tADL, tWHR, tRHW, tCAD;
|
|
|
|
/* T1 <=> tCLS */
|
|
if (timings->tCLS_min > min_clk_period)
|
|
min_clk_period = timings->tCLS_min;
|
|
|
|
/* T2 <=> tCLH */
|
|
if (timings->tCLH_min > min_clk_period)
|
|
min_clk_period = timings->tCLH_min;
|
|
|
|
/* T3 <=> tCS */
|
|
if (timings->tCS_min > min_clk_period)
|
|
min_clk_period = timings->tCS_min;
|
|
|
|
/* T4 <=> tCH */
|
|
if (timings->tCH_min > min_clk_period)
|
|
min_clk_period = timings->tCH_min;
|
|
|
|
/* T5 <=> tWP */
|
|
if (timings->tWP_min > min_clk_period)
|
|
min_clk_period = timings->tWP_min;
|
|
|
|
/* T6 <=> tWH */
|
|
if (timings->tWH_min > min_clk_period)
|
|
min_clk_period = timings->tWH_min;
|
|
|
|
/* T7 <=> tALS */
|
|
if (timings->tALS_min > min_clk_period)
|
|
min_clk_period = timings->tALS_min;
|
|
|
|
/* T8 <=> tDS */
|
|
if (timings->tDS_min > min_clk_period)
|
|
min_clk_period = timings->tDS_min;
|
|
|
|
/* T9 <=> tDH */
|
|
if (timings->tDH_min > min_clk_period)
|
|
min_clk_period = timings->tDH_min;
|
|
|
|
/* T10 <=> tRR */
|
|
if (timings->tRR_min > (min_clk_period * 3))
|
|
min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
|
|
|
|
/* T11 <=> tALH */
|
|
if (timings->tALH_min > min_clk_period)
|
|
min_clk_period = timings->tALH_min;
|
|
|
|
/* T12 <=> tRP */
|
|
if (timings->tRP_min > min_clk_period)
|
|
min_clk_period = timings->tRP_min;
|
|
|
|
/* T13 <=> tREH */
|
|
if (timings->tREH_min > min_clk_period)
|
|
min_clk_period = timings->tREH_min;
|
|
|
|
/* T14 <=> tRC */
|
|
if (timings->tRC_min > (min_clk_period * 2))
|
|
min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
|
|
|
|
/* T15 <=> tWC */
|
|
if (timings->tWC_min > (min_clk_period * 2))
|
|
min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
|
|
|
|
/* T16 - T19 + tCAD */
|
|
tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
|
|
min_clk_period);
|
|
if (tWB < 0) {
|
|
dev_err(nfc->dev, "unsupported tWB\n");
|
|
return tWB;
|
|
}
|
|
|
|
tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
|
|
if (tADL > 3) {
|
|
dev_err(nfc->dev, "unsupported tADL\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
|
|
if (tWHR > 3) {
|
|
dev_err(nfc->dev, "unsupported tWHR\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
|
|
min_clk_period);
|
|
if (tRHW < 0) {
|
|
dev_err(nfc->dev, "unsupported tRHW\n");
|
|
return tRHW;
|
|
}
|
|
|
|
/*
|
|
* TODO: according to ONFI specs this value only applies for DDR NAND,
|
|
* but Allwinner seems to set this to 0x7. Mimic them for now.
|
|
*/
|
|
tCAD = 0x7;
|
|
|
|
/* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
|
|
chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
|
|
|
|
/*
|
|
* ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
|
|
* output cycle timings shall be used if the host drives tRC less than
|
|
* 30 ns.
|
|
*/
|
|
chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
|
|
|
|
/* Convert min_clk_period from picoseconds to nanoseconds */
|
|
min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
|
|
|
|
/*
|
|
* Convert min_clk_period into a clk frequency, then get the
|
|
* appropriate rate for the NAND controller IP given this formula
|
|
* (specified in the datasheet):
|
|
* nand clk_rate = 2 * min_clk_rate
|
|
*/
|
|
chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
|
|
struct device_node *np)
|
|
{
|
|
const struct nand_sdr_timings *timings;
|
|
int ret;
|
|
int mode;
|
|
|
|
mode = onfi_get_async_timing_mode(&chip->nand);
|
|
if (mode == ONFI_TIMING_MODE_UNKNOWN) {
|
|
mode = chip->nand.onfi_timing_mode_default;
|
|
} else {
|
|
uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
|
|
|
|
mode = fls(mode) - 1;
|
|
if (mode < 0)
|
|
mode = 0;
|
|
|
|
feature[0] = mode;
|
|
ret = chip->nand.onfi_set_features(&chip->mtd, &chip->nand,
|
|
ONFI_FEATURE_ADDR_TIMING_MODE,
|
|
feature);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
timings = onfi_async_timing_mode_to_sdr_timings(mode);
|
|
if (IS_ERR(timings))
|
|
return PTR_ERR(timings);
|
|
|
|
return sunxi_nand_chip_set_timings(chip, timings);
|
|
}
|
|
|
|
static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
|
|
struct nand_ecc_ctrl *ecc,
|
|
struct device_node *np)
|
|
{
|
|
static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
|
|
struct nand_chip *nand = mtd->priv;
|
|
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
|
|
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
|
|
struct sunxi_nand_hw_ecc *data;
|
|
struct nand_ecclayout *layout;
|
|
int nsectors;
|
|
int ret;
|
|
int i;
|
|
|
|
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
/* Add ECC info retrieval from DT */
|
|
for (i = 0; i < ARRAY_SIZE(strengths); i++) {
|
|
if (ecc->strength <= strengths[i])
|
|
break;
|
|
}
|
|
|
|
if (i >= ARRAY_SIZE(strengths)) {
|
|
dev_err(nfc->dev, "unsupported strength\n");
|
|
ret = -ENOTSUPP;
|
|
goto err;
|
|
}
|
|
|
|
data->mode = i;
|
|
|
|
/* HW ECC always request ECC bytes for 1024 bytes blocks */
|
|
ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
|
|
|
|
/* HW ECC always work with even numbers of ECC bytes */
|
|
ecc->bytes = ALIGN(ecc->bytes, 2);
|
|
|
|
layout = &data->layout;
|
|
nsectors = mtd->writesize / ecc->size;
|
|
|
|
if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
layout->eccbytes = (ecc->bytes * nsectors);
|
|
|
|
ecc->layout = layout;
|
|
ecc->priv = data;
|
|
|
|
return 0;
|
|
|
|
err:
|
|
kfree(data);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
|
|
{
|
|
kfree(ecc->priv);
|
|
}
|
|
|
|
static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
|
|
struct nand_ecc_ctrl *ecc,
|
|
struct device_node *np)
|
|
{
|
|
struct nand_ecclayout *layout;
|
|
int nsectors;
|
|
int i, j;
|
|
int ret;
|
|
|
|
ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ecc->read_page = sunxi_nfc_hw_ecc_read_page;
|
|
ecc->write_page = sunxi_nfc_hw_ecc_write_page;
|
|
layout = ecc->layout;
|
|
nsectors = mtd->writesize / ecc->size;
|
|
|
|
for (i = 0; i < nsectors; i++) {
|
|
if (i) {
|
|
layout->oobfree[i].offset =
|
|
layout->oobfree[i - 1].offset +
|
|
layout->oobfree[i - 1].length +
|
|
ecc->bytes;
|
|
layout->oobfree[i].length = 4;
|
|
} else {
|
|
/*
|
|
* The first 2 bytes are used for BB markers, hence we
|
|
* only have 2 bytes available in the first user data
|
|
* section.
|
|
*/
|
|
layout->oobfree[i].length = 2;
|
|
layout->oobfree[i].offset = 2;
|
|
}
|
|
|
|
for (j = 0; j < ecc->bytes; j++)
|
|
layout->eccpos[(ecc->bytes * i) + j] =
|
|
layout->oobfree[i].offset +
|
|
layout->oobfree[i].length + j;
|
|
}
|
|
|
|
if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
|
|
layout->oobfree[nsectors].offset =
|
|
layout->oobfree[nsectors - 1].offset +
|
|
layout->oobfree[nsectors - 1].length +
|
|
ecc->bytes;
|
|
layout->oobfree[nsectors].length = mtd->oobsize -
|
|
((ecc->bytes + 4) * nsectors);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
|
|
struct nand_ecc_ctrl *ecc,
|
|
struct device_node *np)
|
|
{
|
|
struct nand_ecclayout *layout;
|
|
int nsectors;
|
|
int i;
|
|
int ret;
|
|
|
|
ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ecc->prepad = 4;
|
|
ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
|
|
ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
|
|
|
|
layout = ecc->layout;
|
|
nsectors = mtd->writesize / ecc->size;
|
|
|
|
for (i = 0; i < (ecc->bytes * nsectors); i++)
|
|
layout->eccpos[i] = i;
|
|
|
|
layout->oobfree[0].length = mtd->oobsize - i;
|
|
layout->oobfree[0].offset = i;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
|
|
{
|
|
switch (ecc->mode) {
|
|
case NAND_ECC_HW:
|
|
case NAND_ECC_HW_SYNDROME:
|
|
sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
|
|
break;
|
|
case NAND_ECC_NONE:
|
|
kfree(ecc->layout);
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
|
|
struct device_node *np)
|
|
{
|
|
struct nand_chip *nand = mtd->priv;
|
|
int strength;
|
|
int blk_size;
|
|
int ret;
|
|
|
|
blk_size = of_get_nand_ecc_step_size(np);
|
|
strength = of_get_nand_ecc_strength(np);
|
|
if (blk_size > 0 && strength > 0) {
|
|
ecc->size = blk_size;
|
|
ecc->strength = strength;
|
|
} else {
|
|
ecc->size = nand->ecc_step_ds;
|
|
ecc->strength = nand->ecc_strength_ds;
|
|
}
|
|
|
|
if (!ecc->size || !ecc->strength)
|
|
return -EINVAL;
|
|
|
|
ecc->mode = NAND_ECC_HW;
|
|
|
|
ret = of_get_nand_ecc_mode(np);
|
|
if (ret >= 0)
|
|
ecc->mode = ret;
|
|
|
|
switch (ecc->mode) {
|
|
case NAND_ECC_SOFT_BCH:
|
|
break;
|
|
case NAND_ECC_HW:
|
|
ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
case NAND_ECC_HW_SYNDROME:
|
|
ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
case NAND_ECC_NONE:
|
|
ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
|
|
if (!ecc->layout)
|
|
return -ENOMEM;
|
|
ecc->layout->oobfree[0].length = mtd->oobsize;
|
|
case NAND_ECC_SOFT:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
|
|
struct device_node *np)
|
|
{
|
|
const struct nand_sdr_timings *timings;
|
|
struct sunxi_nand_chip *chip;
|
|
struct mtd_part_parser_data ppdata;
|
|
struct mtd_info *mtd;
|
|
struct nand_chip *nand;
|
|
int nsels;
|
|
int ret;
|
|
int i;
|
|
u32 tmp;
|
|
|
|
if (!of_get_property(np, "reg", &nsels))
|
|
return -EINVAL;
|
|
|
|
nsels /= sizeof(u32);
|
|
if (!nsels) {
|
|
dev_err(dev, "invalid reg property size\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip = devm_kzalloc(dev,
|
|
sizeof(*chip) +
|
|
(nsels * sizeof(struct sunxi_nand_chip_sel)),
|
|
GFP_KERNEL);
|
|
if (!chip) {
|
|
dev_err(dev, "could not allocate chip\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
chip->nsels = nsels;
|
|
chip->selected = -1;
|
|
|
|
for (i = 0; i < nsels; i++) {
|
|
ret = of_property_read_u32_index(np, "reg", i, &tmp);
|
|
if (ret) {
|
|
dev_err(dev, "could not retrieve reg property: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
if (tmp > NFC_MAX_CS) {
|
|
dev_err(dev,
|
|
"invalid reg value: %u (max CS = 7)\n",
|
|
tmp);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
|
|
dev_err(dev, "CS %d already assigned\n", tmp);
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->sels[i].cs = tmp;
|
|
|
|
if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
|
|
tmp < 2) {
|
|
chip->sels[i].rb.type = RB_NATIVE;
|
|
chip->sels[i].rb.info.nativeid = tmp;
|
|
} else {
|
|
ret = of_get_named_gpio(np, "rb-gpios", i);
|
|
if (ret >= 0) {
|
|
tmp = ret;
|
|
chip->sels[i].rb.type = RB_GPIO;
|
|
chip->sels[i].rb.info.gpio = tmp;
|
|
ret = devm_gpio_request(dev, tmp, "nand-rb");
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = gpio_direction_input(tmp);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
chip->sels[i].rb.type = RB_NONE;
|
|
}
|
|
}
|
|
}
|
|
|
|
timings = onfi_async_timing_mode_to_sdr_timings(0);
|
|
if (IS_ERR(timings)) {
|
|
ret = PTR_ERR(timings);
|
|
dev_err(dev,
|
|
"could not retrieve timings for ONFI mode 0: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = sunxi_nand_chip_set_timings(chip, timings);
|
|
if (ret) {
|
|
dev_err(dev, "could not configure chip timings: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
nand = &chip->nand;
|
|
/* Default tR value specified in the ONFI spec (chapter 4.15.1) */
|
|
nand->chip_delay = 200;
|
|
nand->controller = &nfc->controller;
|
|
nand->select_chip = sunxi_nfc_select_chip;
|
|
nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
|
|
nand->read_buf = sunxi_nfc_read_buf;
|
|
nand->write_buf = sunxi_nfc_write_buf;
|
|
nand->read_byte = sunxi_nfc_read_byte;
|
|
|
|
if (of_get_nand_on_flash_bbt(np))
|
|
nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
|
|
|
|
mtd = &chip->mtd;
|
|
mtd->dev.parent = dev;
|
|
mtd->priv = nand;
|
|
mtd->owner = THIS_MODULE;
|
|
|
|
ret = nand_scan_ident(mtd, nsels, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = sunxi_nand_chip_init_timings(chip, np);
|
|
if (ret) {
|
|
dev_err(dev, "could not configure chip timings: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
|
|
if (ret) {
|
|
dev_err(dev, "ECC init failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret) {
|
|
dev_err(dev, "nand_scan_tail failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ppdata.of_node = np;
|
|
ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
|
|
if (ret) {
|
|
dev_err(dev, "failed to register mtd device: %d\n", ret);
|
|
nand_release(mtd);
|
|
return ret;
|
|
}
|
|
|
|
list_add_tail(&chip->node, &nfc->chips);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct device_node *nand_np;
|
|
int nchips = of_get_child_count(np);
|
|
int ret;
|
|
|
|
if (nchips > 8) {
|
|
dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
|
|
return -EINVAL;
|
|
}
|
|
|
|
for_each_child_of_node(np, nand_np) {
|
|
ret = sunxi_nand_chip_init(dev, nfc, nand_np);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
|
|
{
|
|
struct sunxi_nand_chip *chip;
|
|
|
|
while (!list_empty(&nfc->chips)) {
|
|
chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
|
|
node);
|
|
nand_release(&chip->mtd);
|
|
sunxi_nand_ecc_cleanup(&chip->nand.ecc);
|
|
}
|
|
}
|
|
|
|
static int sunxi_nfc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *r;
|
|
struct sunxi_nfc *nfc;
|
|
int irq;
|
|
int ret;
|
|
|
|
nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
|
|
if (!nfc)
|
|
return -ENOMEM;
|
|
|
|
nfc->dev = dev;
|
|
spin_lock_init(&nfc->controller.lock);
|
|
init_waitqueue_head(&nfc->controller.wq);
|
|
INIT_LIST_HEAD(&nfc->chips);
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
nfc->regs = devm_ioremap_resource(dev, r);
|
|
if (IS_ERR(nfc->regs))
|
|
return PTR_ERR(nfc->regs);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to retrieve irq\n");
|
|
return irq;
|
|
}
|
|
|
|
nfc->ahb_clk = devm_clk_get(dev, "ahb");
|
|
if (IS_ERR(nfc->ahb_clk)) {
|
|
dev_err(dev, "failed to retrieve ahb clk\n");
|
|
return PTR_ERR(nfc->ahb_clk);
|
|
}
|
|
|
|
ret = clk_prepare_enable(nfc->ahb_clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nfc->mod_clk = devm_clk_get(dev, "mod");
|
|
if (IS_ERR(nfc->mod_clk)) {
|
|
dev_err(dev, "failed to retrieve mod clk\n");
|
|
ret = PTR_ERR(nfc->mod_clk);
|
|
goto out_ahb_clk_unprepare;
|
|
}
|
|
|
|
ret = clk_prepare_enable(nfc->mod_clk);
|
|
if (ret)
|
|
goto out_ahb_clk_unprepare;
|
|
|
|
ret = sunxi_nfc_rst(nfc);
|
|
if (ret)
|
|
goto out_mod_clk_unprepare;
|
|
|
|
writel(0, nfc->regs + NFC_REG_INT);
|
|
ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
|
|
0, "sunxi-nand", nfc);
|
|
if (ret)
|
|
goto out_mod_clk_unprepare;
|
|
|
|
platform_set_drvdata(pdev, nfc);
|
|
|
|
ret = sunxi_nand_chips_init(dev, nfc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to init nand chips\n");
|
|
goto out_mod_clk_unprepare;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out_mod_clk_unprepare:
|
|
clk_disable_unprepare(nfc->mod_clk);
|
|
out_ahb_clk_unprepare:
|
|
clk_disable_unprepare(nfc->ahb_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sunxi_nfc_remove(struct platform_device *pdev)
|
|
{
|
|
struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
|
|
|
|
sunxi_nand_chips_cleanup(nfc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sunxi_nfc_ids[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-nand" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
|
|
|
|
static struct platform_driver sunxi_nfc_driver = {
|
|
.driver = {
|
|
.name = "sunxi_nand",
|
|
.of_match_table = sunxi_nfc_ids,
|
|
},
|
|
.probe = sunxi_nfc_probe,
|
|
.remove = sunxi_nfc_remove,
|
|
};
|
|
module_platform_driver(sunxi_nfc_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Boris BREZILLON");
|
|
MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
|
|
MODULE_ALIAS("platform:sunxi_nand");
|