mirror of https://gitee.com/openkylin/linux.git
172 lines
4.8 KiB
C
172 lines
4.8 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_MMU_H__
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#define __ARM_KVM_MMU_H__
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#include <asm/memory.h>
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#include <asm/page.h>
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/*
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* We directly use the kernel VA for the HYP, as we can directly share
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* the mapping (HTTBR "covers" TTBR1).
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*/
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#define HYP_PAGE_OFFSET_MASK UL(~0)
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#define HYP_PAGE_OFFSET PAGE_OFFSET
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#define KERN_TO_HYP(kva) (kva)
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/*
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* Our virtual mapping for the boot-time MMU-enable code. Must be
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* shared across all the page-tables. Conveniently, we use the vectors
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* page, where no kernel data will ever be shared with HYP.
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*/
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#define TRAMPOLINE_VA UL(CONFIG_VECTORS_BASE)
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#ifndef __ASSEMBLY__
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#include <asm/cacheflush.h>
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#include <asm/pgalloc.h>
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int create_hyp_mappings(void *from, void *to);
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int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
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void free_boot_hyp_pgd(void);
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void free_hyp_pgds(void);
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int kvm_alloc_stage2_pgd(struct kvm *kvm);
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void kvm_free_stage2_pgd(struct kvm *kvm);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_mmu_get_boot_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd)
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{
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*pmd = new_pmd;
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flush_pmd_entry(pmd);
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}
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static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
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{
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*pte = new_pte;
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/*
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* flush_pmd_entry just takes a void pointer and cleans the necessary
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* cache entries, so we can reuse the function for ptes.
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*/
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flush_pmd_entry(pte);
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}
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static inline bool kvm_is_write_fault(unsigned long hsr)
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{
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unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
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if (hsr_ec == HSR_EC_IABT)
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return false;
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else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
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return false;
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else
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return true;
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}
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static inline void kvm_clean_pgd(pgd_t *pgd)
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{
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clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
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}
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static inline void kvm_clean_pmd_entry(pmd_t *pmd)
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{
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clean_pmd_entry(pmd);
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}
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static inline void kvm_clean_pte(pte_t *pte)
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{
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clean_pte_table(pte);
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}
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static inline void kvm_set_s2pte_writable(pte_t *pte)
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{
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pte_val(*pte) |= L_PTE_S2_RDWR;
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}
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static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
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{
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pmd_val(*pmd) |= L_PMD_S2_RDWR;
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}
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/* Open coded p*d_addr_end that can deal with 64bit addresses */
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#define kvm_pgd_addr_end(addr, end) \
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({ u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
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(__boundary - 1 < (end) - 1)? __boundary: (end); \
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})
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#define kvm_pud_addr_end(addr,end) (end)
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#define kvm_pmd_addr_end(addr, end) \
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({ u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
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(__boundary - 1 < (end) - 1)? __boundary: (end); \
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})
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;
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}
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static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
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unsigned long size)
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{
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if (!vcpu_has_cache_enabled(vcpu))
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kvm_flush_dcache_to_poc((void *)hva, size);
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/*
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* If we are going to insert an instruction page and the icache is
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* either VIPT or PIPT, there is a potential problem where the host
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* (or another VM) may have used the same page as this guest, and we
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* read incorrect data from the icache. If we're using a PIPT cache,
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* we can invalidate just that page, but if we are using a VIPT cache
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* we need to invalidate the entire icache - damn shame - as written
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* in the ARM ARM (DDI 0406C.b - Page B3-1393).
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*
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* VIVT caches are tagged using both the ASID and the VMID and doesn't
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* need any kind of flushing (DDI 0406C.b - Page B3-1392).
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*/
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if (icache_is_pipt()) {
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__cpuc_coherent_user_range(hva, hva + size);
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} else if (!icache_is_vivt_asid_tagged()) {
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/* any kind of VIPT cache */
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__flush_icache_all();
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}
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}
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#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
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void stage2_flush_vm(struct kvm *kvm);
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#endif /* !__ASSEMBLY__ */
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#endif /* __ARM_KVM_MMU_H__ */
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