mirror of https://gitee.com/openkylin/linux.git
832 lines
19 KiB
C
832 lines
19 KiB
C
/*
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*
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* Intel Management Engine Interface (Intel MEI) Linux driver
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* Copyright (c) 2003-2012, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/pci.h>
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#include <linux/kthread.h>
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#include <linux/interrupt.h>
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#include "mei_dev.h"
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#include "hbm.h"
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#include "hw-me.h"
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#include "hw-me-regs.h"
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/**
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* mei_me_reg_read - Reads 32bit data from the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to read the data
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*
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* returns register value (u32)
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*/
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static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
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unsigned long offset)
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{
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return ioread32(hw->mem_addr + offset);
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}
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/**
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* mei_me_reg_write - Writes 32bit data to the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to write the data
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* @value: register value to write (u32)
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*/
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static inline void mei_me_reg_write(const struct mei_me_hw *hw,
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unsigned long offset, u32 value)
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{
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iowrite32(value, hw->mem_addr + offset);
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}
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/**
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* mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
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* read window register
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*
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* @dev: the device structure
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*
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* returns ME_CB_RW register value (u32)
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*/
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static u32 mei_me_mecbrw_read(const struct mei_device *dev)
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{
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return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
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}
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/**
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* mei_me_mecsr_read - Reads 32bit data from the ME CSR
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*
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* @dev: the device structure
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*
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* returns ME_CSR_HA register value (u32)
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*/
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static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
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{
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return mei_me_reg_read(hw, ME_CSR_HA);
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}
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/**
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* mei_hcsr_read - Reads 32bit data from the host CSR
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*
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* @dev: the device structure
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*
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* returns H_CSR register value (u32)
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*/
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static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
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{
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return mei_me_reg_read(hw, H_CSR);
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}
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/**
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* mei_hcsr_set - writes H_CSR register to the mei device,
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* and ignores the H_IS bit for it is write-one-to-zero.
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*
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* @dev: the device structure
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*/
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static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
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{
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hcsr &= ~H_IS;
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mei_me_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* mei_me_hw_config - configure hw dependent settings
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*
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* @dev: mei device
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*/
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static void mei_me_hw_config(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(to_me_hw(dev));
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/* Doesn't change in runtime */
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dev->hbuf_depth = (hcsr & H_CBD) >> 24;
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hw->pg_state = MEI_PG_OFF;
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}
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/**
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* mei_me_pg_state - translate internal pg state
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* to the mei power gating state
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*
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* @hw - me hardware
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* returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
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*/
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static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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return hw->pg_state;
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}
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/**
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* mei_clear_interrupts - clear and stop interrupts
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*
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* @dev: the device structure
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*/
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static void mei_me_intr_clear(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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if ((hcsr & H_IS) == H_IS)
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mei_me_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* mei_me_intr_enable - enables mei device interrupts
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*
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* @dev: the device structure
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*/
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static void mei_me_intr_enable(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr |= H_IE;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* mei_disable_interrupts - disables mei device interrupts
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*
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* @dev: the device structure
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*/
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static void mei_me_intr_disable(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr &= ~H_IE;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* mei_me_hw_reset_release - release device from the reset
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*
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* @dev: the device structure
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*/
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static void mei_me_hw_reset_release(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr |= H_IG;
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hcsr &= ~H_RST;
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mei_hcsr_set(hw, hcsr);
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/* complete this write before we set host ready on another CPU */
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mmiowb();
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}
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/**
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* mei_me_hw_reset - resets fw via mei csr register.
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*
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* @dev: the device structure
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* @intr_enable: if interrupt should be enabled after reset.
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*/
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static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr |= H_RST | H_IG | H_IS;
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if (intr_enable)
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hcsr |= H_IE;
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else
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hcsr &= ~H_IE;
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dev->recvd_hw_ready = false;
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mei_me_reg_write(hw, H_CSR, hcsr);
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/*
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* Host reads the H_CSR once to ensure that the
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* posted write to H_CSR completes.
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*/
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hcsr = mei_hcsr_read(hw);
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if ((hcsr & H_RST) == 0)
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dev_warn(&dev->pdev->dev, "H_RST is not set = 0x%08X", hcsr);
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if ((hcsr & H_RDY) == H_RDY)
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dev_warn(&dev->pdev->dev, "H_RDY is not cleared 0x%08X", hcsr);
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if (intr_enable == false)
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mei_me_hw_reset_release(dev);
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return 0;
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}
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/**
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* mei_me_host_set_ready - enable device
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*
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* @dev - mei device
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* returns bool
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*/
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static void mei_me_host_set_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->host_hw_state = mei_hcsr_read(hw);
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hw->host_hw_state |= H_IE | H_IG | H_RDY;
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mei_hcsr_set(hw, hw->host_hw_state);
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}
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/**
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* mei_me_host_is_ready - check whether the host has turned ready
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*
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* @dev - mei device
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* returns bool
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*/
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static bool mei_me_host_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->host_hw_state = mei_hcsr_read(hw);
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return (hw->host_hw_state & H_RDY) == H_RDY;
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}
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/**
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* mei_me_hw_is_ready - check whether the me(hw) has turned ready
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*
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* @dev - mei device
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* returns bool
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*/
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static bool mei_me_hw_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->me_hw_state = mei_me_mecsr_read(hw);
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return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
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}
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static int mei_me_hw_ready_wait(struct mei_device *dev)
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{
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int err;
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mutex_unlock(&dev->device_lock);
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err = wait_event_interruptible_timeout(dev->wait_hw_ready,
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dev->recvd_hw_ready,
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mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
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mutex_lock(&dev->device_lock);
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if (!err && !dev->recvd_hw_ready) {
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if (!err)
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err = -ETIME;
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dev_err(&dev->pdev->dev,
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"wait hw ready failed. status = %d\n", err);
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return err;
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}
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dev->recvd_hw_ready = false;
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return 0;
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}
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static int mei_me_hw_start(struct mei_device *dev)
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{
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int ret = mei_me_hw_ready_wait(dev);
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if (ret)
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return ret;
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dev_dbg(&dev->pdev->dev, "hw is ready\n");
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mei_me_host_set_ready(dev);
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return ret;
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}
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/**
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* mei_hbuf_filled_slots - gets number of device filled buffer slots
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*
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* @dev: the device structure
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*
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* returns number of filled slots
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*/
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static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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char read_ptr, write_ptr;
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hw->host_hw_state = mei_hcsr_read(hw);
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read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
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write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
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return (unsigned char) (write_ptr - read_ptr);
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}
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/**
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* mei_me_hbuf_is_empty - checks if host buffer is empty.
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*
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* @dev: the device structure
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*
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* returns true if empty, false - otherwise.
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*/
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static bool mei_me_hbuf_is_empty(struct mei_device *dev)
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{
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return mei_hbuf_filled_slots(dev) == 0;
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}
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/**
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* mei_me_hbuf_empty_slots - counts write empty slots.
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*
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* @dev: the device structure
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*
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* returns -EOVERFLOW if overflow, otherwise empty slots count
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*/
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static int mei_me_hbuf_empty_slots(struct mei_device *dev)
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{
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unsigned char filled_slots, empty_slots;
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filled_slots = mei_hbuf_filled_slots(dev);
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empty_slots = dev->hbuf_depth - filled_slots;
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/* check for overflow */
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if (filled_slots > dev->hbuf_depth)
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return -EOVERFLOW;
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return empty_slots;
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}
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static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
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{
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return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
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}
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/**
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* mei_me_write_message - writes a message to mei device.
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*
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* @dev: the device structure
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* @header: mei HECI header of message
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* @buf: message payload will be written
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*
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* This function returns -EIO if write has failed
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*/
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static int mei_me_write_message(struct mei_device *dev,
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struct mei_msg_hdr *header,
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unsigned char *buf)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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unsigned long rem;
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unsigned long length = header->length;
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u32 *reg_buf = (u32 *)buf;
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u32 hcsr;
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u32 dw_cnt;
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int i;
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int empty_slots;
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dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
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empty_slots = mei_hbuf_empty_slots(dev);
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dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
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dw_cnt = mei_data2slots(length);
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if (empty_slots < 0 || dw_cnt > empty_slots)
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return -EMSGSIZE;
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mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
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for (i = 0; i < length / 4; i++)
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mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
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rem = length & 0x3;
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if (rem > 0) {
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u32 reg = 0;
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memcpy(®, &buf[length - rem], rem);
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mei_me_reg_write(hw, H_CB_WW, reg);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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if (!mei_me_hw_is_ready(dev))
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return -EIO;
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return 0;
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}
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/**
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* mei_me_count_full_read_slots - counts read full slots.
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*
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* @dev: the device structure
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*
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* returns -EOVERFLOW if overflow, otherwise filled slots count
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*/
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static int mei_me_count_full_read_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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char read_ptr, write_ptr;
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unsigned char buffer_depth, filled_slots;
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hw->me_hw_state = mei_me_mecsr_read(hw);
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buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
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read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
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write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
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filled_slots = (unsigned char) (write_ptr - read_ptr);
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/* check for overflow */
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if (filled_slots > buffer_depth)
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return -EOVERFLOW;
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dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
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return (int)filled_slots;
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}
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/**
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* mei_me_read_slots - reads a message from mei device.
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*
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* @dev: the device structure
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* @buffer: message buffer will be written
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* @buffer_length: message size will be read
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*/
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static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
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unsigned long buffer_length)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 *reg_buf = (u32 *)buffer;
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u32 hcsr;
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for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
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*reg_buf++ = mei_me_mecbrw_read(dev);
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if (buffer_length > 0) {
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u32 reg = mei_me_mecbrw_read(dev);
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memcpy(reg_buf, ®, buffer_length);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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return 0;
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}
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/**
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* mei_me_pg_enter - write pg enter register to mei device.
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*
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* @dev: the device structure
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*/
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static void mei_me_pg_enter(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
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reg |= H_HPG_CSR_PGI;
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mei_me_reg_write(hw, H_HPG_CSR, reg);
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}
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/**
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* mei_me_pg_enter - write pg enter register to mei device.
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*
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* @dev: the device structure
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*/
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static void mei_me_pg_exit(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
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WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
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reg |= H_HPG_CSR_PGIHEXR;
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mei_me_reg_write(hw, H_HPG_CSR, reg);
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}
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/**
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* mei_me_pg_set_sync - perform pg entry procedure
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*
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* @dev: the device structure
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*
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* returns 0 on success an error code otherwise
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*/
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int mei_me_pg_set_sync(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
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int ret;
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dev->pg_event = MEI_PG_EVENT_WAIT;
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ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mutex_unlock(&dev->device_lock);
|
|
wait_event_timeout(dev->wait_pg,
|
|
dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
|
|
mutex_lock(&dev->device_lock);
|
|
|
|
if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
|
|
mei_me_pg_enter(dev);
|
|
ret = 0;
|
|
} else {
|
|
ret = -ETIME;
|
|
}
|
|
|
|
dev->pg_event = MEI_PG_EVENT_IDLE;
|
|
hw->pg_state = MEI_PG_ON;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* mei_me_pg_unset_sync - perform pg exit procedure
|
|
*
|
|
* @dev: the device structure
|
|
*
|
|
* returns 0 on success an error code otherwise
|
|
*/
|
|
int mei_me_pg_unset_sync(struct mei_device *dev)
|
|
{
|
|
struct mei_me_hw *hw = to_me_hw(dev);
|
|
unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
|
|
int ret;
|
|
|
|
if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
|
|
goto reply;
|
|
|
|
dev->pg_event = MEI_PG_EVENT_WAIT;
|
|
|
|
mei_me_pg_exit(dev);
|
|
|
|
mutex_unlock(&dev->device_lock);
|
|
wait_event_timeout(dev->wait_pg,
|
|
dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
|
|
mutex_lock(&dev->device_lock);
|
|
|
|
reply:
|
|
if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
|
|
ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
|
|
else
|
|
ret = -ETIME;
|
|
|
|
dev->pg_event = MEI_PG_EVENT_IDLE;
|
|
hw->pg_state = MEI_PG_OFF;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* mei_me_pg_is_enabled - detect if PG is supported by HW
|
|
*
|
|
* @dev: the device structure
|
|
*
|
|
* returns: true is pg supported, false otherwise
|
|
*/
|
|
static bool mei_me_pg_is_enabled(struct mei_device *dev)
|
|
{
|
|
struct mei_me_hw *hw = to_me_hw(dev);
|
|
u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
|
|
|
|
if ((reg & ME_PGIC_HRA) == 0)
|
|
goto notsupported;
|
|
|
|
if (dev->version.major_version < HBM_MAJOR_VERSION_PGI)
|
|
goto notsupported;
|
|
|
|
if (dev->version.major_version == HBM_MAJOR_VERSION_PGI &&
|
|
dev->version.minor_version < HBM_MINOR_VERSION_PGI)
|
|
goto notsupported;
|
|
|
|
return true;
|
|
|
|
notsupported:
|
|
dev_dbg(&dev->pdev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
|
|
!!(reg & ME_PGIC_HRA),
|
|
dev->version.major_version,
|
|
dev->version.minor_version,
|
|
HBM_MAJOR_VERSION_PGI,
|
|
HBM_MINOR_VERSION_PGI);
|
|
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* mei_me_irq_quick_handler - The ISR of the MEI device
|
|
*
|
|
* @irq: The irq number
|
|
* @dev_id: pointer to the device structure
|
|
*
|
|
* returns irqreturn_t
|
|
*/
|
|
|
|
irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
|
|
{
|
|
struct mei_device *dev = (struct mei_device *) dev_id;
|
|
struct mei_me_hw *hw = to_me_hw(dev);
|
|
u32 csr_reg = mei_hcsr_read(hw);
|
|
|
|
if ((csr_reg & H_IS) != H_IS)
|
|
return IRQ_NONE;
|
|
|
|
/* clear H_IS bit in H_CSR */
|
|
mei_me_reg_write(hw, H_CSR, csr_reg);
|
|
|
|
return IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
/**
|
|
* mei_me_irq_thread_handler - function called after ISR to handle the interrupt
|
|
* processing.
|
|
*
|
|
* @irq: The irq number
|
|
* @dev_id: pointer to the device structure
|
|
*
|
|
* returns irqreturn_t
|
|
*
|
|
*/
|
|
irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
|
|
{
|
|
struct mei_device *dev = (struct mei_device *) dev_id;
|
|
struct mei_cl_cb complete_list;
|
|
s32 slots;
|
|
int rets = 0;
|
|
|
|
dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
|
|
/* initialize our complete list */
|
|
mutex_lock(&dev->device_lock);
|
|
mei_io_list_init(&complete_list);
|
|
|
|
/* Ack the interrupt here
|
|
* In case of MSI we don't go through the quick handler */
|
|
if (pci_dev_msi_enabled(dev->pdev))
|
|
mei_clear_interrupts(dev);
|
|
|
|
/* check if ME wants a reset */
|
|
if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
|
|
dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
|
|
schedule_work(&dev->reset_work);
|
|
goto end;
|
|
}
|
|
|
|
/* check if we need to start the dev */
|
|
if (!mei_host_is_ready(dev)) {
|
|
if (mei_hw_is_ready(dev)) {
|
|
mei_me_hw_reset_release(dev);
|
|
dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
|
|
|
|
dev->recvd_hw_ready = true;
|
|
wake_up_interruptible(&dev->wait_hw_ready);
|
|
} else {
|
|
dev_dbg(&dev->pdev->dev, "Spurious Interrupt\n");
|
|
}
|
|
goto end;
|
|
}
|
|
/* check slots available for reading */
|
|
slots = mei_count_full_read_slots(dev);
|
|
while (slots > 0) {
|
|
dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
|
|
rets = mei_irq_read_handler(dev, &complete_list, &slots);
|
|
/* There is a race between ME write and interrupt delivery:
|
|
* Not all data is always available immediately after the
|
|
* interrupt, so try to read again on the next interrupt.
|
|
*/
|
|
if (rets == -ENODATA)
|
|
break;
|
|
|
|
if (rets && dev->dev_state != MEI_DEV_RESETTING) {
|
|
dev_err(&dev->pdev->dev, "mei_irq_read_handler ret = %d.\n",
|
|
rets);
|
|
schedule_work(&dev->reset_work);
|
|
goto end;
|
|
}
|
|
}
|
|
|
|
dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
|
|
|
|
/*
|
|
* During PG handshake only allowed write is the replay to the
|
|
* PG exit message, so block calling write function
|
|
* if the pg state is not idle
|
|
*/
|
|
if (dev->pg_event == MEI_PG_EVENT_IDLE) {
|
|
rets = mei_irq_write_handler(dev, &complete_list);
|
|
dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
|
|
}
|
|
|
|
mei_irq_compl_handler(dev, &complete_list);
|
|
|
|
end:
|
|
dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
|
|
mutex_unlock(&dev->device_lock);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct mei_hw_ops mei_me_hw_ops = {
|
|
|
|
.pg_state = mei_me_pg_state,
|
|
|
|
.host_is_ready = mei_me_host_is_ready,
|
|
|
|
.hw_is_ready = mei_me_hw_is_ready,
|
|
.hw_reset = mei_me_hw_reset,
|
|
.hw_config = mei_me_hw_config,
|
|
.hw_start = mei_me_hw_start,
|
|
|
|
.pg_is_enabled = mei_me_pg_is_enabled,
|
|
|
|
.intr_clear = mei_me_intr_clear,
|
|
.intr_enable = mei_me_intr_enable,
|
|
.intr_disable = mei_me_intr_disable,
|
|
|
|
.hbuf_free_slots = mei_me_hbuf_empty_slots,
|
|
.hbuf_is_ready = mei_me_hbuf_is_empty,
|
|
.hbuf_max_len = mei_me_hbuf_max_len,
|
|
|
|
.write = mei_me_write_message,
|
|
|
|
.rdbuf_full_slots = mei_me_count_full_read_slots,
|
|
.read_hdr = mei_me_mecbrw_read,
|
|
.read = mei_me_read_slots
|
|
};
|
|
|
|
static bool mei_me_fw_type_nm(struct pci_dev *pdev)
|
|
{
|
|
u32 reg;
|
|
pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
|
|
/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
|
|
return (reg & 0x600) == 0x200;
|
|
}
|
|
|
|
#define MEI_CFG_FW_NM \
|
|
.quirk_probe = mei_me_fw_type_nm
|
|
|
|
static bool mei_me_fw_type_sps(struct pci_dev *pdev)
|
|
{
|
|
u32 reg;
|
|
/* Read ME FW Status check for SPS Firmware */
|
|
pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
|
|
/* if bits [19:16] = 15, running SPS Firmware */
|
|
return (reg & 0xf0000) == 0xf0000;
|
|
}
|
|
|
|
#define MEI_CFG_FW_SPS \
|
|
.quirk_probe = mei_me_fw_type_sps
|
|
|
|
|
|
#define MEI_CFG_LEGACY_HFS \
|
|
.fw_status.count = 0
|
|
|
|
#define MEI_CFG_ICH_HFS \
|
|
.fw_status.count = 1, \
|
|
.fw_status.status[0] = PCI_CFG_HFS_1
|
|
|
|
#define MEI_CFG_PCH_HFS \
|
|
.fw_status.count = 2, \
|
|
.fw_status.status[0] = PCI_CFG_HFS_1, \
|
|
.fw_status.status[1] = PCI_CFG_HFS_2
|
|
|
|
|
|
/* ICH Legacy devices */
|
|
const struct mei_cfg mei_me_legacy_cfg = {
|
|
MEI_CFG_LEGACY_HFS,
|
|
};
|
|
|
|
/* ICH devices */
|
|
const struct mei_cfg mei_me_ich_cfg = {
|
|
MEI_CFG_ICH_HFS,
|
|
};
|
|
|
|
/* PCH devices */
|
|
const struct mei_cfg mei_me_pch_cfg = {
|
|
MEI_CFG_PCH_HFS,
|
|
};
|
|
|
|
|
|
/* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
|
|
const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
|
|
MEI_CFG_PCH_HFS,
|
|
MEI_CFG_FW_NM,
|
|
};
|
|
|
|
/* PCH Lynx Point with quirk for SPS Firmware exclusion */
|
|
const struct mei_cfg mei_me_lpt_cfg = {
|
|
MEI_CFG_PCH_HFS,
|
|
MEI_CFG_FW_SPS,
|
|
};
|
|
|
|
/**
|
|
* mei_me_dev_init - allocates and initializes the mei device structure
|
|
*
|
|
* @pdev: The pci device structure
|
|
* @cfg: per device generation config
|
|
*
|
|
* returns The mei_device_device pointer on success, NULL on failure.
|
|
*/
|
|
struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
|
|
const struct mei_cfg *cfg)
|
|
{
|
|
struct mei_device *dev;
|
|
|
|
dev = kzalloc(sizeof(struct mei_device) +
|
|
sizeof(struct mei_me_hw), GFP_KERNEL);
|
|
if (!dev)
|
|
return NULL;
|
|
|
|
mei_device_init(dev, cfg);
|
|
|
|
dev->ops = &mei_me_hw_ops;
|
|
|
|
dev->pdev = pdev;
|
|
return dev;
|
|
}
|
|
|