mirror of https://gitee.com/openkylin/linux.git
471 lines
11 KiB
C
471 lines
11 KiB
C
/*
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* sh7372 Power management support
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*
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* Copyright (C) 2011 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/pm_clock.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/bitrev.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <asm/suspend.h>
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#include <mach/common.h>
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#include <mach/sh7372.h>
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/* DBG */
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#define DBGREG1 0xe6100020
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#define DBGREG9 0xe6100040
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/* CPGA */
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#define SYSTBCR 0xe6150024
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#define MSTPSR0 0xe6150030
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#define MSTPSR1 0xe6150038
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#define MSTPSR2 0xe6150040
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#define MSTPSR3 0xe6150048
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#define MSTPSR4 0xe615004c
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#define PLLC01STPCR 0xe61500c8
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/* SYSC */
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#define SPDCR 0xe6180008
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#define SWUCR 0xe6180014
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#define SBAR 0xe6180020
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#define WUPRMSK 0xe6180028
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#define WUPSMSK 0xe618002c
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#define WUPSMSK2 0xe6180048
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#define PSTR 0xe6180080
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#define WUPSFAC 0xe6180098
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#define IRQCR 0xe618022c
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#define IRQCR2 0xe6180238
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#define IRQCR3 0xe6180244
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#define IRQCR4 0xe6180248
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#define PDNSEL 0xe6180254
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/* INTC */
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#define ICR1A 0xe6900000
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#define ICR2A 0xe6900004
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#define ICR3A 0xe6900008
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#define ICR4A 0xe690000c
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#define INTMSK00A 0xe6900040
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#define INTMSK10A 0xe6900044
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#define INTMSK20A 0xe6900048
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#define INTMSK30A 0xe690004c
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/* MFIS */
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#define SMFRAM 0xe6a70000
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/* AP-System Core */
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#define APARMBAREA 0xe6f10020
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#define PSTR_RETRIES 100
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#define PSTR_DELAY_US 10
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#ifdef CONFIG_PM
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static int pd_power_down(struct generic_pm_domain *genpd)
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{
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struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
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unsigned int mask = 1 << sh7372_pd->bit_shift;
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if (sh7372_pd->suspend)
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sh7372_pd->suspend();
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if (sh7372_pd->stay_on)
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return 0;
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if (__raw_readl(PSTR) & mask) {
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unsigned int retry_count;
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__raw_writel(mask, SPDCR);
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for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
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if (!(__raw_readl(SPDCR) & mask))
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break;
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cpu_relax();
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}
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}
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if (!sh7372_pd->no_debug)
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pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
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mask, __raw_readl(PSTR));
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return 0;
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}
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static int pd_power_up(struct generic_pm_domain *genpd)
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{
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struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
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unsigned int mask = 1 << sh7372_pd->bit_shift;
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unsigned int retry_count;
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int ret = 0;
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if (sh7372_pd->stay_on)
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goto out;
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if (__raw_readl(PSTR) & mask)
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goto out;
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__raw_writel(mask, SWUCR);
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for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
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if (!(__raw_readl(SWUCR) & mask))
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goto out;
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if (retry_count > PSTR_RETRIES)
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udelay(PSTR_DELAY_US);
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else
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cpu_relax();
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}
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if (__raw_readl(SWUCR) & mask)
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ret = -EIO;
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if (!sh7372_pd->no_debug)
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pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
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mask, __raw_readl(PSTR));
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out:
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if (ret == 0 && sh7372_pd->resume)
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sh7372_pd->resume();
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return ret;
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}
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static void sh7372_a4r_suspend(void)
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{
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sh7372_intcs_suspend();
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__raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
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}
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static bool pd_active_wakeup(struct device *dev)
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{
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return true;
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}
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static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain)
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{
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return false;
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}
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struct dev_power_governor sh7372_always_on_gov = {
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.power_down_ok = sh7372_power_down_forbidden,
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};
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void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
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{
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struct generic_pm_domain *genpd = &sh7372_pd->genpd;
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pm_genpd_init(genpd, sh7372_pd->gov, false);
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genpd->stop_device = pm_clk_suspend;
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genpd->start_device = pm_clk_resume;
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genpd->dev_irq_safe = true;
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genpd->active_wakeup = pd_active_wakeup;
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genpd->power_off = pd_power_down;
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genpd->power_on = pd_power_up;
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genpd->power_on(&sh7372_pd->genpd);
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}
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void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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pm_genpd_add_device(&sh7372_pd->genpd, dev);
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if (pm_clk_no_clocks(dev))
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pm_clk_add(dev, NULL);
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}
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void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
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struct sh7372_pm_domain *sh7372_sd)
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{
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pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
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}
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struct sh7372_pm_domain sh7372_a4lc = {
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.bit_shift = 1,
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};
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struct sh7372_pm_domain sh7372_a4mp = {
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.bit_shift = 2,
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};
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struct sh7372_pm_domain sh7372_d4 = {
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.bit_shift = 3,
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};
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struct sh7372_pm_domain sh7372_a4r = {
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.bit_shift = 5,
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.gov = &sh7372_always_on_gov,
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.suspend = sh7372_a4r_suspend,
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.resume = sh7372_intcs_resume,
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.stay_on = true,
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};
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struct sh7372_pm_domain sh7372_a3rv = {
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.bit_shift = 6,
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};
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struct sh7372_pm_domain sh7372_a3ri = {
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.bit_shift = 8,
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};
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struct sh7372_pm_domain sh7372_a3sp = {
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.bit_shift = 11,
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.gov = &sh7372_always_on_gov,
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.no_debug = true,
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};
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struct sh7372_pm_domain sh7372_a3sg = {
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.bit_shift = 13,
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};
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#endif /* CONFIG_PM */
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#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
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static int sh7372_do_idle_core_standby(unsigned long unused)
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{
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cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
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return 0;
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}
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static void sh7372_enter_core_standby(void)
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{
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/* set reset vector, translate 4k */
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__raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
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__raw_writel(0, APARMBAREA);
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/* enter sleep mode with SYSTBCR to 0x10 */
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__raw_writel(0x10, SYSTBCR);
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cpu_suspend(0, sh7372_do_idle_core_standby);
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__raw_writel(0, SYSTBCR);
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/* disable reset vector translation */
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__raw_writel(0, SBAR);
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}
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#endif
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#ifdef CONFIG_SUSPEND
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static void sh7372_enter_a3sm_common(int pllc0_on)
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{
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/* set reset vector, translate 4k */
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__raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
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__raw_writel(0, APARMBAREA);
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if (pllc0_on)
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__raw_writel(0, PLLC01STPCR);
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else
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__raw_writel(1 << 28, PLLC01STPCR);
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__raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */
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__raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
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cpu_suspend(0, sh7372_do_idle_a3sm);
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__raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
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/* disable reset vector translation */
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__raw_writel(0, SBAR);
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}
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static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p)
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{
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unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
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unsigned long msk, msk2;
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/* check active clocks to determine potential wakeup sources */
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mstpsr0 = __raw_readl(MSTPSR0);
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if ((mstpsr0 & 0x00000003) != 0x00000003) {
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pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
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return 0;
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}
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mstpsr1 = __raw_readl(MSTPSR1);
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if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
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pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
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return 0;
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}
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mstpsr2 = __raw_readl(MSTPSR2);
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if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
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pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
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return 0;
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}
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mstpsr3 = __raw_readl(MSTPSR3);
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if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
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pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
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return 0;
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}
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mstpsr4 = __raw_readl(MSTPSR4);
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if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
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pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
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return 0;
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}
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msk = 0;
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msk2 = 0;
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/* make bitmaps of limited number of wakeup sources */
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if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
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msk |= 1 << 31;
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if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
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msk |= 1 << 21;
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if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
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msk |= 1 << 2;
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if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
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msk |= 1 << 1;
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if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
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msk |= 1 << 1;
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if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
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msk |= 1 << 1;
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if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
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msk2 |= 1 << 17;
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*mskp = msk;
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*msk2p = msk2;
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return 1;
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}
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static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
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{
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u16 tmp, irqcr1, irqcr2;
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int k;
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irqcr1 = 0;
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irqcr2 = 0;
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/* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
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for (k = 0; k <= 7; k++) {
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tmp = (icr >> ((7 - k) * 4)) & 0xf;
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irqcr1 |= (tmp & 0x03) << (k * 2);
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irqcr2 |= (tmp >> 2) << (k * 2);
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}
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*irqcr1p = irqcr1;
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*irqcr2p = irqcr2;
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}
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static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
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{
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u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
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unsigned long tmp;
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/* read IRQ0A -> IRQ15A mask */
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tmp = bitrev8(__raw_readb(INTMSK00A));
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tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
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/* setup WUPSMSK from clocks and external IRQ mask */
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msk = (~msk & 0xc030000f) | (tmp << 4);
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__raw_writel(msk, WUPSMSK);
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/* propage level/edge trigger for external IRQ 0->15 */
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sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
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sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
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__raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
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__raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
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/* read IRQ16A -> IRQ31A mask */
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tmp = bitrev8(__raw_readb(INTMSK20A));
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tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
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/* setup WUPSMSK2 from clocks and external IRQ mask */
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msk2 = (~msk2 & 0x00030000) | tmp;
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__raw_writel(msk2, WUPSMSK2);
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/* propage level/edge trigger for external IRQ 16->31 */
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sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
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sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
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__raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
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__raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
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}
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#endif
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#ifdef CONFIG_CPU_IDLE
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static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
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{
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struct cpuidle_state *state = &drv->states[drv->state_count];
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snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
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strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
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state->exit_latency = 10;
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state->target_residency = 20 + 10;
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state->flags = CPUIDLE_FLAG_TIME_VALID;
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shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
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drv->state_count++;
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}
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static void sh7372_cpuidle_init(void)
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{
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shmobile_cpuidle_setup = sh7372_cpuidle_setup;
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}
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#else
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static void sh7372_cpuidle_init(void) {}
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#endif
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#ifdef CONFIG_SUSPEND
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static int sh7372_enter_suspend(suspend_state_t suspend_state)
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{
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unsigned long msk, msk2;
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/* check active clocks to determine potential wakeup sources */
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if (sh7372_a3sm_valid(&msk, &msk2)) {
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/* convert INTC mask and sense to SYSC mask and sense */
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sh7372_setup_a3sm(msk, msk2);
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/* enter A3SM sleep with PLLC0 off */
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pr_debug("entering A3SM\n");
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sh7372_enter_a3sm_common(0);
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} else {
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/* default to Core Standby that supports all wakeup sources */
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pr_debug("entering Core Standby\n");
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sh7372_enter_core_standby();
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}
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return 0;
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}
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static void sh7372_suspend_init(void)
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{
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shmobile_suspend_ops.enter = sh7372_enter_suspend;
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}
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#else
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static void sh7372_suspend_init(void) {}
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#endif
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void __init sh7372_pm_init(void)
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{
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/* enable DBG hardware block to kick SYSC */
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__raw_writel(0x0000a500, DBGREG9);
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__raw_writel(0x0000a501, DBGREG9);
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__raw_writel(0x00000000, DBGREG1);
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/* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
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__raw_writel(0, PDNSEL);
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sh7372_suspend_init();
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sh7372_cpuidle_init();
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}
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