Dmitry Osipenko 860fbde438 cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle ... The driver's code is refactored in a way that will make it easy to support Tegra30/114/124 SoCs by this unified driver later on. The current functionality is equal to the old Tegra20 driver, only the code's structure changed a tad. This is also a proper platform driver now. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>		2020-03-13 11:31:58 +01:00
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arc	ARCv2: IDU-intc: Add support for edge-triggered interrupts	2019-08-26 22:34:59 +05:30
at91	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
bcm2835	soc: bcm2835: sync firmware properties with downstream	2019-01-09 16:34:46 +01:00
brcmstb	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fsl	soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c	2019-12-09 13:54:37 -06:00
imx	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mediatek	iommu/mediatek: Clean up struct mtk_smi_iommu	2019-08-30 15:57:27 +02:00
mscc	net: mscc: ocelot: export ANA, DEV and QSYS registers to include/soc/mscc	2020-01-05 23:22:33 -08:00
nps	soc: Support for NPS HW scheduling	2016-11-30 11:54:25 -08:00
qcom	soc: qcom: ocmem: add missing includes	2019-10-07 08:19:43 -07:00
rockchip	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
tegra	cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle	2020-03-13 11:31:58 +01:00