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32 lines
1.0 KiB
Plaintext
32 lines
1.0 KiB
Plaintext
OMAP Timer bindings
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Required properties:
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- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers.
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- reg: Contains timer register address range (base address and
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length).
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- interrupts: Contains the interrupt information for the timer. The
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format is being dependent on which interrupt controller
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the OMAP device uses.
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- ti,hwmods: Name of the hwmod associated to the timer, "timer<X>",
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where <X> is the instance number of the timer from the
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HW spec.
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Optional properties:
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- ti,timer-alwon: Indicates the timer is in an alway-on power domain.
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- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in
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addition to the ARM CPU.
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- ti,timer-pwm: Indicates the timer can generate a PWM output.
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- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device
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and therefore cannot be used by the kernel.
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Example:
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timer12: timer@48304000 {
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compatible = "ti,omap2-timer";
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reg = <0x48304000 0x400>;
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interrupts = <95>;
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ti,hwmods = "timer12"
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ti,timer-alwon;
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ti,timer-secure;
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};
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