mirror of https://gitee.com/openkylin/linux.git
822 lines
21 KiB
C
822 lines
21 KiB
C
/*
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* PowerPC64 port by Mike Corrigan and Dave Engebretsen
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* {mikejc|engebret}@us.ibm.com
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*
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* Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
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*
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* SMP scalability work:
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Module name: htab.c
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*
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* Description:
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* PowerPC Hashed Page Table functions
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#undef DEBUG_LOW
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/stat.h>
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#include <linux/sysctl.h>
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#include <linux/ctype.h>
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#include <linux/cache.h>
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#include <linux/init.h>
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#include <linux/signal.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/lmb.h>
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#include <asm/abs_addr.h>
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#include <asm/tlbflush.h>
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#include <asm/io.h>
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#include <asm/eeh.h>
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#include <asm/tlb.h>
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#include <asm/cacheflush.h>
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#include <asm/cputable.h>
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#include <asm/abs_addr.h>
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#include <asm/sections.h>
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#ifdef DEBUG_LOW
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#define DBG_LOW(fmt...) udbg_printf(fmt)
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#else
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#define DBG_LOW(fmt...)
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#endif
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#define KB (1024)
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#define MB (1024*KB)
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/*
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* Note: pte --> Linux PTE
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* HPTE --> PowerPC Hashed Page Table Entry
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*
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* Execution context:
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* htab_initialize is called with the MMU off (of course), but
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* the kernel has been copied down to zero so it can directly
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* reference global data. At this point it is very difficult
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* to print debug info.
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*
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*/
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#ifdef CONFIG_U3_DART
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extern unsigned long dart_tablebase;
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#endif /* CONFIG_U3_DART */
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static unsigned long _SDR1;
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struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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hpte_t *htab_address;
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unsigned long htab_size_bytes;
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unsigned long htab_hash_mask;
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int mmu_linear_psize = MMU_PAGE_4K;
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int mmu_virtual_psize = MMU_PAGE_4K;
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int mmu_vmalloc_psize = MMU_PAGE_4K;
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int mmu_io_psize = MMU_PAGE_4K;
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#ifdef CONFIG_HUGETLB_PAGE
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int mmu_huge_psize = MMU_PAGE_16M;
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unsigned int HPAGE_SHIFT;
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#endif
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#ifdef CONFIG_PPC_64K_PAGES
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int mmu_ci_restrictions;
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#endif
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/* There are definitions of page sizes arrays to be used when none
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* is provided by the firmware.
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*/
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/* Pre-POWER4 CPUs (4k pages only)
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*/
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struct mmu_psize_def mmu_psize_defaults_old[] = {
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[MMU_PAGE_4K] = {
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.shift = 12,
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.sllp = 0,
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.penc = 0,
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.avpnm = 0,
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.tlbiel = 0,
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},
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};
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/* POWER4, GPUL, POWER5
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*
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* Support for 16Mb large pages
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*/
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struct mmu_psize_def mmu_psize_defaults_gp[] = {
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[MMU_PAGE_4K] = {
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.shift = 12,
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.sllp = 0,
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.penc = 0,
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.avpnm = 0,
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.tlbiel = 1,
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},
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[MMU_PAGE_16M] = {
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.shift = 24,
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.sllp = SLB_VSID_L,
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.penc = 0,
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.avpnm = 0x1UL,
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.tlbiel = 0,
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},
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};
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int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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unsigned long pstart, unsigned long mode, int psize)
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{
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unsigned long vaddr, paddr;
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unsigned int step, shift;
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unsigned long tmp_mode;
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int ret = 0;
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shift = mmu_psize_defs[psize].shift;
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step = 1 << shift;
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for (vaddr = vstart, paddr = pstart; vaddr < vend;
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vaddr += step, paddr += step) {
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unsigned long vpn, hash, hpteg;
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unsigned long vsid = get_kernel_vsid(vaddr);
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unsigned long va = (vsid << 28) | (vaddr & 0x0fffffff);
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vpn = va >> shift;
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tmp_mode = mode;
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/* Make non-kernel text non-executable */
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if (!in_kernel_text(vaddr))
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tmp_mode = mode | HPTE_R_N;
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hash = hpt_hash(va, shift);
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hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
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DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
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BUG_ON(!ppc_md.hpte_insert);
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ret = ppc_md.hpte_insert(hpteg, va, paddr,
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tmp_mode, HPTE_V_BOLTED, psize);
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if (ret < 0)
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break;
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}
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return ret < 0 ? ret : 0;
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}
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static int __init htab_dt_scan_page_sizes(unsigned long node,
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const char *uname, int depth,
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void *data)
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{
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char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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u32 *prop;
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unsigned long size = 0;
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/* We are scanning "cpu" nodes only */
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if (type == NULL || strcmp(type, "cpu") != 0)
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return 0;
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prop = (u32 *)of_get_flat_dt_prop(node,
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"ibm,segment-page-sizes", &size);
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if (prop != NULL) {
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DBG("Page sizes from device-tree:\n");
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size /= 4;
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cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
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while(size > 0) {
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unsigned int shift = prop[0];
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unsigned int slbenc = prop[1];
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unsigned int lpnum = prop[2];
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unsigned int lpenc = 0;
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struct mmu_psize_def *def;
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int idx = -1;
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size -= 3; prop += 3;
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while(size > 0 && lpnum) {
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if (prop[0] == shift)
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lpenc = prop[1];
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prop += 2; size -= 2;
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lpnum--;
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}
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switch(shift) {
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case 0xc:
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idx = MMU_PAGE_4K;
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break;
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case 0x10:
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idx = MMU_PAGE_64K;
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break;
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case 0x14:
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idx = MMU_PAGE_1M;
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break;
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case 0x18:
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idx = MMU_PAGE_16M;
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cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
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break;
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case 0x22:
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idx = MMU_PAGE_16G;
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break;
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}
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if (idx < 0)
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continue;
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def = &mmu_psize_defs[idx];
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def->shift = shift;
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if (shift <= 23)
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def->avpnm = 0;
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else
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def->avpnm = (1 << (shift - 23)) - 1;
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def->sllp = slbenc;
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def->penc = lpenc;
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/* We don't know for sure what's up with tlbiel, so
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* for now we only set it for 4K and 64K pages
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*/
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if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
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def->tlbiel = 1;
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else
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def->tlbiel = 0;
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DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
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"tlbiel=%d, penc=%d\n",
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idx, shift, def->sllp, def->avpnm, def->tlbiel,
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def->penc);
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}
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return 1;
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}
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return 0;
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}
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static void __init htab_init_page_sizes(void)
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{
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int rc;
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/* Default to 4K pages only */
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memcpy(mmu_psize_defs, mmu_psize_defaults_old,
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sizeof(mmu_psize_defaults_old));
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/*
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* Try to find the available page sizes in the device-tree
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*/
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rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
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if (rc != 0) /* Found */
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goto found;
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/*
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* Not in the device-tree, let's fallback on known size
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* list for 16M capable GP & GR
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*/
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if (cpu_has_feature(CPU_FTR_16M_PAGE) && !machine_is(iseries))
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memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
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sizeof(mmu_psize_defaults_gp));
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found:
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/*
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* Pick a size for the linear mapping. Currently, we only support
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* 16M, 1M and 4K which is the default
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*/
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if (mmu_psize_defs[MMU_PAGE_16M].shift)
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mmu_linear_psize = MMU_PAGE_16M;
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else if (mmu_psize_defs[MMU_PAGE_1M].shift)
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mmu_linear_psize = MMU_PAGE_1M;
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#ifdef CONFIG_PPC_64K_PAGES
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/*
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* Pick a size for the ordinary pages. Default is 4K, we support
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* 64K for user mappings and vmalloc if supported by the processor.
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* We only use 64k for ioremap if the processor
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* (and firmware) support cache-inhibited large pages.
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* If not, we use 4k and set mmu_ci_restrictions so that
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* hash_page knows to switch processes that use cache-inhibited
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* mappings to 4k pages.
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*/
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if (mmu_psize_defs[MMU_PAGE_64K].shift) {
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mmu_virtual_psize = MMU_PAGE_64K;
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mmu_vmalloc_psize = MMU_PAGE_64K;
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if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
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mmu_io_psize = MMU_PAGE_64K;
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else
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mmu_ci_restrictions = 1;
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}
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#endif
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printk(KERN_DEBUG "Page orders: linear mapping = %d, "
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"virtual = %d, io = %d\n",
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mmu_psize_defs[mmu_linear_psize].shift,
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mmu_psize_defs[mmu_virtual_psize].shift,
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mmu_psize_defs[mmu_io_psize].shift);
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#ifdef CONFIG_HUGETLB_PAGE
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/* Init large page size. Currently, we pick 16M or 1M depending
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* on what is available
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*/
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if (mmu_psize_defs[MMU_PAGE_16M].shift)
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mmu_huge_psize = MMU_PAGE_16M;
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/* With 4k/4level pagetables, we can't (for now) cope with a
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* huge page size < PMD_SIZE */
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else if (mmu_psize_defs[MMU_PAGE_1M].shift)
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mmu_huge_psize = MMU_PAGE_1M;
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/* Calculate HPAGE_SHIFT and sanity check it */
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if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT &&
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mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT)
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HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift;
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else
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HPAGE_SHIFT = 0; /* No huge pages dude ! */
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#endif /* CONFIG_HUGETLB_PAGE */
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}
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static int __init htab_dt_scan_pftsize(unsigned long node,
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const char *uname, int depth,
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void *data)
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{
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char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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u32 *prop;
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/* We are scanning "cpu" nodes only */
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if (type == NULL || strcmp(type, "cpu") != 0)
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return 0;
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prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
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if (prop != NULL) {
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/* pft_size[0] is the NUMA CEC cookie */
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ppc64_pft_size = prop[1];
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return 1;
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}
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return 0;
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}
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static unsigned long __init htab_get_table_size(void)
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{
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unsigned long mem_size, rnd_mem_size, pteg_count;
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/* If hash size isn't already provided by the platform, we try to
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* retrieve it from the device-tree. If it's not there neither, we
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* calculate it now based on the total RAM size
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*/
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if (ppc64_pft_size == 0)
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of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
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if (ppc64_pft_size)
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return 1UL << ppc64_pft_size;
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/* round mem_size up to next power of 2 */
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mem_size = lmb_phys_mem_size();
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rnd_mem_size = 1UL << __ilog2(mem_size);
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if (rnd_mem_size < mem_size)
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rnd_mem_size <<= 1;
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/* # pages / 2 */
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pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
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return pteg_count << 7;
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}
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#ifdef CONFIG_MEMORY_HOTPLUG
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void create_section_mapping(unsigned long start, unsigned long end)
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{
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BUG_ON(htab_bolt_mapping(start, end, __pa(start),
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_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
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mmu_linear_psize));
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}
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#endif /* CONFIG_MEMORY_HOTPLUG */
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static inline void make_bl(unsigned int *insn_addr, void *func)
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{
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unsigned long funcp = *((unsigned long *)func);
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int offset = funcp - (unsigned long)insn_addr;
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*insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
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flush_icache_range((unsigned long)insn_addr, 4+
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(unsigned long)insn_addr);
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}
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static void __init htab_finish_init(void)
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{
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extern unsigned int *htab_call_hpte_insert1;
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extern unsigned int *htab_call_hpte_insert2;
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extern unsigned int *htab_call_hpte_remove;
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extern unsigned int *htab_call_hpte_updatepp;
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#ifdef CONFIG_PPC_64K_PAGES
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extern unsigned int *ht64_call_hpte_insert1;
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extern unsigned int *ht64_call_hpte_insert2;
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extern unsigned int *ht64_call_hpte_remove;
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extern unsigned int *ht64_call_hpte_updatepp;
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make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
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make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
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make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
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make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
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#endif /* CONFIG_PPC_64K_PAGES */
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make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
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make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
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make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
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make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
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}
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void __init htab_initialize(void)
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{
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unsigned long table;
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unsigned long pteg_count;
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unsigned long mode_rw;
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unsigned long base = 0, size = 0;
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int i;
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extern unsigned long tce_alloc_start, tce_alloc_end;
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DBG(" -> htab_initialize()\n");
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/* Initialize page sizes */
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htab_init_page_sizes();
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/*
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* Calculate the required size of the htab. We want the number of
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* PTEGs to equal one half the number of real pages.
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*/
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htab_size_bytes = htab_get_table_size();
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pteg_count = htab_size_bytes >> 7;
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htab_hash_mask = pteg_count - 1;
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if (firmware_has_feature(FW_FEATURE_LPAR)) {
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/* Using a hypervisor which owns the htab */
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htab_address = NULL;
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_SDR1 = 0;
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} else {
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/* Find storage for the HPT. Must be contiguous in
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* the absolute address space.
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*/
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table = lmb_alloc(htab_size_bytes, htab_size_bytes);
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DBG("Hash table allocated at %lx, size: %lx\n", table,
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htab_size_bytes);
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htab_address = abs_to_virt(table);
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/* htab absolute addr + encoded htabsize */
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_SDR1 = table + __ilog2(pteg_count) - 11;
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/* Initialize the HPT with no entries */
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memset((void *)table, 0, htab_size_bytes);
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/* Set SDR1 */
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mtspr(SPRN_SDR1, _SDR1);
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}
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mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
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/* On U3 based machines, we need to reserve the DART area and
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* _NOT_ map it to avoid cache paradoxes as it's remapped non
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* cacheable later on
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*/
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|
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/* create bolted the linear mapping in the hash table */
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for (i=0; i < lmb.memory.cnt; i++) {
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base = (unsigned long)__va(lmb.memory.region[i].base);
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size = lmb.memory.region[i].size;
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|
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DBG("creating mapping for region: %lx : %lx\n", base, size);
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|
|
#ifdef CONFIG_U3_DART
|
|
/* Do not map the DART space. Fortunately, it will be aligned
|
|
* in such a way that it will not cross two lmb regions and
|
|
* will fit within a single 16Mb page.
|
|
* The DART space is assumed to be a full 16Mb region even if
|
|
* we only use 2Mb of that space. We will use more of it later
|
|
* for AGP GART. We have to use a full 16Mb large page.
|
|
*/
|
|
DBG("DART base: %lx\n", dart_tablebase);
|
|
|
|
if (dart_tablebase != 0 && dart_tablebase >= base
|
|
&& dart_tablebase < (base + size)) {
|
|
unsigned long dart_table_end = dart_tablebase + 16 * MB;
|
|
if (base != dart_tablebase)
|
|
BUG_ON(htab_bolt_mapping(base, dart_tablebase,
|
|
__pa(base), mode_rw,
|
|
mmu_linear_psize));
|
|
if ((base + size) > dart_table_end)
|
|
BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
|
|
base + size,
|
|
__pa(dart_table_end),
|
|
mode_rw,
|
|
mmu_linear_psize));
|
|
continue;
|
|
}
|
|
#endif /* CONFIG_U3_DART */
|
|
BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
|
|
mode_rw, mmu_linear_psize));
|
|
}
|
|
|
|
/*
|
|
* If we have a memory_limit and we've allocated TCEs then we need to
|
|
* explicitly map the TCE area at the top of RAM. We also cope with the
|
|
* case that the TCEs start below memory_limit.
|
|
* tce_alloc_start/end are 16MB aligned so the mapping should work
|
|
* for either 4K or 16MB pages.
|
|
*/
|
|
if (tce_alloc_start) {
|
|
tce_alloc_start = (unsigned long)__va(tce_alloc_start);
|
|
tce_alloc_end = (unsigned long)__va(tce_alloc_end);
|
|
|
|
if (base + size >= tce_alloc_start)
|
|
tce_alloc_start = base + size + 1;
|
|
|
|
BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
|
|
__pa(tce_alloc_start), mode_rw,
|
|
mmu_linear_psize));
|
|
}
|
|
|
|
htab_finish_init();
|
|
|
|
DBG(" <- htab_initialize()\n");
|
|
}
|
|
#undef KB
|
|
#undef MB
|
|
|
|
void htab_initialize_secondary(void)
|
|
{
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
|
mtspr(SPRN_SDR1, _SDR1);
|
|
}
|
|
|
|
/*
|
|
* Called by asm hashtable.S for doing lazy icache flush
|
|
*/
|
|
unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
|
|
{
|
|
struct page *page;
|
|
|
|
if (!pfn_valid(pte_pfn(pte)))
|
|
return pp;
|
|
|
|
page = pte_page(pte);
|
|
|
|
/* page is dirty */
|
|
if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
|
|
if (trap == 0x400) {
|
|
__flush_dcache_icache(page_address(page));
|
|
set_bit(PG_arch_1, &page->flags);
|
|
} else
|
|
pp |= HPTE_R_N;
|
|
}
|
|
return pp;
|
|
}
|
|
|
|
/* Result code is:
|
|
* 0 - handled
|
|
* 1 - normal page fault
|
|
* -1 - critical hash insertion error
|
|
*/
|
|
int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
|
|
{
|
|
void *pgdir;
|
|
unsigned long vsid;
|
|
struct mm_struct *mm;
|
|
pte_t *ptep;
|
|
cpumask_t tmp;
|
|
int rc, user_region = 0, local = 0;
|
|
int psize;
|
|
|
|
DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
|
|
ea, access, trap);
|
|
|
|
if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
|
|
DBG_LOW(" out of pgtable range !\n");
|
|
return 1;
|
|
}
|
|
|
|
/* Get region & vsid */
|
|
switch (REGION_ID(ea)) {
|
|
case USER_REGION_ID:
|
|
user_region = 1;
|
|
mm = current->mm;
|
|
if (! mm) {
|
|
DBG_LOW(" user region with no mm !\n");
|
|
return 1;
|
|
}
|
|
vsid = get_vsid(mm->context.id, ea);
|
|
psize = mm->context.user_psize;
|
|
break;
|
|
case VMALLOC_REGION_ID:
|
|
mm = &init_mm;
|
|
vsid = get_kernel_vsid(ea);
|
|
if (ea < VMALLOC_END)
|
|
psize = mmu_vmalloc_psize;
|
|
else
|
|
psize = mmu_io_psize;
|
|
break;
|
|
default:
|
|
/* Not a valid range
|
|
* Send the problem up to do_page_fault
|
|
*/
|
|
return 1;
|
|
}
|
|
DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
|
|
|
|
/* Get pgdir */
|
|
pgdir = mm->pgd;
|
|
if (pgdir == NULL)
|
|
return 1;
|
|
|
|
/* Check CPU locality */
|
|
tmp = cpumask_of_cpu(smp_processor_id());
|
|
if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
|
|
local = 1;
|
|
|
|
/* Handle hugepage regions */
|
|
if (unlikely(in_hugepage_area(mm->context, ea))) {
|
|
DBG_LOW(" -> huge page !\n");
|
|
return hash_huge_page(mm, access, ea, vsid, local, trap);
|
|
}
|
|
|
|
/* Get PTE and page size from page tables */
|
|
ptep = find_linux_pte(pgdir, ea);
|
|
if (ptep == NULL || !pte_present(*ptep)) {
|
|
DBG_LOW(" no PTE !\n");
|
|
return 1;
|
|
}
|
|
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
|
|
#else
|
|
DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
|
|
pte_val(*(ptep + PTRS_PER_PTE)));
|
|
#endif
|
|
/* Pre-check access permissions (will be re-checked atomically
|
|
* in __hash_page_XX but this pre-check is a fast path
|
|
*/
|
|
if (access & ~pte_val(*ptep)) {
|
|
DBG_LOW(" no access !\n");
|
|
return 1;
|
|
}
|
|
|
|
/* Do actual hashing */
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
|
|
#else
|
|
if (mmu_ci_restrictions) {
|
|
/* If this PTE is non-cacheable, switch to 4k */
|
|
if (psize == MMU_PAGE_64K &&
|
|
(pte_val(*ptep) & _PAGE_NO_CACHE)) {
|
|
if (user_region) {
|
|
psize = MMU_PAGE_4K;
|
|
mm->context.user_psize = MMU_PAGE_4K;
|
|
mm->context.sllp = SLB_VSID_USER |
|
|
mmu_psize_defs[MMU_PAGE_4K].sllp;
|
|
} else if (ea < VMALLOC_END) {
|
|
/*
|
|
* some driver did a non-cacheable mapping
|
|
* in vmalloc space, so switch vmalloc
|
|
* to 4k pages
|
|
*/
|
|
printk(KERN_ALERT "Reducing vmalloc segment "
|
|
"to 4kB pages because of "
|
|
"non-cacheable mapping\n");
|
|
psize = mmu_vmalloc_psize = MMU_PAGE_4K;
|
|
}
|
|
}
|
|
if (user_region) {
|
|
if (psize != get_paca()->context.user_psize) {
|
|
get_paca()->context = mm->context;
|
|
slb_flush_and_rebolt();
|
|
}
|
|
} else if (get_paca()->vmalloc_sllp !=
|
|
mmu_psize_defs[mmu_vmalloc_psize].sllp) {
|
|
get_paca()->vmalloc_sllp =
|
|
mmu_psize_defs[mmu_vmalloc_psize].sllp;
|
|
slb_flush_and_rebolt();
|
|
}
|
|
}
|
|
if (psize == MMU_PAGE_64K)
|
|
rc = __hash_page_64K(ea, access, vsid, ptep, trap, local);
|
|
else
|
|
rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
|
|
#else
|
|
DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
|
|
pte_val(*(ptep + PTRS_PER_PTE)));
|
|
#endif
|
|
DBG_LOW(" -> rc=%d\n", rc);
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hash_page);
|
|
|
|
void hash_preload(struct mm_struct *mm, unsigned long ea,
|
|
unsigned long access, unsigned long trap)
|
|
{
|
|
unsigned long vsid;
|
|
void *pgdir;
|
|
pte_t *ptep;
|
|
cpumask_t mask;
|
|
unsigned long flags;
|
|
int local = 0;
|
|
|
|
/* We don't want huge pages prefaulted for now
|
|
*/
|
|
if (unlikely(in_hugepage_area(mm->context, ea)))
|
|
return;
|
|
|
|
DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
|
|
" trap=%lx\n", mm, mm->pgd, ea, access, trap);
|
|
|
|
/* Get PTE, VSID, access mask */
|
|
pgdir = mm->pgd;
|
|
if (pgdir == NULL)
|
|
return;
|
|
ptep = find_linux_pte(pgdir, ea);
|
|
if (!ptep)
|
|
return;
|
|
vsid = get_vsid(mm->context.id, ea);
|
|
|
|
/* Hash it in */
|
|
local_irq_save(flags);
|
|
mask = cpumask_of_cpu(smp_processor_id());
|
|
if (cpus_equal(mm->cpu_vm_mask, mask))
|
|
local = 1;
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
__hash_page_4K(ea, access, vsid, ptep, trap, local);
|
|
#else
|
|
if (mmu_ci_restrictions) {
|
|
/* If this PTE is non-cacheable, switch to 4k */
|
|
if (mm->context.user_psize == MMU_PAGE_64K &&
|
|
(pte_val(*ptep) & _PAGE_NO_CACHE)) {
|
|
mm->context.user_psize = MMU_PAGE_4K;
|
|
mm->context.sllp = SLB_VSID_USER |
|
|
mmu_psize_defs[MMU_PAGE_4K].sllp;
|
|
get_paca()->context = mm->context;
|
|
slb_flush_and_rebolt();
|
|
}
|
|
}
|
|
if (mm->context.user_psize == MMU_PAGE_64K)
|
|
__hash_page_64K(ea, access, vsid, ptep, trap, local);
|
|
else
|
|
__hash_page_4K(ea, access, vsid, ptep, trap, local);
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int local)
|
|
{
|
|
unsigned long hash, index, shift, hidx, slot;
|
|
|
|
DBG_LOW("flush_hash_page(va=%016x)\n", va);
|
|
pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
|
|
hash = hpt_hash(va, shift);
|
|
hidx = __rpte_to_hidx(pte, index);
|
|
if (hidx & _PTEIDX_SECONDARY)
|
|
hash = ~hash;
|
|
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
|
|
slot += hidx & _PTEIDX_GROUP_IX;
|
|
DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
|
|
ppc_md.hpte_invalidate(slot, va, psize, local);
|
|
} pte_iterate_hashed_end();
|
|
}
|
|
|
|
void flush_hash_range(unsigned long number, int local)
|
|
{
|
|
if (ppc_md.flush_hash_range)
|
|
ppc_md.flush_hash_range(number, local);
|
|
else {
|
|
int i;
|
|
struct ppc64_tlb_batch *batch =
|
|
&__get_cpu_var(ppc64_tlb_batch);
|
|
|
|
for (i = 0; i < number; i++)
|
|
flush_hash_page(batch->vaddr[i], batch->pte[i],
|
|
batch->psize, local);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* low_hash_fault is called when we the low level hash code failed
|
|
* to instert a PTE due to an hypervisor error
|
|
*/
|
|
void low_hash_fault(struct pt_regs *regs, unsigned long address)
|
|
{
|
|
if (user_mode(regs)) {
|
|
siginfo_t info;
|
|
|
|
info.si_signo = SIGBUS;
|
|
info.si_errno = 0;
|
|
info.si_code = BUS_ADRERR;
|
|
info.si_addr = (void __user *)address;
|
|
force_sig_info(SIGBUS, &info, current);
|
|
return;
|
|
}
|
|
bad_page_fault(regs, address, SIGBUS);
|
|
}
|