mirror of https://gitee.com/openkylin/linux.git
283 lines
5.7 KiB
C
283 lines
5.7 KiB
C
#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <asm/processor-cyrix.h>
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#include <asm/processor-flags.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "mtrr.h"
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static void
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cyrix_get_arr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type * type)
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{
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unsigned char arr, ccr3, rcr, shift;
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unsigned long flags;
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arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
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local_irq_save(flags);
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
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((unsigned char *)base)[3] = getCx86(arr);
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((unsigned char *)base)[2] = getCx86(arr + 1);
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((unsigned char *)base)[1] = getCx86(arr + 2);
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rcr = getCx86(CX86_RCR_BASE + reg);
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setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
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local_irq_restore(flags);
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shift = ((unsigned char *) base)[1] & 0x0f;
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*base >>= PAGE_SHIFT;
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/*
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* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
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* Note: shift==0xf means 4G, this is unsupported.
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*/
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if (shift)
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*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
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else
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*size = 0;
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/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
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if (reg < 7) {
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switch (rcr) {
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case 1:
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*type = MTRR_TYPE_UNCACHABLE;
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break;
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case 8:
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*type = MTRR_TYPE_WRBACK;
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break;
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case 9:
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*type = MTRR_TYPE_WRCOMB;
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break;
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case 24:
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default:
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*type = MTRR_TYPE_WRTHROUGH;
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break;
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}
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} else {
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switch (rcr) {
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case 0:
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*type = MTRR_TYPE_UNCACHABLE;
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break;
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case 8:
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*type = MTRR_TYPE_WRCOMB;
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break;
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case 9:
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*type = MTRR_TYPE_WRBACK;
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break;
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case 25:
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default:
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*type = MTRR_TYPE_WRTHROUGH;
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break;
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}
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}
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}
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/*
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* cyrix_get_free_region - get a free ARR.
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*
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* @base: the starting (base) address of the region.
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* @size: the size (in bytes) of the region.
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*
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* Returns: the index of the region on success, else -1 on error.
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*/
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static int
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cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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{
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unsigned long lbase, lsize;
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mtrr_type ltype;
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int i;
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switch (replace_reg) {
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case 7:
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if (size < 0x40)
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break;
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case 6:
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case 5:
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case 4:
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return replace_reg;
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case 3:
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case 2:
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case 1:
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case 0:
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return replace_reg;
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}
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/* If we are to set up a region >32M then look at ARR7 immediately */
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if (size > 0x2000) {
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cyrix_get_arr(7, &lbase, &lsize, <ype);
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if (lsize == 0)
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return 7;
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/* Else try ARR0-ARR6 first */
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} else {
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for (i = 0; i < 7; i++) {
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cyrix_get_arr(i, &lbase, &lsize, <ype);
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if (lsize == 0)
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return i;
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}
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/*
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* ARR0-ARR6 isn't free
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* try ARR7 but its size must be at least 256K
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*/
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cyrix_get_arr(i, &lbase, &lsize, <ype);
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if ((lsize == 0) && (size >= 0x40))
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return i;
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}
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return -ENOSPC;
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}
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static u32 cr4, ccr3;
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static void prepare_set(void)
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{
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u32 cr0;
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if (cpu_has_pge) {
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cr4 = read_cr4();
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write_cr4(cr4 & ~X86_CR4_PGE);
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}
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/*
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* Disable and flush caches.
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* Note that wbinvd flushes the TLBs as a side-effect
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*/
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cr0 = read_cr0() | X86_CR0_CD;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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/* Cyrix ARRs - everything else was excluded at the top */
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ccr3 = getCx86(CX86_CCR3);
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/* Cyrix ARRs - everything else was excluded at the top */
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
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}
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static void post_set(void)
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{
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/* Flush caches and TLBs */
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wbinvd();
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/* Cyrix ARRs - everything else was excluded at the top */
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setCx86(CX86_CCR3, ccr3);
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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/* Restore value of CR4 */
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if (cpu_has_pge)
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write_cr4(cr4);
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}
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static void cyrix_set_arr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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{
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unsigned char arr, arr_type, arr_size;
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arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
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/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
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if (reg >= 7)
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size >>= 6;
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size &= 0x7fff; /* make sure arr_size <= 14 */
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for (arr_size = 0; size; arr_size++, size >>= 1)
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;
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if (reg < 7) {
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switch (type) {
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case MTRR_TYPE_UNCACHABLE:
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arr_type = 1;
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break;
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case MTRR_TYPE_WRCOMB:
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arr_type = 9;
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break;
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case MTRR_TYPE_WRTHROUGH:
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arr_type = 24;
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break;
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default:
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arr_type = 8;
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break;
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}
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} else {
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switch (type) {
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case MTRR_TYPE_UNCACHABLE:
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arr_type = 0;
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break;
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case MTRR_TYPE_WRCOMB:
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arr_type = 8;
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break;
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case MTRR_TYPE_WRTHROUGH:
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arr_type = 25;
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break;
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default:
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arr_type = 9;
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break;
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}
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}
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prepare_set();
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base <<= PAGE_SHIFT;
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setCx86(arr + 0, ((unsigned char *)&base)[3]);
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setCx86(arr + 1, ((unsigned char *)&base)[2]);
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setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size);
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setCx86(CX86_RCR_BASE + reg, arr_type);
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post_set();
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}
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typedef struct {
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unsigned long base;
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unsigned long size;
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mtrr_type type;
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} arr_state_t;
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static arr_state_t arr_state[8] = {
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{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
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{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
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};
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static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };
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static void cyrix_set_all(void)
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{
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int i;
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prepare_set();
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/* the CCRs are not contiguous */
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for (i = 0; i < 4; i++)
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setCx86(CX86_CCR0 + i, ccr_state[i]);
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for (; i < 7; i++)
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setCx86(CX86_CCR4 + i, ccr_state[i]);
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for (i = 0; i < 8; i++) {
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cyrix_set_arr(i, arr_state[i].base,
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arr_state[i].size, arr_state[i].type);
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}
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post_set();
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}
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static struct mtrr_ops cyrix_mtrr_ops = {
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.vendor = X86_VENDOR_CYRIX,
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.set_all = cyrix_set_all,
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.set = cyrix_set_arr,
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.get = cyrix_get_arr,
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.get_free_region = cyrix_get_free_region,
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.validate_add_page = generic_validate_add_page,
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.have_wrcomb = positive_have_wrcomb,
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};
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int __init cyrix_init_mtrr(void)
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{
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set_mtrr_ops(&cyrix_mtrr_ops);
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return 0;
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}
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