mirror of https://gitee.com/openkylin/linux.git
56713da3ee
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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| .. | ||
| Makefile | ||
| clk-gate-a10.c | ||
| clk-gate.c | ||
| clk-periph-a10.c | ||
| clk-periph.c | ||
| clk-pll-a10.c | ||
| clk-pll.c | ||
| clk.c | ||
| clk.h | ||