mirror of https://gitee.com/openkylin/linux.git
397 lines
10 KiB
C
397 lines
10 KiB
C
/*
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* arch/arm/mach-at91/at91cap9.c
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*
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* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
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* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2007 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/cpu.h>
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#include <mach/at91cap9.h>
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#include <mach/at91_pmc.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioABCD_clk = {
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.name = "pioABCD_clk",
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.pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mpb0_clk = {
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.name = "mpb0_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MPB0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mpb1_clk = {
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.name = "mpb1_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MPB1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mpb2_clk = {
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.name = "mpb2_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MPB2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mpb3_clk = {
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.name = "mpb3_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MPB3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mpb4_clk = {
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.name = "mpb4_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MPB4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91CAP9_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91CAP9_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91CAP9_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91CAP9_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk can_clk = {
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.name = "can_clk",
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.pmc_mask = 1 << AT91CAP9_ID_CAN,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91CAP9_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91CAP9_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91CAP9_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91CAP9_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91CAP9_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91CAP9_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb_clk = {
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.name = "tcb_clk",
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.pmc_mask = 1 << AT91CAP9_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91CAP9_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "pclk",
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.pmc_mask = 1 << AT91CAP9_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk aestdes_clk = {
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.name = "aestdes_clk",
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.pmc_mask = 1 << AT91CAP9_ID_AESTDES,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91CAP9_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91CAP9_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91CAP9_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91CAP9_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91CAP9_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91CAP9_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioABCD_clk,
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&mpb0_clk,
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&mpb1_clk,
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&mpb2_clk,
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&mpb3_clk,
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&mpb4_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc0_clk,
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&mmc1_clk,
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&can_clk,
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&ac97_clk,
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&tcb_clk,
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&pwm_clk,
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&macb_clk,
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&aestdes_clk,
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&adc_clk,
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&isi_clk,
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&lcdc_clk,
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&dma_clk,
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&udphs_clk,
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&ohci_clk,
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// irq0 .. irq1
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* One additional fake clock for macb_hclk */
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CLKDEV_CON_ID("hclk", &macb_clk),
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CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
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CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
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/* fake hclk clock */
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CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
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CLKDEV_CON_ID("pioA", &pioABCD_clk),
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CLKDEV_CON_ID("pioB", &pioABCD_clk),
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CLKDEV_CON_ID("pioC", &pioABCD_clk),
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CLKDEV_CON_ID("pioD", &pioABCD_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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};
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/*
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* The four programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 2,
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};
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static struct clk pck3 = {
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.name = "pck3",
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.pmc_mask = AT91_PMC_PCK3,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 3,
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};
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static void __init at91cap9_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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clk_register(&pck2);
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clk_register(&pck3);
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}
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static struct clk_lookup console_clock_lookup;
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void __init at91cap9_set_console_clock(int id)
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{
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if (id >= ARRAY_SIZE(usart_clocks_lookups))
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return;
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console_clock_lookup.con_id = "usart";
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console_clock_lookup.clk = usart_clocks_lookups[id].clk;
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clkdev_add(&console_clock_lookup);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
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{
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.id = AT91CAP9_ID_PIOABCD,
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.regbase = AT91CAP9_BASE_PIOA,
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}, {
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.id = AT91CAP9_ID_PIOABCD,
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.regbase = AT91CAP9_BASE_PIOB,
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}, {
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.id = AT91CAP9_ID_PIOABCD,
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.regbase = AT91CAP9_BASE_PIOC,
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}, {
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.id = AT91CAP9_ID_PIOABCD,
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.regbase = AT91CAP9_BASE_PIOD,
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}
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};
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/* --------------------------------------------------------------------
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* AT91CAP9 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91cap9_map_io(void)
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{
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at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
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}
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static void __init at91cap9_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
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at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
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at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
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}
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static void __init at91cap9_initialize(void)
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{
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arm_pm_restart = at91sam9g45_restart;
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at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
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/* Register GPIO subsystem */
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at91_gpio_init(at91cap9_gpio, 4);
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/* Remember the silicon revision */
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if (cpu_is_at91cap9_revB())
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system_rev = 0xB;
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else if (cpu_is_at91cap9_revC())
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system_rev = 0xC;
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A, B, C and D */
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0, /* MP Block Peripheral 0 */
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0, /* MP Block Peripheral 1 */
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0, /* MP Block Peripheral 2 */
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0, /* MP Block Peripheral 3 */
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0, /* MP Block Peripheral 4 */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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0, /* Multimedia Card Interface 0 */
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0, /* Multimedia Card Interface 1 */
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3, /* CAN */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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5, /* AC97 Controller */
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0, /* Timer Counter 0, 1 and 2 */
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0, /* Pulse Width Modulation Controller */
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3, /* Ethernet */
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0, /* Advanced Encryption Standard, Triple DES*/
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0, /* Analog-to-Digital Converter */
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0, /* Image Sensor Interface */
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3, /* LCD Controller */
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0, /* DMA Controller */
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2, /* USB Device Port */
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2, /* USB Host port */
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0, /* Advanced Interrupt Controller (IRQ0) */
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0, /* Advanced Interrupt Controller (IRQ1) */
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};
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struct at91_init_soc __initdata at91cap9_soc = {
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.map_io = at91cap9_map_io,
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.default_irq_priority = at91cap9_default_irq_priority,
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.ioremap_registers = at91cap9_ioremap_registers,
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.register_clocks = at91cap9_register_clocks,
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.init = at91cap9_initialize,
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};
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