mirror of https://gitee.com/openkylin/linux.git
495 lines
12 KiB
C
495 lines
12 KiB
C
/*
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* Platform CAN bus driver for Bosch C_CAN controller
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*
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* Copyright (C) 2010 ST Microelectronics
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* Bhupesh Sharma <bhupesh.sharma@st.com>
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*
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* Borrowed heavily from the C_CAN driver originally written by:
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* Copyright (C) 2007
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* - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
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* - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
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*
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* Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
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* Bosch C_CAN user manual can be obtained from:
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* http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
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* users_manual_c_can.pdf
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/if_arp.h>
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#include <linux/if_ether.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/can/dev.h>
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#include "c_can.h"
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#define DCAN_RAM_INIT_BIT BIT(3)
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static DEFINE_SPINLOCK(raminit_lock);
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/* 16-bit c_can registers can be arranged differently in the memory
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* architecture of different implementations. For example: 16-bit
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* registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
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* Handle the same by providing a common read/write interface.
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*/
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static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
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enum reg index)
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{
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return readw(priv->base + priv->regs[index]);
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}
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static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
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enum reg index, u16 val)
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{
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writew(val, priv->base + priv->regs[index]);
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}
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static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
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enum reg index)
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{
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return readw(priv->base + 2 * priv->regs[index]);
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}
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static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
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enum reg index, u16 val)
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{
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writew(val, priv->base + 2 * priv->regs[index]);
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}
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static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
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u32 mask, u32 val)
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{
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const struct c_can_raminit *raminit = &priv->raminit_sys;
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int timeout = 0;
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u32 ctrl = 0;
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/* We look only at the bits of our instance. */
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val &= mask;
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do {
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udelay(1);
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timeout++;
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regmap_read(raminit->syscon, raminit->reg, &ctrl);
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if (timeout == 1000) {
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dev_err(&priv->dev->dev, "%s: time out\n", __func__);
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break;
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}
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} while ((ctrl & mask) != val);
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}
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static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
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{
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const struct c_can_raminit *raminit = &priv->raminit_sys;
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u32 ctrl = 0;
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u32 mask;
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spin_lock(&raminit_lock);
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mask = 1 << raminit->bits.start | 1 << raminit->bits.done;
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regmap_read(raminit->syscon, raminit->reg, &ctrl);
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/* We clear the start bit first. The start bit is
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* looking at the 0 -> transition, but is not self clearing;
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* NOTE: DONE must be written with 1 to clear it.
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* We can't clear the DONE bit here using regmap_update_bits()
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* as it will bypass the write if initial condition is START:0 DONE:1
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* e.g. on DRA7 which needs START pulse.
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*/
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ctrl &= ~mask; /* START = 0, DONE = 0 */
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regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
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/* check if START bit is 0. Ignore DONE bit for now
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* as it can be either 0 or 1.
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*/
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c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl);
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if (enable) {
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/* Clear DONE bit & set START bit. */
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ctrl |= 1 << raminit->bits.start;
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/* DONE must be written with 1 to clear it */
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ctrl |= 1 << raminit->bits.done;
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regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
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/* prevent further clearing of DONE bit */
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ctrl &= ~(1 << raminit->bits.done);
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/* clear START bit if start pulse is needed */
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if (raminit->needs_pulse) {
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ctrl &= ~(1 << raminit->bits.start);
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regmap_update_bits(raminit->syscon, raminit->reg,
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mask, ctrl);
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}
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ctrl |= 1 << raminit->bits.done;
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c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
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}
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spin_unlock(&raminit_lock);
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}
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static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
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{
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u32 val;
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val = priv->read_reg(priv, index);
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val |= ((u32)priv->read_reg(priv, index + 1)) << 16;
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return val;
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}
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static void c_can_plat_write_reg32(const struct c_can_priv *priv,
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enum reg index, u32 val)
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{
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priv->write_reg(priv, index + 1, val >> 16);
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priv->write_reg(priv, index, val);
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}
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static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
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{
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return readl(priv->base + priv->regs[index]);
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}
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static void d_can_plat_write_reg32(const struct c_can_priv *priv,
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enum reg index, u32 val)
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{
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writel(val, priv->base + priv->regs[index]);
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}
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static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
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{
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while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
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udelay(1);
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}
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static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
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{
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u32 ctrl;
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ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
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ctrl &= ~DCAN_RAM_INIT_BIT;
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priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
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c_can_hw_raminit_wait(priv, ctrl);
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if (enable) {
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ctrl |= DCAN_RAM_INIT_BIT;
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priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
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c_can_hw_raminit_wait(priv, ctrl);
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}
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}
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static const struct c_can_driver_data c_can_drvdata = {
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.id = BOSCH_C_CAN,
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};
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static const struct c_can_driver_data d_can_drvdata = {
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.id = BOSCH_D_CAN,
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};
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static const struct raminit_bits dra7_raminit_bits[] = {
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[0] = { .start = 3, .done = 1, },
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[1] = { .start = 5, .done = 2, },
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};
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static const struct c_can_driver_data dra7_dcan_drvdata = {
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.id = BOSCH_D_CAN,
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.raminit_num = ARRAY_SIZE(dra7_raminit_bits),
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.raminit_bits = dra7_raminit_bits,
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.raminit_pulse = true,
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};
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static const struct raminit_bits am3352_raminit_bits[] = {
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[0] = { .start = 0, .done = 8, },
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[1] = { .start = 1, .done = 9, },
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};
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static const struct c_can_driver_data am3352_dcan_drvdata = {
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.id = BOSCH_D_CAN,
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.raminit_num = ARRAY_SIZE(am3352_raminit_bits),
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.raminit_bits = am3352_raminit_bits,
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};
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static const struct platform_device_id c_can_id_table[] = {
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{
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.name = KBUILD_MODNAME,
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.driver_data = (kernel_ulong_t)&c_can_drvdata,
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},
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{
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.name = "c_can",
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.driver_data = (kernel_ulong_t)&c_can_drvdata,
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},
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{
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.name = "d_can",
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.driver_data = (kernel_ulong_t)&d_can_drvdata,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(platform, c_can_id_table);
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static const struct of_device_id c_can_of_table[] = {
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{ .compatible = "bosch,c_can", .data = &c_can_drvdata },
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{ .compatible = "bosch,d_can", .data = &d_can_drvdata },
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{ .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
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{ .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
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{ .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, c_can_of_table);
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static int c_can_plat_probe(struct platform_device *pdev)
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{
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int ret;
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void __iomem *addr;
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struct net_device *dev;
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struct c_can_priv *priv;
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const struct of_device_id *match;
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struct resource *mem;
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int irq;
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struct clk *clk;
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const struct c_can_driver_data *drvdata;
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struct device_node *np = pdev->dev.of_node;
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match = of_match_device(c_can_of_table, &pdev->dev);
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if (match) {
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drvdata = match->data;
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} else if (pdev->id_entry->driver_data) {
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drvdata = (struct c_can_driver_data *)
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platform_get_device_id(pdev)->driver_data;
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} else {
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return -ENODEV;
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}
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/* get the appropriate clk */
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto exit;
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}
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/* get the platform data */
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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ret = -ENODEV;
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goto exit;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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addr = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(addr)) {
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ret = PTR_ERR(addr);
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goto exit;
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}
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/* allocate the c_can device */
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dev = alloc_c_can_dev();
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if (!dev) {
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ret = -ENOMEM;
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goto exit;
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}
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priv = netdev_priv(dev);
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switch (drvdata->id) {
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case BOSCH_C_CAN:
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priv->regs = reg_map_c_can;
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switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
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case IORESOURCE_MEM_32BIT:
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priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
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priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
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priv->read_reg32 = c_can_plat_read_reg32;
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priv->write_reg32 = c_can_plat_write_reg32;
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break;
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case IORESOURCE_MEM_16BIT:
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default:
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priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
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priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
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priv->read_reg32 = c_can_plat_read_reg32;
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priv->write_reg32 = c_can_plat_write_reg32;
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break;
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}
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break;
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case BOSCH_D_CAN:
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priv->regs = reg_map_d_can;
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priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
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priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
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priv->read_reg32 = d_can_plat_read_reg32;
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priv->write_reg32 = d_can_plat_write_reg32;
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/* Check if we need custom RAMINIT via syscon. Mostly for TI
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* platforms. Only supported with DT boot.
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*/
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if (np && of_property_read_bool(np, "syscon-raminit")) {
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u32 id;
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struct c_can_raminit *raminit = &priv->raminit_sys;
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ret = -EINVAL;
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raminit->syscon = syscon_regmap_lookup_by_phandle(np,
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"syscon-raminit");
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if (IS_ERR(raminit->syscon)) {
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/* can fail with -EPROBE_DEFER */
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ret = PTR_ERR(raminit->syscon);
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free_c_can_dev(dev);
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return ret;
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}
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if (of_property_read_u32_index(np, "syscon-raminit", 1,
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&raminit->reg)) {
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dev_err(&pdev->dev,
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"couldn't get the RAMINIT reg. offset!\n");
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goto exit_free_device;
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}
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if (of_property_read_u32_index(np, "syscon-raminit", 2,
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&id)) {
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dev_err(&pdev->dev,
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"couldn't get the CAN instance ID\n");
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goto exit_free_device;
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}
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if (id >= drvdata->raminit_num) {
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dev_err(&pdev->dev,
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"Invalid CAN instance ID\n");
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goto exit_free_device;
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}
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raminit->bits = drvdata->raminit_bits[id];
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raminit->needs_pulse = drvdata->raminit_pulse;
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priv->raminit = c_can_hw_raminit_syscon;
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} else {
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priv->raminit = c_can_hw_raminit;
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}
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break;
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default:
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ret = -EINVAL;
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goto exit_free_device;
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}
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dev->irq = irq;
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priv->base = addr;
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priv->device = &pdev->dev;
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priv->can.clock.freq = clk_get_rate(clk);
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priv->priv = clk;
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priv->type = drvdata->id;
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platform_set_drvdata(pdev, dev);
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SET_NETDEV_DEV(dev, &pdev->dev);
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ret = register_c_can_dev(dev);
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if (ret) {
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dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
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KBUILD_MODNAME, ret);
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goto exit_free_device;
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}
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dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
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KBUILD_MODNAME, priv->base, dev->irq);
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return 0;
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exit_free_device:
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free_c_can_dev(dev);
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exit:
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dev_err(&pdev->dev, "probe failed\n");
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return ret;
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}
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static int c_can_plat_remove(struct platform_device *pdev)
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{
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struct net_device *dev = platform_get_drvdata(pdev);
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unregister_c_can_dev(dev);
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free_c_can_dev(dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
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{
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int ret;
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct c_can_priv *priv = netdev_priv(ndev);
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if (priv->type != BOSCH_D_CAN) {
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dev_warn(&pdev->dev, "Not supported\n");
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return 0;
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}
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if (netif_running(ndev)) {
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netif_stop_queue(ndev);
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netif_device_detach(ndev);
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}
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ret = c_can_power_down(ndev);
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if (ret) {
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netdev_err(ndev, "failed to enter power down mode\n");
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return ret;
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}
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priv->can.state = CAN_STATE_SLEEPING;
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return 0;
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}
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static int c_can_resume(struct platform_device *pdev)
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{
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int ret;
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct c_can_priv *priv = netdev_priv(ndev);
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if (priv->type != BOSCH_D_CAN) {
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dev_warn(&pdev->dev, "Not supported\n");
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return 0;
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}
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ret = c_can_power_up(ndev);
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if (ret) {
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netdev_err(ndev, "Still in power down mode\n");
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return ret;
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}
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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if (netif_running(ndev)) {
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netif_device_attach(ndev);
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netif_start_queue(ndev);
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}
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return 0;
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}
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#else
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#define c_can_suspend NULL
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#define c_can_resume NULL
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#endif
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static struct platform_driver c_can_plat_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = c_can_of_table,
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},
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.probe = c_can_plat_probe,
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.remove = c_can_plat_remove,
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.suspend = c_can_suspend,
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.resume = c_can_resume,
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.id_table = c_can_id_table,
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};
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module_platform_driver(c_can_plat_driver);
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MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
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