mirror of https://gitee.com/openkylin/linux.git
1897 lines
49 KiB
C
1897 lines
49 KiB
C
/*
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* IOMMU API for ARM architected SMMU implementations.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2013 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*
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* This driver currently supports:
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* - SMMUv1 and v2 implementations
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* - Stream-matching and stream-indexing
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* - v7/v8 long-descriptor format
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* - Non-secure access to the SMMU
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* - Context fault reporting
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*/
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#define pr_fmt(fmt) "arm-smmu: " fmt
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/amba/bus.h>
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#include "io-pgtable.h"
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/* Maximum number of stream IDs assigned to a single device */
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#define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
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/* Maximum number of context banks per SMMU */
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#define ARM_SMMU_MAX_CBS 128
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/* Maximum number of mapping groups per SMMU */
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#define ARM_SMMU_MAX_SMRS 128
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/* SMMU global address space */
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#define ARM_SMMU_GR0(smmu) ((smmu)->base)
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#define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
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/*
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* SMMU global address space with conditional offset to access secure
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* aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
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* nsGFSYNR0: 0x450)
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*/
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#define ARM_SMMU_GR0_NS(smmu) \
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((smmu)->base + \
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((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
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? 0x400 : 0))
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/* Configuration registers */
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#define ARM_SMMU_GR0_sCR0 0x0
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#define sCR0_CLIENTPD (1 << 0)
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#define sCR0_GFRE (1 << 1)
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#define sCR0_GFIE (1 << 2)
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#define sCR0_GCFGFRE (1 << 4)
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#define sCR0_GCFGFIE (1 << 5)
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#define sCR0_USFCFG (1 << 10)
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#define sCR0_VMIDPNE (1 << 11)
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#define sCR0_PTM (1 << 12)
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#define sCR0_FB (1 << 13)
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#define sCR0_BSU_SHIFT 14
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#define sCR0_BSU_MASK 0x3
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/* Identification registers */
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#define ARM_SMMU_GR0_ID0 0x20
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#define ARM_SMMU_GR0_ID1 0x24
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#define ARM_SMMU_GR0_ID2 0x28
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#define ARM_SMMU_GR0_ID3 0x2c
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#define ARM_SMMU_GR0_ID4 0x30
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#define ARM_SMMU_GR0_ID5 0x34
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#define ARM_SMMU_GR0_ID6 0x38
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#define ARM_SMMU_GR0_ID7 0x3c
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#define ARM_SMMU_GR0_sGFSR 0x48
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#define ARM_SMMU_GR0_sGFSYNR0 0x50
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#define ARM_SMMU_GR0_sGFSYNR1 0x54
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#define ARM_SMMU_GR0_sGFSYNR2 0x58
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#define ID0_S1TS (1 << 30)
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#define ID0_S2TS (1 << 29)
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#define ID0_NTS (1 << 28)
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#define ID0_SMS (1 << 27)
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#define ID0_ATOSNS (1 << 26)
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#define ID0_CTTW (1 << 14)
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#define ID0_NUMIRPT_SHIFT 16
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMSIDB_SHIFT 9
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#define ID0_NUMSIDB_MASK 0xf
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_MASK 0xff
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#define ID1_PAGESIZE (1 << 31)
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#define ID1_NUMPAGENDXB_SHIFT 28
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#define ID1_NUMPAGENDXB_MASK 7
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#define ID1_NUMS2CB_SHIFT 16
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#define ID1_NUMS2CB_MASK 0xff
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#define ID1_NUMCB_SHIFT 0
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#define ID1_NUMCB_MASK 0xff
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#define ID2_OAS_SHIFT 4
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#define ID2_OAS_MASK 0xf
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#define ID2_IAS_SHIFT 0
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#define ID2_IAS_MASK 0xf
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#define ID2_UBS_SHIFT 8
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#define ID2_UBS_MASK 0xf
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#define ID2_PTFS_4K (1 << 12)
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#define ID2_PTFS_16K (1 << 13)
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#define ID2_PTFS_64K (1 << 14)
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/* Global TLB invalidation */
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#define ARM_SMMU_GR0_TLBIVMID 0x64
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#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
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#define ARM_SMMU_GR0_TLBIALLH 0x6c
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#define ARM_SMMU_GR0_sTLBGSYNC 0x70
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#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
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#define sTLBGSTATUS_GSACTIVE (1 << 0)
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#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
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/* Stream mapping registers */
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#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
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#define SMR_VALID (1 << 31)
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#define SMR_MASK_SHIFT 16
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#define SMR_MASK_MASK 0x7fff
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#define SMR_ID_SHIFT 0
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#define SMR_ID_MASK 0x7fff
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#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
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#define S2CR_CBNDX_SHIFT 0
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#define S2CR_CBNDX_MASK 0xff
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#define S2CR_TYPE_SHIFT 16
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#define S2CR_TYPE_MASK 0x3
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#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
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#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
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#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
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/* Context bank attribute registers */
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#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
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#define CBAR_VMID_SHIFT 0
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#define CBAR_VMID_MASK 0xff
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#define CBAR_S1_BPSHCFG_SHIFT 8
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#define CBAR_S1_BPSHCFG_MASK 3
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#define CBAR_S1_BPSHCFG_NSH 3
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#define CBAR_S1_MEMATTR_SHIFT 12
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#define CBAR_S1_MEMATTR_MASK 0xf
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#define CBAR_S1_MEMATTR_WB 0xf
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#define CBAR_TYPE_SHIFT 16
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#define CBAR_TYPE_MASK 0x3
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#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
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#define CBAR_IRPTNDX_SHIFT 24
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#define CBAR_IRPTNDX_MASK 0xff
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#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
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#define CBA2R_RW64_32BIT (0 << 0)
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#define CBA2R_RW64_64BIT (1 << 0)
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/* Translation context bank */
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#define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
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#define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
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#define ARM_SMMU_CB_SCTLR 0x0
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#define ARM_SMMU_CB_RESUME 0x8
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#define ARM_SMMU_CB_TTBCR2 0x10
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#define ARM_SMMU_CB_TTBR0_LO 0x20
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#define ARM_SMMU_CB_TTBR0_HI 0x24
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#define ARM_SMMU_CB_TTBR1_LO 0x28
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#define ARM_SMMU_CB_TTBR1_HI 0x2c
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#define ARM_SMMU_CB_TTBCR 0x30
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#define ARM_SMMU_CB_S1_MAIR0 0x38
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#define ARM_SMMU_CB_S1_MAIR1 0x3c
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#define ARM_SMMU_CB_PAR_LO 0x50
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#define ARM_SMMU_CB_PAR_HI 0x54
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#define ARM_SMMU_CB_FSR 0x58
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#define ARM_SMMU_CB_FAR_LO 0x60
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#define ARM_SMMU_CB_FAR_HI 0x64
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define ARM_SMMU_CB_S1_TLBIVA 0x600
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#define ARM_SMMU_CB_S1_TLBIASID 0x610
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#define ARM_SMMU_CB_S1_TLBIVAL 0x620
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#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
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#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
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#define ARM_SMMU_CB_ATS1PR_LO 0x800
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#define ARM_SMMU_CB_ATS1PR_HI 0x804
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#define ARM_SMMU_CB_ATSR 0x8f0
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#define SCTLR_S1_ASIDPNE (1 << 12)
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#define SCTLR_CFCFG (1 << 7)
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#define SCTLR_CFIE (1 << 6)
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#define SCTLR_CFRE (1 << 5)
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#define SCTLR_E (1 << 4)
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#define SCTLR_AFE (1 << 2)
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#define SCTLR_TRE (1 << 1)
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#define SCTLR_M (1 << 0)
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#define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
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#define CB_PAR_F (1 << 0)
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#define ATSR_ACTIVE (1 << 0)
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#define RESUME_RETRY (0 << 0)
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#define RESUME_TERMINATE (1 << 0)
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_MASK 0x7
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#define TTBCR2_ADDR_32 0
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#define TTBCR2_ADDR_36 1
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#define TTBCR2_ADDR_40 2
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#define TTBCR2_ADDR_42 3
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#define TTBCR2_ADDR_44 4
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#define TTBCR2_ADDR_48 5
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#define TTBRn_HI_ASID_SHIFT 16
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#define FSR_MULTI (1 << 31)
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#define FSR_SS (1 << 30)
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#define FSR_UUT (1 << 8)
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#define FSR_ASF (1 << 7)
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#define FSR_TLBLKF (1 << 6)
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#define FSR_TLBMCF (1 << 5)
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#define FSR_EF (1 << 4)
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#define FSR_PF (1 << 3)
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#define FSR_AFF (1 << 2)
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#define FSR_TF (1 << 1)
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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FSR_TLBMCF | FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define FSYNR0_WNR (1 << 4)
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static int force_stage;
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module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(force_stage,
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"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
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enum arm_smmu_arch_version {
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ARM_SMMU_V1 = 1,
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ARM_SMMU_V2,
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};
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struct arm_smmu_smr {
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u8 idx;
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u16 mask;
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u16 id;
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};
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struct arm_smmu_master_cfg {
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int num_streamids;
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u16 streamids[MAX_MASTER_STREAMIDS];
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struct arm_smmu_smr *smrs;
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};
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struct arm_smmu_master {
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struct device_node *of_node;
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struct rb_node node;
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struct arm_smmu_master_cfg cfg;
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};
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struct arm_smmu_device {
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struct device *dev;
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void __iomem *base;
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unsigned long size;
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unsigned long pgshift;
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#define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
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#define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
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#define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
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#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
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#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
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#define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
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u32 features;
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#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
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u32 options;
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enum arm_smmu_arch_version version;
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u32 num_context_banks;
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u32 num_s2_context_banks;
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DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
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atomic_t irptndx;
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u32 num_mapping_groups;
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DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
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unsigned long va_size;
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unsigned long ipa_size;
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unsigned long pa_size;
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u32 num_global_irqs;
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u32 num_context_irqs;
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unsigned int *irqs;
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struct list_head list;
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struct rb_root masters;
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};
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struct arm_smmu_cfg {
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u8 cbndx;
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u8 irptndx;
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u32 cbar;
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};
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#define INVALID_IRPTNDX 0xff
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#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
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#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
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enum arm_smmu_domain_stage {
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ARM_SMMU_DOMAIN_S1 = 0,
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ARM_SMMU_DOMAIN_S2,
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ARM_SMMU_DOMAIN_NESTED,
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};
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struct arm_smmu_domain {
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struct arm_smmu_device *smmu;
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struct io_pgtable_ops *pgtbl_ops;
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spinlock_t pgtbl_lock;
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struct arm_smmu_cfg cfg;
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enum arm_smmu_domain_stage stage;
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struct mutex init_mutex; /* Protects smmu pointer */
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};
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static struct iommu_ops arm_smmu_ops;
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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
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static LIST_HEAD(arm_smmu_devices);
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struct arm_smmu_option_prop {
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u32 opt;
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const char *prop;
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};
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static struct arm_smmu_option_prop arm_smmu_options[] = {
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{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
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{ 0, NULL},
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};
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static void parse_driver_options(struct arm_smmu_device *smmu)
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{
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int i = 0;
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do {
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if (of_property_read_bool(smmu->dev->of_node,
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arm_smmu_options[i].prop)) {
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smmu->options |= arm_smmu_options[i].opt;
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dev_notice(smmu->dev, "option %s\n",
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arm_smmu_options[i].prop);
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}
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} while (arm_smmu_options[++i].opt);
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}
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static struct device_node *dev_get_dev_node(struct device *dev)
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{
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if (dev_is_pci(dev)) {
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struct pci_bus *bus = to_pci_dev(dev)->bus;
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while (!pci_is_root_bus(bus))
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bus = bus->parent;
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return bus->bridge->parent->of_node;
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}
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return dev->of_node;
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}
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static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
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struct device_node *dev_node)
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{
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struct rb_node *node = smmu->masters.rb_node;
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while (node) {
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struct arm_smmu_master *master;
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master = container_of(node, struct arm_smmu_master, node);
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if (dev_node < master->of_node)
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node = node->rb_left;
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else if (dev_node > master->of_node)
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node = node->rb_right;
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else
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return master;
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}
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return NULL;
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}
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static struct arm_smmu_master_cfg *
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find_smmu_master_cfg(struct device *dev)
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{
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struct arm_smmu_master_cfg *cfg = NULL;
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struct iommu_group *group = iommu_group_get(dev);
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if (group) {
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cfg = iommu_group_get_iommudata(group);
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iommu_group_put(group);
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}
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return cfg;
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}
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static int insert_smmu_master(struct arm_smmu_device *smmu,
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struct arm_smmu_master *master)
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{
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struct rb_node **new, *parent;
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new = &smmu->masters.rb_node;
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parent = NULL;
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while (*new) {
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struct arm_smmu_master *this
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= container_of(*new, struct arm_smmu_master, node);
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parent = *new;
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if (master->of_node < this->of_node)
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new = &((*new)->rb_left);
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else if (master->of_node > this->of_node)
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new = &((*new)->rb_right);
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else
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return -EEXIST;
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}
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rb_link_node(&master->node, parent, new);
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rb_insert_color(&master->node, &smmu->masters);
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return 0;
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}
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static int register_smmu_master(struct arm_smmu_device *smmu,
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struct device *dev,
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struct of_phandle_args *masterspec)
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{
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int i;
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struct arm_smmu_master *master;
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master = find_smmu_master(smmu, masterspec->np);
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if (master) {
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dev_err(dev,
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"rejecting multiple registrations for master device %s\n",
|
|
masterspec->np->name);
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
|
|
dev_err(dev,
|
|
"reached maximum number (%d) of stream IDs for master device %s\n",
|
|
MAX_MASTER_STREAMIDS, masterspec->np->name);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
master->of_node = masterspec->np;
|
|
master->cfg.num_streamids = masterspec->args_count;
|
|
|
|
for (i = 0; i < master->cfg.num_streamids; ++i) {
|
|
u16 streamid = masterspec->args[i];
|
|
|
|
if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
|
|
(streamid >= smmu->num_mapping_groups)) {
|
|
dev_err(dev,
|
|
"stream ID for master device %s greater than maximum allowed (%d)\n",
|
|
masterspec->np->name, smmu->num_mapping_groups);
|
|
return -ERANGE;
|
|
}
|
|
master->cfg.streamids[i] = streamid;
|
|
}
|
|
return insert_smmu_master(smmu, master);
|
|
}
|
|
|
|
static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
|
|
{
|
|
struct arm_smmu_device *smmu;
|
|
struct arm_smmu_master *master = NULL;
|
|
struct device_node *dev_node = dev_get_dev_node(dev);
|
|
|
|
spin_lock(&arm_smmu_devices_lock);
|
|
list_for_each_entry(smmu, &arm_smmu_devices, list) {
|
|
master = find_smmu_master(smmu, dev_node);
|
|
if (master)
|
|
break;
|
|
}
|
|
spin_unlock(&arm_smmu_devices_lock);
|
|
|
|
return master ? smmu : NULL;
|
|
}
|
|
|
|
static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
|
|
{
|
|
int idx;
|
|
|
|
do {
|
|
idx = find_next_zero_bit(map, end, start);
|
|
if (idx == end)
|
|
return -ENOSPC;
|
|
} while (test_and_set_bit(idx, map));
|
|
|
|
return idx;
|
|
}
|
|
|
|
static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
|
|
{
|
|
clear_bit(idx, map);
|
|
}
|
|
|
|
/* Wait for any pending TLB invalidations to complete */
|
|
static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
|
|
{
|
|
int count = 0;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
|
|
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
|
|
while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
|
|
& sTLBGSTATUS_GSACTIVE) {
|
|
cpu_relax();
|
|
if (++count == TLB_LOOP_TIMEOUT) {
|
|
dev_err_ratelimited(smmu->dev,
|
|
"TLB sync timed out -- SMMU may be deadlocked\n");
|
|
return;
|
|
}
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
static void arm_smmu_tlb_sync(void *cookie)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = cookie;
|
|
__arm_smmu_tlb_sync(smmu_domain->smmu);
|
|
}
|
|
|
|
static void arm_smmu_tlb_inv_context(void *cookie)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = cookie;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
|
|
void __iomem *base;
|
|
|
|
if (stage1) {
|
|
base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
writel_relaxed(ARM_SMMU_CB_ASID(cfg),
|
|
base + ARM_SMMU_CB_S1_TLBIASID);
|
|
} else {
|
|
base = ARM_SMMU_GR0(smmu);
|
|
writel_relaxed(ARM_SMMU_CB_VMID(cfg),
|
|
base + ARM_SMMU_GR0_TLBIVMID);
|
|
}
|
|
|
|
__arm_smmu_tlb_sync(smmu);
|
|
}
|
|
|
|
static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
|
|
bool leaf, void *cookie)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = cookie;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
|
|
void __iomem *reg;
|
|
|
|
if (stage1) {
|
|
reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
|
|
|
|
if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
|
|
iova &= ~12UL;
|
|
iova |= ARM_SMMU_CB_ASID(cfg);
|
|
writel_relaxed(iova, reg);
|
|
#ifdef CONFIG_64BIT
|
|
} else {
|
|
iova >>= 12;
|
|
iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
|
|
writeq_relaxed(iova, reg);
|
|
#endif
|
|
}
|
|
#ifdef CONFIG_64BIT
|
|
} else if (smmu->version == ARM_SMMU_V2) {
|
|
reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
|
|
ARM_SMMU_CB_S2_TLBIIPAS2;
|
|
writeq_relaxed(iova >> 12, reg);
|
|
#endif
|
|
} else {
|
|
reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
|
|
writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
|
|
}
|
|
}
|
|
|
|
static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = cookie;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
|
|
|
|
|
|
/* Ensure new page tables are visible to the hardware walker */
|
|
if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
|
|
dsb(ishst);
|
|
} else {
|
|
/*
|
|
* If the SMMU can't walk tables in the CPU caches, treat them
|
|
* like non-coherent DMA since we need to flush the new entries
|
|
* all the way out to memory. There's no possibility of
|
|
* recursion here as the SMMU table walker will not be wired
|
|
* through another SMMU.
|
|
*/
|
|
dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
|
|
DMA_TO_DEVICE);
|
|
}
|
|
}
|
|
|
|
static struct iommu_gather_ops arm_smmu_gather_ops = {
|
|
.tlb_flush_all = arm_smmu_tlb_inv_context,
|
|
.tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
|
|
.tlb_sync = arm_smmu_tlb_sync,
|
|
.flush_pgtable = arm_smmu_flush_pgtable,
|
|
};
|
|
|
|
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
|
|
{
|
|
int flags, ret;
|
|
u32 fsr, far, fsynr, resume;
|
|
unsigned long iova;
|
|
struct iommu_domain *domain = dev;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
void __iomem *cb_base;
|
|
|
|
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
|
|
|
|
if (!(fsr & FSR_FAULT))
|
|
return IRQ_NONE;
|
|
|
|
if (fsr & FSR_IGN)
|
|
dev_err_ratelimited(smmu->dev,
|
|
"Unexpected context fault (fsr 0x%x)\n",
|
|
fsr);
|
|
|
|
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
|
|
flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
|
|
|
|
far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
|
|
iova = far;
|
|
#ifdef CONFIG_64BIT
|
|
far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
|
|
iova |= ((unsigned long)far << 32);
|
|
#endif
|
|
|
|
if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
|
|
ret = IRQ_HANDLED;
|
|
resume = RESUME_RETRY;
|
|
} else {
|
|
dev_err_ratelimited(smmu->dev,
|
|
"Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
|
|
iova, fsynr, cfg->cbndx);
|
|
ret = IRQ_NONE;
|
|
resume = RESUME_TERMINATE;
|
|
}
|
|
|
|
/* Clear the faulting FSR */
|
|
writel(fsr, cb_base + ARM_SMMU_CB_FSR);
|
|
|
|
/* Retry or terminate any stalled transactions */
|
|
if (fsr & FSR_SS)
|
|
writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
|
|
{
|
|
u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
|
|
struct arm_smmu_device *smmu = dev;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
|
|
|
|
gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
|
|
gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
|
|
gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
|
|
gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
|
|
|
|
if (!gfsr)
|
|
return IRQ_NONE;
|
|
|
|
dev_err_ratelimited(smmu->dev,
|
|
"Unexpected global fault, this could be serious\n");
|
|
dev_err_ratelimited(smmu->dev,
|
|
"\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
|
|
gfsr, gfsynr0, gfsynr1, gfsynr2);
|
|
|
|
writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
|
|
struct io_pgtable_cfg *pgtbl_cfg)
|
|
{
|
|
u32 reg;
|
|
bool stage1;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
void __iomem *cb_base, *gr0_base, *gr1_base;
|
|
|
|
gr0_base = ARM_SMMU_GR0(smmu);
|
|
gr1_base = ARM_SMMU_GR1(smmu);
|
|
stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
|
|
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
|
|
/* CBAR */
|
|
reg = cfg->cbar;
|
|
if (smmu->version == ARM_SMMU_V1)
|
|
reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
|
|
|
|
/*
|
|
* Use the weakest shareability/memory types, so they are
|
|
* overridden by the ttbcr/pte.
|
|
*/
|
|
if (stage1) {
|
|
reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
|
|
(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
|
|
} else {
|
|
reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
|
|
}
|
|
writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
|
|
|
|
if (smmu->version > ARM_SMMU_V1) {
|
|
/* CBA2R */
|
|
#ifdef CONFIG_64BIT
|
|
reg = CBA2R_RW64_64BIT;
|
|
#else
|
|
reg = CBA2R_RW64_32BIT;
|
|
#endif
|
|
writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
|
|
}
|
|
|
|
/* TTBRs */
|
|
if (stage1) {
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32;
|
|
reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
|
|
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32;
|
|
reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);
|
|
} else {
|
|
reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
|
|
reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
|
|
}
|
|
|
|
/* TTBCR */
|
|
if (stage1) {
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
|
|
if (smmu->version > ARM_SMMU_V1) {
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
|
|
switch (smmu->va_size) {
|
|
case 32:
|
|
reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
|
|
break;
|
|
case 36:
|
|
reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
|
|
break;
|
|
case 40:
|
|
reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
|
|
break;
|
|
case 42:
|
|
reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
|
|
break;
|
|
case 44:
|
|
reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
|
|
break;
|
|
case 48:
|
|
reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
|
|
break;
|
|
}
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
|
|
}
|
|
} else {
|
|
reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
|
|
}
|
|
|
|
/* MAIRs (stage-1 only) */
|
|
if (stage1) {
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
|
|
reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
|
|
}
|
|
|
|
/* SCTLR */
|
|
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
|
|
if (stage1)
|
|
reg |= SCTLR_S1_ASIDPNE;
|
|
#ifdef __BIG_ENDIAN
|
|
reg |= SCTLR_E;
|
|
#endif
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
|
|
}
|
|
|
|
static int arm_smmu_init_domain_context(struct iommu_domain *domain,
|
|
struct arm_smmu_device *smmu)
|
|
{
|
|
int irq, start, ret = 0;
|
|
unsigned long ias, oas;
|
|
struct io_pgtable_ops *pgtbl_ops;
|
|
struct io_pgtable_cfg pgtbl_cfg;
|
|
enum io_pgtable_fmt fmt;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
|
|
mutex_lock(&smmu_domain->init_mutex);
|
|
if (smmu_domain->smmu)
|
|
goto out_unlock;
|
|
|
|
/*
|
|
* Mapping the requested stage onto what we support is surprisingly
|
|
* complicated, mainly because the spec allows S1+S2 SMMUs without
|
|
* support for nested translation. That means we end up with the
|
|
* following table:
|
|
*
|
|
* Requested Supported Actual
|
|
* S1 N S1
|
|
* S1 S1+S2 S1
|
|
* S1 S2 S2
|
|
* S1 S1 S1
|
|
* N N N
|
|
* N S1+S2 S2
|
|
* N S2 S2
|
|
* N S1 S1
|
|
*
|
|
* Note that you can't actually request stage-2 mappings.
|
|
*/
|
|
if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
|
|
smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
|
|
if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
|
|
smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
|
|
|
|
switch (smmu_domain->stage) {
|
|
case ARM_SMMU_DOMAIN_S1:
|
|
cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
|
|
start = smmu->num_s2_context_banks;
|
|
ias = smmu->va_size;
|
|
oas = smmu->ipa_size;
|
|
if (IS_ENABLED(CONFIG_64BIT))
|
|
fmt = ARM_64_LPAE_S1;
|
|
else
|
|
fmt = ARM_32_LPAE_S1;
|
|
break;
|
|
case ARM_SMMU_DOMAIN_NESTED:
|
|
/*
|
|
* We will likely want to change this if/when KVM gets
|
|
* involved.
|
|
*/
|
|
case ARM_SMMU_DOMAIN_S2:
|
|
cfg->cbar = CBAR_TYPE_S2_TRANS;
|
|
start = 0;
|
|
ias = smmu->ipa_size;
|
|
oas = smmu->pa_size;
|
|
if (IS_ENABLED(CONFIG_64BIT))
|
|
fmt = ARM_64_LPAE_S2;
|
|
else
|
|
fmt = ARM_32_LPAE_S2;
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
goto out_unlock;
|
|
}
|
|
|
|
ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
|
|
smmu->num_context_banks);
|
|
if (IS_ERR_VALUE(ret))
|
|
goto out_unlock;
|
|
|
|
cfg->cbndx = ret;
|
|
if (smmu->version == ARM_SMMU_V1) {
|
|
cfg->irptndx = atomic_inc_return(&smmu->irptndx);
|
|
cfg->irptndx %= smmu->num_context_irqs;
|
|
} else {
|
|
cfg->irptndx = cfg->cbndx;
|
|
}
|
|
|
|
pgtbl_cfg = (struct io_pgtable_cfg) {
|
|
.pgsize_bitmap = arm_smmu_ops.pgsize_bitmap,
|
|
.ias = ias,
|
|
.oas = oas,
|
|
.tlb = &arm_smmu_gather_ops,
|
|
};
|
|
|
|
smmu_domain->smmu = smmu;
|
|
pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
|
|
if (!pgtbl_ops) {
|
|
ret = -ENOMEM;
|
|
goto out_clear_smmu;
|
|
}
|
|
|
|
/* Update our support page sizes to reflect the page table format */
|
|
arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
|
|
|
|
/* Initialise the context bank with our page table cfg */
|
|
arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
|
|
|
|
/*
|
|
* Request context fault interrupt. Do this last to avoid the
|
|
* handler seeing a half-initialised domain state.
|
|
*/
|
|
irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
|
|
ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
|
|
"arm-smmu-context-fault", domain);
|
|
if (IS_ERR_VALUE(ret)) {
|
|
dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
|
|
cfg->irptndx, irq);
|
|
cfg->irptndx = INVALID_IRPTNDX;
|
|
}
|
|
|
|
mutex_unlock(&smmu_domain->init_mutex);
|
|
|
|
/* Publish page table ops for map/unmap */
|
|
smmu_domain->pgtbl_ops = pgtbl_ops;
|
|
return 0;
|
|
|
|
out_clear_smmu:
|
|
smmu_domain->smmu = NULL;
|
|
out_unlock:
|
|
mutex_unlock(&smmu_domain->init_mutex);
|
|
return ret;
|
|
}
|
|
|
|
static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
void __iomem *cb_base;
|
|
int irq;
|
|
|
|
if (!smmu)
|
|
return;
|
|
|
|
/*
|
|
* Disable the context bank and free the page tables before freeing
|
|
* it.
|
|
*/
|
|
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
|
|
|
|
if (cfg->irptndx != INVALID_IRPTNDX) {
|
|
irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
|
|
free_irq(irq, domain);
|
|
}
|
|
|
|
if (smmu_domain->pgtbl_ops)
|
|
free_io_pgtable_ops(smmu_domain->pgtbl_ops);
|
|
|
|
__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
|
|
}
|
|
|
|
static int arm_smmu_domain_init(struct iommu_domain *domain)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain;
|
|
|
|
/*
|
|
* Allocate the domain and initialise some of its data structures.
|
|
* We can't really do anything meaningful until we've added a
|
|
* master.
|
|
*/
|
|
smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
|
|
if (!smmu_domain)
|
|
return -ENOMEM;
|
|
|
|
mutex_init(&smmu_domain->init_mutex);
|
|
spin_lock_init(&smmu_domain->pgtbl_lock);
|
|
domain->priv = smmu_domain;
|
|
return 0;
|
|
}
|
|
|
|
static void arm_smmu_domain_destroy(struct iommu_domain *domain)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
|
|
/*
|
|
* Free the domain resources. We assume that all devices have
|
|
* already been detached.
|
|
*/
|
|
arm_smmu_destroy_domain_context(domain);
|
|
kfree(smmu_domain);
|
|
}
|
|
|
|
static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
|
|
struct arm_smmu_master_cfg *cfg)
|
|
{
|
|
int i;
|
|
struct arm_smmu_smr *smrs;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
|
|
if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
|
|
return 0;
|
|
|
|
if (cfg->smrs)
|
|
return -EEXIST;
|
|
|
|
smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
|
|
if (!smrs) {
|
|
dev_err(smmu->dev, "failed to allocate %d SMRs\n",
|
|
cfg->num_streamids);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Allocate the SMRs on the SMMU */
|
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
|
int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
|
|
smmu->num_mapping_groups);
|
|
if (IS_ERR_VALUE(idx)) {
|
|
dev_err(smmu->dev, "failed to allocate free SMR\n");
|
|
goto err_free_smrs;
|
|
}
|
|
|
|
smrs[i] = (struct arm_smmu_smr) {
|
|
.idx = idx,
|
|
.mask = 0, /* We don't currently share SMRs */
|
|
.id = cfg->streamids[i],
|
|
};
|
|
}
|
|
|
|
/* It worked! Now, poke the actual hardware */
|
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
|
u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
|
|
smrs[i].mask << SMR_MASK_SHIFT;
|
|
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
|
|
}
|
|
|
|
cfg->smrs = smrs;
|
|
return 0;
|
|
|
|
err_free_smrs:
|
|
while (--i >= 0)
|
|
__arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
|
|
kfree(smrs);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
|
|
struct arm_smmu_master_cfg *cfg)
|
|
{
|
|
int i;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
struct arm_smmu_smr *smrs = cfg->smrs;
|
|
|
|
if (!smrs)
|
|
return;
|
|
|
|
/* Invalidate the SMRs before freeing back to the allocator */
|
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
|
u8 idx = smrs[i].idx;
|
|
|
|
writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
|
|
__arm_smmu_free_bitmap(smmu->smr_map, idx);
|
|
}
|
|
|
|
cfg->smrs = NULL;
|
|
kfree(smrs);
|
|
}
|
|
|
|
static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
|
|
struct arm_smmu_master_cfg *cfg)
|
|
{
|
|
int i, ret;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
|
|
/* Devices in an IOMMU group may already be configured */
|
|
ret = arm_smmu_master_configure_smrs(smmu, cfg);
|
|
if (ret)
|
|
return ret == -EEXIST ? 0 : ret;
|
|
|
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
|
u32 idx, s2cr;
|
|
|
|
idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
|
|
s2cr = S2CR_TYPE_TRANS |
|
|
(smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
|
|
writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
|
|
struct arm_smmu_master_cfg *cfg)
|
|
{
|
|
int i;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
|
|
/* An IOMMU group is torn down by the first device to be removed */
|
|
if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
|
|
return;
|
|
|
|
/*
|
|
* We *must* clear the S2CR first, because freeing the SMR means
|
|
* that it can be re-allocated immediately.
|
|
*/
|
|
for (i = 0; i < cfg->num_streamids; ++i) {
|
|
u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
|
|
|
|
writel_relaxed(S2CR_TYPE_BYPASS,
|
|
gr0_base + ARM_SMMU_GR0_S2CR(idx));
|
|
}
|
|
|
|
arm_smmu_master_free_smrs(smmu, cfg);
|
|
}
|
|
|
|
static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
|
{
|
|
int ret;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct arm_smmu_device *smmu;
|
|
struct arm_smmu_master_cfg *cfg;
|
|
|
|
smmu = find_smmu_for_device(dev);
|
|
if (!smmu) {
|
|
dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (dev->archdata.iommu) {
|
|
dev_err(dev, "already attached to IOMMU domain\n");
|
|
return -EEXIST;
|
|
}
|
|
|
|
/* Ensure that the domain is finalised */
|
|
ret = arm_smmu_init_domain_context(domain, smmu);
|
|
if (IS_ERR_VALUE(ret))
|
|
return ret;
|
|
|
|
/*
|
|
* Sanity check the domain. We don't support domains across
|
|
* different SMMUs.
|
|
*/
|
|
if (smmu_domain->smmu != smmu) {
|
|
dev_err(dev,
|
|
"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
|
|
dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Looks ok, so add the device to the domain */
|
|
cfg = find_smmu_master_cfg(dev);
|
|
if (!cfg)
|
|
return -ENODEV;
|
|
|
|
ret = arm_smmu_domain_add_master(smmu_domain, cfg);
|
|
if (!ret)
|
|
dev->archdata.iommu = domain;
|
|
return ret;
|
|
}
|
|
|
|
static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct arm_smmu_master_cfg *cfg;
|
|
|
|
cfg = find_smmu_master_cfg(dev);
|
|
if (!cfg)
|
|
return;
|
|
|
|
dev->archdata.iommu = NULL;
|
|
arm_smmu_domain_remove_master(smmu_domain, cfg);
|
|
}
|
|
|
|
static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
|
|
phys_addr_t paddr, size_t size, int prot)
|
|
{
|
|
int ret;
|
|
unsigned long flags;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
|
|
|
|
if (!ops)
|
|
return -ENODEV;
|
|
|
|
spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
|
|
ret = ops->map(ops, iova, paddr, size, prot);
|
|
spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|
size_t size)
|
|
{
|
|
size_t ret;
|
|
unsigned long flags;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
|
|
|
|
if (!ops)
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
|
|
ret = ops->unmap(ops, iova, size);
|
|
spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct arm_smmu_device *smmu = smmu_domain->smmu;
|
|
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
|
|
struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
|
|
struct device *dev = smmu->dev;
|
|
void __iomem *cb_base;
|
|
u32 tmp;
|
|
u64 phys;
|
|
|
|
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
|
|
|
|
if (smmu->version == 1) {
|
|
u32 reg = iova & ~0xfff;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
|
|
} else {
|
|
u32 reg = iova & ~0xfff;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
|
|
reg = ((u64)iova & ~0xfff) >> 32;
|
|
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
|
|
}
|
|
|
|
if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
|
|
!(tmp & ATSR_ACTIVE), 5, 50)) {
|
|
dev_err(dev,
|
|
"iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
|
|
&iova);
|
|
return ops->iova_to_phys(ops, iova);
|
|
}
|
|
|
|
phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
|
|
phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
|
|
|
|
if (phys & CB_PAR_F) {
|
|
dev_err(dev, "translation fault!\n");
|
|
dev_err(dev, "PAR = 0x%llx\n", phys);
|
|
return 0;
|
|
}
|
|
|
|
return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
|
|
}
|
|
|
|
static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
phys_addr_t ret;
|
|
unsigned long flags;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
|
|
|
|
if (!ops)
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
|
|
if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS)
|
|
ret = arm_smmu_iova_to_phys_hard(domain, iova);
|
|
else
|
|
ret = ops->iova_to_phys(ops, iova);
|
|
spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool arm_smmu_capable(enum iommu_cap cap)
|
|
{
|
|
switch (cap) {
|
|
case IOMMU_CAP_CACHE_COHERENCY:
|
|
/*
|
|
* Return true here as the SMMU can always send out coherent
|
|
* requests.
|
|
*/
|
|
return true;
|
|
case IOMMU_CAP_INTR_REMAP:
|
|
return true; /* MSIs are just memory writes */
|
|
case IOMMU_CAP_NOEXEC:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
|
|
{
|
|
*((u16 *)data) = alias;
|
|
return 0; /* Continue walking */
|
|
}
|
|
|
|
static void __arm_smmu_release_pci_iommudata(void *data)
|
|
{
|
|
kfree(data);
|
|
}
|
|
|
|
static int arm_smmu_add_device(struct device *dev)
|
|
{
|
|
struct arm_smmu_device *smmu;
|
|
struct arm_smmu_master_cfg *cfg;
|
|
struct iommu_group *group;
|
|
void (*releasefn)(void *) = NULL;
|
|
int ret;
|
|
|
|
smmu = find_smmu_for_device(dev);
|
|
if (!smmu)
|
|
return -ENODEV;
|
|
|
|
group = iommu_group_alloc();
|
|
if (IS_ERR(group)) {
|
|
dev_err(dev, "Failed to allocate IOMMU group\n");
|
|
return PTR_ERR(group);
|
|
}
|
|
|
|
if (dev_is_pci(dev)) {
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
|
|
if (!cfg) {
|
|
ret = -ENOMEM;
|
|
goto out_put_group;
|
|
}
|
|
|
|
cfg->num_streamids = 1;
|
|
/*
|
|
* Assume Stream ID == Requester ID for now.
|
|
* We need a way to describe the ID mappings in FDT.
|
|
*/
|
|
pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
|
|
&cfg->streamids[0]);
|
|
releasefn = __arm_smmu_release_pci_iommudata;
|
|
} else {
|
|
struct arm_smmu_master *master;
|
|
|
|
master = find_smmu_master(smmu, dev->of_node);
|
|
if (!master) {
|
|
ret = -ENODEV;
|
|
goto out_put_group;
|
|
}
|
|
|
|
cfg = &master->cfg;
|
|
}
|
|
|
|
iommu_group_set_iommudata(group, cfg, releasefn);
|
|
ret = iommu_group_add_device(group, dev);
|
|
|
|
out_put_group:
|
|
iommu_group_put(group);
|
|
return ret;
|
|
}
|
|
|
|
static void arm_smmu_remove_device(struct device *dev)
|
|
{
|
|
iommu_group_remove_device(dev);
|
|
}
|
|
|
|
static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
|
|
enum iommu_attr attr, void *data)
|
|
{
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
|
|
switch (attr) {
|
|
case DOMAIN_ATTR_NESTING:
|
|
*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
|
|
return 0;
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
|
|
enum iommu_attr attr, void *data)
|
|
{
|
|
int ret = 0;
|
|
struct arm_smmu_domain *smmu_domain = domain->priv;
|
|
|
|
mutex_lock(&smmu_domain->init_mutex);
|
|
|
|
switch (attr) {
|
|
case DOMAIN_ATTR_NESTING:
|
|
if (smmu_domain->smmu) {
|
|
ret = -EPERM;
|
|
goto out_unlock;
|
|
}
|
|
|
|
if (*(int *)data)
|
|
smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
|
|
else
|
|
smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
|
|
|
|
break;
|
|
default:
|
|
ret = -ENODEV;
|
|
}
|
|
|
|
out_unlock:
|
|
mutex_unlock(&smmu_domain->init_mutex);
|
|
return ret;
|
|
}
|
|
|
|
static struct iommu_ops arm_smmu_ops = {
|
|
.capable = arm_smmu_capable,
|
|
.domain_init = arm_smmu_domain_init,
|
|
.domain_destroy = arm_smmu_domain_destroy,
|
|
.attach_dev = arm_smmu_attach_dev,
|
|
.detach_dev = arm_smmu_detach_dev,
|
|
.map = arm_smmu_map,
|
|
.unmap = arm_smmu_unmap,
|
|
.map_sg = default_iommu_map_sg,
|
|
.iova_to_phys = arm_smmu_iova_to_phys,
|
|
.add_device = arm_smmu_add_device,
|
|
.remove_device = arm_smmu_remove_device,
|
|
.domain_get_attr = arm_smmu_domain_get_attr,
|
|
.domain_set_attr = arm_smmu_domain_set_attr,
|
|
.pgsize_bitmap = -1UL, /* Restricted during device attach */
|
|
};
|
|
|
|
static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
|
|
{
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
void __iomem *cb_base;
|
|
int i = 0;
|
|
u32 reg;
|
|
|
|
/* clear global FSR */
|
|
reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
|
|
writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
|
|
|
|
/* Mark all SMRn as invalid and all S2CRn as bypass */
|
|
for (i = 0; i < smmu->num_mapping_groups; ++i) {
|
|
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
|
|
writel_relaxed(S2CR_TYPE_BYPASS,
|
|
gr0_base + ARM_SMMU_GR0_S2CR(i));
|
|
}
|
|
|
|
/* Make sure all context banks are disabled and clear CB_FSR */
|
|
for (i = 0; i < smmu->num_context_banks; ++i) {
|
|
cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
|
|
writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
|
|
writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
|
|
}
|
|
|
|
/* Invalidate the TLB, just in case */
|
|
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
|
|
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
|
|
|
|
reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
|
|
|
|
/* Enable fault reporting */
|
|
reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
|
|
|
|
/* Disable TLB broadcasting. */
|
|
reg |= (sCR0_VMIDPNE | sCR0_PTM);
|
|
|
|
/* Enable client access, but bypass when no mapping is found */
|
|
reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
|
|
|
|
/* Disable forced broadcasting */
|
|
reg &= ~sCR0_FB;
|
|
|
|
/* Don't upgrade barriers */
|
|
reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
|
|
|
|
/* Push the button */
|
|
__arm_smmu_tlb_sync(smmu);
|
|
writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
|
|
}
|
|
|
|
static int arm_smmu_id_size_to_bits(int size)
|
|
{
|
|
switch (size) {
|
|
case 0:
|
|
return 32;
|
|
case 1:
|
|
return 36;
|
|
case 2:
|
|
return 40;
|
|
case 3:
|
|
return 42;
|
|
case 4:
|
|
return 44;
|
|
case 5:
|
|
default:
|
|
return 48;
|
|
}
|
|
}
|
|
|
|
static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
|
|
{
|
|
unsigned long size;
|
|
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
|
u32 id;
|
|
|
|
dev_notice(smmu->dev, "probing hardware configuration...\n");
|
|
dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
|
|
|
|
/* ID0 */
|
|
id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
|
|
|
|
/* Restrict available stages based on module parameter */
|
|
if (force_stage == 1)
|
|
id &= ~(ID0_S2TS | ID0_NTS);
|
|
else if (force_stage == 2)
|
|
id &= ~(ID0_S1TS | ID0_NTS);
|
|
|
|
if (id & ID0_S1TS) {
|
|
smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
|
|
dev_notice(smmu->dev, "\tstage 1 translation\n");
|
|
}
|
|
|
|
if (id & ID0_S2TS) {
|
|
smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
|
|
dev_notice(smmu->dev, "\tstage 2 translation\n");
|
|
}
|
|
|
|
if (id & ID0_NTS) {
|
|
smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
|
|
dev_notice(smmu->dev, "\tnested translation\n");
|
|
}
|
|
|
|
if (!(smmu->features &
|
|
(ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
|
|
dev_err(smmu->dev, "\tno translation support!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) {
|
|
smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
|
|
dev_notice(smmu->dev, "\taddress translation ops\n");
|
|
}
|
|
|
|
if (id & ID0_CTTW) {
|
|
smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
|
|
dev_notice(smmu->dev, "\tcoherent table walk\n");
|
|
}
|
|
|
|
if (id & ID0_SMS) {
|
|
u32 smr, sid, mask;
|
|
|
|
smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
|
|
smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
|
|
ID0_NUMSMRG_MASK;
|
|
if (smmu->num_mapping_groups == 0) {
|
|
dev_err(smmu->dev,
|
|
"stream-matching supported, but no SMRs present!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
|
|
smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
|
|
writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
|
|
smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
|
|
|
|
mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
|
|
sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
|
|
if ((mask & sid) != sid) {
|
|
dev_err(smmu->dev,
|
|
"SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
|
|
mask, sid);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_notice(smmu->dev,
|
|
"\tstream matching with %u register groups, mask 0x%x",
|
|
smmu->num_mapping_groups, mask);
|
|
} else {
|
|
smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
|
|
ID0_NUMSIDB_MASK;
|
|
}
|
|
|
|
/* ID1 */
|
|
id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
|
|
smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
|
|
|
|
/* Check for size mismatch of SMMU address space from mapped region */
|
|
size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
|
|
size *= 2 << smmu->pgshift;
|
|
if (smmu->size != size)
|
|
dev_warn(smmu->dev,
|
|
"SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
|
|
size, smmu->size);
|
|
|
|
smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
|
|
smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
|
|
if (smmu->num_s2_context_banks > smmu->num_context_banks) {
|
|
dev_err(smmu->dev, "impossible number of S2 context banks!\n");
|
|
return -ENODEV;
|
|
}
|
|
dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
|
|
smmu->num_context_banks, smmu->num_s2_context_banks);
|
|
|
|
/* ID2 */
|
|
id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
|
|
size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
|
|
smmu->ipa_size = size;
|
|
|
|
/* The output mask is also applied for bypass */
|
|
size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
|
|
smmu->pa_size = size;
|
|
|
|
if (smmu->version == ARM_SMMU_V1) {
|
|
smmu->va_size = smmu->ipa_size;
|
|
size = SZ_4K | SZ_2M | SZ_1G;
|
|
} else {
|
|
size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
|
|
smmu->va_size = arm_smmu_id_size_to_bits(size);
|
|
#ifndef CONFIG_64BIT
|
|
smmu->va_size = min(32UL, smmu->va_size);
|
|
#endif
|
|
size = 0;
|
|
if (id & ID2_PTFS_4K)
|
|
size |= SZ_4K | SZ_2M | SZ_1G;
|
|
if (id & ID2_PTFS_16K)
|
|
size |= SZ_16K | SZ_32M;
|
|
if (id & ID2_PTFS_64K)
|
|
size |= SZ_64K | SZ_512M;
|
|
}
|
|
|
|
arm_smmu_ops.pgsize_bitmap &= size;
|
|
dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size);
|
|
|
|
if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
|
|
dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
|
|
smmu->va_size, smmu->ipa_size);
|
|
|
|
if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
|
|
dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
|
|
smmu->ipa_size, smmu->pa_size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id arm_smmu_of_match[] = {
|
|
{ .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
|
|
{ .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
|
|
{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
|
|
{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
|
|
{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
|
|
|
|
static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id;
|
|
struct resource *res;
|
|
struct arm_smmu_device *smmu;
|
|
struct device *dev = &pdev->dev;
|
|
struct rb_node *node;
|
|
struct of_phandle_args masterspec;
|
|
int num_irqs, i, err;
|
|
|
|
smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
|
|
if (!smmu) {
|
|
dev_err(dev, "failed to allocate arm_smmu_device\n");
|
|
return -ENOMEM;
|
|
}
|
|
smmu->dev = dev;
|
|
|
|
of_id = of_match_node(arm_smmu_of_match, dev->of_node);
|
|
smmu->version = (enum arm_smmu_arch_version)of_id->data;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
smmu->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(smmu->base))
|
|
return PTR_ERR(smmu->base);
|
|
smmu->size = resource_size(res);
|
|
|
|
if (of_property_read_u32(dev->of_node, "#global-interrupts",
|
|
&smmu->num_global_irqs)) {
|
|
dev_err(dev, "missing #global-interrupts property\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
num_irqs = 0;
|
|
while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
|
|
num_irqs++;
|
|
if (num_irqs > smmu->num_global_irqs)
|
|
smmu->num_context_irqs++;
|
|
}
|
|
|
|
if (!smmu->num_context_irqs) {
|
|
dev_err(dev, "found %d interrupts but expected at least %d\n",
|
|
num_irqs, smmu->num_global_irqs + 1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
|
|
GFP_KERNEL);
|
|
if (!smmu->irqs) {
|
|
dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
for (i = 0; i < num_irqs; ++i) {
|
|
int irq = platform_get_irq(pdev, i);
|
|
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to get irq index %d\n", i);
|
|
return -ENODEV;
|
|
}
|
|
smmu->irqs[i] = irq;
|
|
}
|
|
|
|
err = arm_smmu_device_cfg_probe(smmu);
|
|
if (err)
|
|
return err;
|
|
|
|
i = 0;
|
|
smmu->masters = RB_ROOT;
|
|
while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
|
|
"#stream-id-cells", i,
|
|
&masterspec)) {
|
|
err = register_smmu_master(smmu, dev, &masterspec);
|
|
if (err) {
|
|
dev_err(dev, "failed to add master %s\n",
|
|
masterspec.np->name);
|
|
goto out_put_masters;
|
|
}
|
|
|
|
i++;
|
|
}
|
|
dev_notice(dev, "registered %d master devices\n", i);
|
|
|
|
parse_driver_options(smmu);
|
|
|
|
if (smmu->version > ARM_SMMU_V1 &&
|
|
smmu->num_context_banks != smmu->num_context_irqs) {
|
|
dev_err(dev,
|
|
"found only %d context interrupt(s) but %d required\n",
|
|
smmu->num_context_irqs, smmu->num_context_banks);
|
|
err = -ENODEV;
|
|
goto out_put_masters;
|
|
}
|
|
|
|
for (i = 0; i < smmu->num_global_irqs; ++i) {
|
|
err = request_irq(smmu->irqs[i],
|
|
arm_smmu_global_fault,
|
|
IRQF_SHARED,
|
|
"arm-smmu global fault",
|
|
smmu);
|
|
if (err) {
|
|
dev_err(dev, "failed to request global IRQ %d (%u)\n",
|
|
i, smmu->irqs[i]);
|
|
goto out_free_irqs;
|
|
}
|
|
}
|
|
|
|
INIT_LIST_HEAD(&smmu->list);
|
|
spin_lock(&arm_smmu_devices_lock);
|
|
list_add(&smmu->list, &arm_smmu_devices);
|
|
spin_unlock(&arm_smmu_devices_lock);
|
|
|
|
arm_smmu_device_reset(smmu);
|
|
return 0;
|
|
|
|
out_free_irqs:
|
|
while (i--)
|
|
free_irq(smmu->irqs[i], smmu);
|
|
|
|
out_put_masters:
|
|
for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
|
|
struct arm_smmu_master *master
|
|
= container_of(node, struct arm_smmu_master, node);
|
|
of_node_put(master->of_node);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int arm_smmu_device_remove(struct platform_device *pdev)
|
|
{
|
|
int i;
|
|
struct device *dev = &pdev->dev;
|
|
struct arm_smmu_device *curr, *smmu = NULL;
|
|
struct rb_node *node;
|
|
|
|
spin_lock(&arm_smmu_devices_lock);
|
|
list_for_each_entry(curr, &arm_smmu_devices, list) {
|
|
if (curr->dev == dev) {
|
|
smmu = curr;
|
|
list_del(&smmu->list);
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock(&arm_smmu_devices_lock);
|
|
|
|
if (!smmu)
|
|
return -ENODEV;
|
|
|
|
for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
|
|
struct arm_smmu_master *master
|
|
= container_of(node, struct arm_smmu_master, node);
|
|
of_node_put(master->of_node);
|
|
}
|
|
|
|
if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
|
|
dev_err(dev, "removing device with active domains!\n");
|
|
|
|
for (i = 0; i < smmu->num_global_irqs; ++i)
|
|
free_irq(smmu->irqs[i], smmu);
|
|
|
|
/* Turn the thing off */
|
|
writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver arm_smmu_driver = {
|
|
.driver = {
|
|
.name = "arm-smmu",
|
|
.of_match_table = of_match_ptr(arm_smmu_of_match),
|
|
},
|
|
.probe = arm_smmu_device_dt_probe,
|
|
.remove = arm_smmu_device_remove,
|
|
};
|
|
|
|
static int __init arm_smmu_init(void)
|
|
{
|
|
struct device_node *np;
|
|
int ret;
|
|
|
|
/*
|
|
* Play nice with systems that don't have an ARM SMMU by checking that
|
|
* an ARM SMMU exists in the system before proceeding with the driver
|
|
* and IOMMU bus operation registration.
|
|
*/
|
|
np = of_find_matching_node(NULL, arm_smmu_of_match);
|
|
if (!np)
|
|
return 0;
|
|
|
|
of_node_put(np);
|
|
|
|
ret = platform_driver_register(&arm_smmu_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Oh, for a proper bus abstraction */
|
|
if (!iommu_present(&platform_bus_type))
|
|
bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
|
|
|
|
#ifdef CONFIG_ARM_AMBA
|
|
if (!iommu_present(&amba_bustype))
|
|
bus_set_iommu(&amba_bustype, &arm_smmu_ops);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI
|
|
if (!iommu_present(&pci_bus_type))
|
|
bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit arm_smmu_exit(void)
|
|
{
|
|
return platform_driver_unregister(&arm_smmu_driver);
|
|
}
|
|
|
|
subsys_initcall(arm_smmu_init);
|
|
module_exit(arm_smmu_exit);
|
|
|
|
MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
|
|
MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
|
|
MODULE_LICENSE("GPL v2");
|