mirror of https://gitee.com/openkylin/linux.git
376 lines
9.8 KiB
C
376 lines
9.8 KiB
C
/*
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* Copyright (c) 2011 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <brcm_hw_ids.h>
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#include <chipcommon.h>
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#include <brcmu_utils.h>
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#include "pub.h"
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#include "aiutils.h"
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#include "pmu.h"
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#include "soc.h"
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/*
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* external LPO crystal frequency
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*/
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#define EXT_ILP_HZ 32768
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/*
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* Duration for ILP clock frequency measurment in milliseconds
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*
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* remark: 1000 must be an integer multiple of this duration
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*/
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#define ILP_CALC_DUR 10
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/* Fields in pmucontrol */
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#define PCTL_ILP_DIV_MASK 0xffff0000
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#define PCTL_ILP_DIV_SHIFT 16
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#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
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#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
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#define PCTL_HT_REQ_EN 0x00000100
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#define PCTL_ALP_REQ_EN 0x00000080
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#define PCTL_XTALFREQ_MASK 0x0000007c
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#define PCTL_XTALFREQ_SHIFT 2
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#define PCTL_ILP_DIV_EN 0x00000002
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#define PCTL_LPO_SEL 0x00000001
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/* ILP clock */
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#define ILP_CLOCK 32000
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/* ALP clock on pre-PMU chips */
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#define ALP_CLOCK 20000000
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/* pmustatus */
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#define PST_EXTLPOAVAIL 0x0100
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#define PST_WDRESET 0x0080
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#define PST_INTPEND 0x0040
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#define PST_SBCLKST 0x0030
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#define PST_SBCLKST_ILP 0x0010
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#define PST_SBCLKST_ALP 0x0020
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#define PST_SBCLKST_HT 0x0030
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#define PST_ALPAVAIL 0x0008
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#define PST_HTAVAIL 0x0004
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#define PST_RESINIT 0x0003
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/* PMU resource bit position */
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#define PMURES_BIT(bit) (1 << (bit))
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/* PMU corerev and chip specific PLL controls.
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* PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
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* number to differentiate different PLLs controlled by the same PMU rev.
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*/
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/* pllcontrol registers:
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* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
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* p1div, p2div, _bypass_sdmod
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*/
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#define PMU1_PLL0_PLLCTL0 0
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#define PMU1_PLL0_PLLCTL1 1
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#define PMU1_PLL0_PLLCTL2 2
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#define PMU1_PLL0_PLLCTL3 3
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#define PMU1_PLL0_PLLCTL4 4
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#define PMU1_PLL0_PLLCTL5 5
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/* pmu XtalFreqRatio */
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#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
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#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
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#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
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/* 4313 resources */
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#define RES4313_BB_PU_RSRC 0
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#define RES4313_ILP_REQ_RSRC 1
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#define RES4313_XTAL_PU_RSRC 2
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#define RES4313_ALP_AVAIL_RSRC 3
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#define RES4313_RADIO_PU_RSRC 4
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#define RES4313_BG_PU_RSRC 5
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#define RES4313_VREG1P4_PU_RSRC 6
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#define RES4313_AFE_PWRSW_RSRC 7
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#define RES4313_RX_PWRSW_RSRC 8
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#define RES4313_TX_PWRSW_RSRC 9
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#define RES4313_BB_PWRSW_RSRC 10
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#define RES4313_SYNTH_PWRSW_RSRC 11
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#define RES4313_MISC_PWRSW_RSRC 12
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#define RES4313_BB_PLL_PWRSW_RSRC 13
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#define RES4313_HT_AVAIL_RSRC 14
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#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
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/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
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static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
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{
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u32 min_mask = 0, max_mask = 0;
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uint rsrcs;
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/* # resources */
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rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
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/* determine min/max rsrc masks */
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switch (ai_get_chip_id(sih)) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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/* ??? */
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break;
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case BCM4313_CHIP_ID:
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min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
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PMURES_BIT(RES4313_XTAL_PU_RSRC) |
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PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
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PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
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max_mask = 0xffff;
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break;
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default:
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break;
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}
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*pmin = min_mask;
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*pmax = max_mask;
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}
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void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid)
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{
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u32 tmp = 0;
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struct bcma_device *core;
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/* switch to chipc */
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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switch (ai_get_chip_id(sih)) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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if (spuravoid == 1) {
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL0);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x11500010);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL1);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x000C0C06);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL2);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x0F600a08);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL3);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x00000000);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL4);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x2001E920);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL5);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x88888815);
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} else {
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL0);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x11100010);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL1);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x000c0c06);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL2);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x03000a08);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL3);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x00000000);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL4);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x200005c0);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL5);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x88888815);
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}
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tmp = 1 << 10;
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break;
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default:
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/* bail out */
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return;
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}
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bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
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}
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u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
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{
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uint delay = PMU_MAX_TRANSITION_DLY;
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switch (ai_get_chip_id(sih)) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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case BCM4313_CHIP_ID:
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delay = 3700;
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break;
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default:
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break;
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}
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return (u16) delay;
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}
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/* Read/write a chipcontrol reg */
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u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
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return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
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mask, val);
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}
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/* Read/write a regcontrol reg */
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u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
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return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
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mask, val);
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}
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/* Read/write a pllcontrol reg */
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u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
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return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
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mask, val);
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}
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/* PMU PLL update */
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void si_pmu_pllupd(struct si_pub *sih)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
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PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
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}
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/* query alp/xtal clock frequency */
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u32 si_pmu_alp_clock(struct si_pub *sih)
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{
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u32 clock = ALP_CLOCK;
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/* bail out with default */
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if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
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return clock;
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switch (ai_get_chip_id(sih)) {
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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case BCM4313_CHIP_ID:
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/* always 20Mhz */
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clock = 20000 * 1000;
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break;
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default:
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break;
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}
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return clock;
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}
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/* initialize PMU */
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void si_pmu_init(struct si_pub *sih)
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{
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struct bcma_device *core;
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/* select chipc */
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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if (ai_get_pmurev(sih) == 1)
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bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
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~PCTL_NOILP_ON_WAIT);
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else if (ai_get_pmurev(sih) >= 2)
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bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
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}
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/* initialize PMU resources */
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void si_pmu_res_init(struct si_pub *sih)
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{
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struct bcma_device *core;
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u32 min_mask = 0, max_mask = 0;
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/* select to chipc */
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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/* Determine min/max rsrc masks */
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si_pmu_res_masks(sih, &min_mask, &max_mask);
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/* It is required to program max_mask first and then min_mask */
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/* Program max resource mask */
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if (max_mask)
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bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
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/* Program min resource mask */
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if (min_mask)
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bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
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/* Add some delay; allow resources to come up and settle. */
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mdelay(2);
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}
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u32 si_pmu_measure_alpclk(struct si_pub *sih)
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{
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struct bcma_device *core;
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u32 alp_khz;
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if (ai_get_pmurev(sih) < 10)
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return 0;
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/* Remember original core before switch to chipc */
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
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u32 ilp_ctr, alp_hz;
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/*
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* Enable the reg to measure the freq,
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* in case it was disabled before
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*/
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bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
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1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
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/* Delay for well over 4 ILP clocks */
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udelay(1000);
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/* Read the latched number of ALP ticks per 4 ILP ticks */
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ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
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PMU_XTALFREQ_REG_ILPCTR_MASK;
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/*
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* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
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* bit to save power
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*/
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bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
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/* Calculate ALP frequency */
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alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
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/*
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* Round to nearest 100KHz, and at
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* the same time convert to KHz
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*/
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alp_khz = (alp_hz + 50000) / 100000 * 100;
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} else
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alp_khz = 0;
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return alp_khz;
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}
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