mirror of https://gitee.com/openkylin/linux.git
110 lines
3.0 KiB
C
110 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* leon_pci.c: LEON Host PCI support
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*
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* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
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*
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* Code is partially derived from pcic.c
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*/
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#include <linux/of_device.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/export.h>
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#include <asm/leon.h>
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#include <asm/leon_pci.h>
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/* The LEON architecture does not rely on a BIOS or bootloader to setup
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* PCI for us. The Linux generic routines are used to setup resources,
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* reset values of configuration-space register settings are preserved.
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*
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* PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
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* accessed through a Window which is translated to low 64KB in PCI space, the
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* first 4KB is not used so 60KB is available.
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*/
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void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
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{
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LIST_HEAD(resources);
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struct pci_bus *root_bus;
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struct pci_host_bridge *bridge;
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int ret;
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bridge = pci_alloc_host_bridge(0);
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if (!bridge)
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return;
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pci_add_resource_offset(&resources, &info->io_space,
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info->io_space.start - 0x1000);
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pci_add_resource(&resources, &info->mem_space);
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info->busn.flags = IORESOURCE_BUS;
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pci_add_resource(&resources, &info->busn);
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list_splice_init(&resources, &bridge->windows);
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bridge->dev.parent = &ofdev->dev;
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bridge->sysdata = info;
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bridge->busnr = 0;
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bridge->ops = info->ops;
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bridge->swizzle_irq = pci_common_swizzle;
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bridge->map_irq = info->map_irq;
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret) {
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pci_free_host_bridge(bridge);
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return;
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}
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root_bus = bridge->bus;
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/* Assign devices with resources */
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pci_assign_unassigned_resources();
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pci_bus_add_devices(root_bus);
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}
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void pcibios_fixup_bus(struct pci_bus *pbus)
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{
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struct pci_dev *dev;
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int i, has_io, has_mem;
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u16 cmd;
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list_for_each_entry(dev, &pbus->devices, bus_list) {
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/*
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* We can not rely on that the bootloader has enabled I/O
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* or memory access to PCI devices. Instead we enable it here
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* if the device has BARs of respective type.
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*/
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has_io = has_mem = 0;
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for (i = 0; i < PCI_ROM_RESOURCE; i++) {
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unsigned long f = dev->resource[i].flags;
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if (f & IORESOURCE_IO)
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has_io = 1;
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else if (f & IORESOURCE_MEM)
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has_mem = 1;
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}
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/* ROM BARs are mapped into 32-bit memory space */
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if (dev->resource[PCI_ROM_RESOURCE].end != 0) {
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dev->resource[PCI_ROM_RESOURCE].flags |=
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IORESOURCE_ROM_ENABLE;
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has_mem = 1;
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}
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pci_bus_read_config_word(pbus, dev->devfn, PCI_COMMAND, &cmd);
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if (has_io && !(cmd & PCI_COMMAND_IO)) {
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#ifdef CONFIG_PCI_DEBUG
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printk(KERN_INFO "LEONPCI: Enabling I/O for dev %s\n",
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pci_name(dev));
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#endif
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cmd |= PCI_COMMAND_IO;
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pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
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cmd);
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}
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if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
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#ifdef CONFIG_PCI_DEBUG
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printk(KERN_INFO "LEONPCI: Enabling MEMORY for dev"
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"%s\n", pci_name(dev));
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#endif
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cmd |= PCI_COMMAND_MEMORY;
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pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
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cmd);
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}
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}
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}
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