mirror of https://gitee.com/openkylin/linux.git
747 lines
19 KiB
C
747 lines
19 KiB
C
/*
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* linux/arch/arm/mach-omap2/timer.c
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*
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* OMAP2 GP timer support.
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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*
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* Original driver:
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004-2009 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dmtimer-omap.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/time.h>
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include <plat/counter-32k.h>
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#include <clocksource/timer-ti-dm.h>
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#include "soc.h"
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#include "common.h"
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#include "control.h"
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#include "powerdomain.h"
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#include "omap-secure.h"
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#define REALTIME_COUNTER_BASE 0x48243200
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#define INCREMENTER_NUMERATOR_OFFSET 0x10
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#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
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#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
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/* Clockevent code */
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static struct omap_dm_timer clkev;
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static struct clock_event_device clockevent_gpt;
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/* Clockevent hwmod for am335x and am437x suspend */
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static struct omap_hwmod *clockevent_gpt_hwmod;
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/* Clockesource hwmod for am437x suspend */
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static struct omap_hwmod *clocksource_gpt_hwmod;
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#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
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static unsigned long arch_timer_freq;
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void set_cntfreq(void)
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{
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omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
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}
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#endif
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_gpt;
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__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction omap2_gp_timer_irq = {
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.name = "gp_timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = omap2_gp_timer_interrupt,
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};
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static int omap2_gp_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
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0xffffffff - cycles, OMAP_TIMER_POSTED);
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return 0;
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}
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static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
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{
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__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
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return 0;
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}
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static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
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{
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u32 period;
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__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
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period = clkev.rate / HZ;
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period -= 1;
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/* Looks like we need to first set the load value separately */
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__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
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OMAP_TIMER_POSTED);
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__omap_dm_timer_load_start(&clkev,
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OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
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0xffffffff - period, OMAP_TIMER_POSTED);
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return 0;
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}
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static void omap_clkevt_idle(struct clock_event_device *unused)
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{
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if (!clockevent_gpt_hwmod)
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return;
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omap_hwmod_idle(clockevent_gpt_hwmod);
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}
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static void omap_clkevt_unidle(struct clock_event_device *unused)
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{
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if (!clockevent_gpt_hwmod)
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return;
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omap_hwmod_enable(clockevent_gpt_hwmod);
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__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
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}
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static struct clock_event_device clockevent_gpt = {
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.rating = 300,
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.set_next_event = omap2_gp_timer_set_next_event,
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.set_state_shutdown = omap2_gp_timer_shutdown,
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.set_state_periodic = omap2_gp_timer_set_periodic,
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.set_state_oneshot = omap2_gp_timer_shutdown,
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.tick_resume = omap2_gp_timer_shutdown,
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};
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static const struct of_device_id omap_timer_match[] __initconst = {
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{ .compatible = "ti,omap2420-timer", },
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{ .compatible = "ti,omap3430-timer", },
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{ .compatible = "ti,omap4430-timer", },
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{ .compatible = "ti,omap5430-timer", },
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{ .compatible = "ti,dm814-timer", },
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{ .compatible = "ti,dm816-timer", },
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{ .compatible = "ti,am335x-timer", },
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{ .compatible = "ti,am335x-timer-1ms", },
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{ }
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};
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static int omap_timer_add_disabled_property(struct device_node *np)
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{
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struct property *prop;
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prop = kzalloc(sizeof(*prop), GFP_KERNEL);
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if (!prop)
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return -ENOMEM;
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prop->name = "status";
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prop->value = "disabled";
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prop->length = strlen(prop->value);
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return of_add_property(np, prop);
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}
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static int omap_timer_update_dt(struct device_node *np)
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{
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int error = 0;
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if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
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error = omap_timer_add_disabled_property(np);
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if (error)
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return error;
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}
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/* No parent interconnect target module configured? */
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if (of_get_property(np, "ti,hwmods", NULL))
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return error;
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/* Tag parent interconnect target module disabled */
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error = omap_timer_add_disabled_property(np->parent);
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if (error)
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return error;
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return 0;
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}
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/**
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* omap_get_timer_dt - get a timer using device-tree
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* @match - device-tree match structure for matching a device type
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* @property - optional timer property to match
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*
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* Helper function to get a timer during early boot using device-tree for use
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* as kernel system timer. Optionally, the property argument can be used to
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* select a timer with a specific property. Once a timer is found then mark
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* the timer node in device-tree as disabled, to prevent the kernel from
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* registering this timer as a platform device and so no one else can use it.
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*/
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static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
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const char *property)
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{
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struct device_node *np;
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int error;
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for_each_matching_node(np, match) {
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if (!of_device_is_available(np))
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continue;
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if (property && !of_get_property(np, property, NULL))
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continue;
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if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
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of_get_property(np, "ti,timer-dsp", NULL) ||
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of_get_property(np, "ti,timer-pwm", NULL) ||
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of_get_property(np, "ti,timer-secure", NULL)))
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continue;
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error = omap_timer_update_dt(np);
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WARN(error, "%s: Could not update dt: %i\n", __func__, error);
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return np;
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}
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return NULL;
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}
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/**
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* omap_dmtimer_init - initialisation function when device tree is used
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*
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* For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
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* cannot be used by the kernel as they are reserved. Therefore, to prevent the
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* kernel registering these devices remove them dynamically from the device
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* tree on boot.
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*/
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static void __init omap_dmtimer_init(void)
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{
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struct device_node *np;
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if (!cpu_is_omap34xx() && !soc_is_dra7xx())
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return;
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/* If we are a secure device, remove any secure timer nodes */
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if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
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np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
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of_node_put(np);
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}
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}
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/**
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* omap_dm_timer_get_errata - get errata flags for a timer
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*
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* Get the timer errata flags that are specific to the OMAP device being used.
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*/
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static u32 __init omap_dm_timer_get_errata(void)
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{
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if (cpu_is_omap24xx())
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return 0;
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return OMAP_TIMER_ERRATA_I103_I767;
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}
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static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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const char *fck_source,
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const char *property,
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const char **timer_name,
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int posted)
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{
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const char *oh_name = NULL;
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struct device_node *np;
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struct omap_hwmod *oh;
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struct clk *src;
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int r = 0;
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np = omap_get_timer_dt(omap_timer_match, property);
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if (!np)
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return -ENODEV;
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of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
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if (!oh_name) {
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of_property_read_string_index(np->parent, "ti,hwmods", 0,
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&oh_name);
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if (!oh_name)
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return -ENODEV;
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}
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timer->irq = irq_of_parse_and_map(np, 0);
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if (!timer->irq)
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return -ENXIO;
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timer->io_base = of_iomap(np, 0);
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timer->fclk = of_clk_get_by_name(np, "fck");
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of_node_put(np);
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oh = omap_hwmod_lookup(oh_name);
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if (!oh)
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return -ENODEV;
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*timer_name = oh->name;
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if (!timer->io_base)
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return -ENXIO;
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omap_hwmod_setup_one(oh_name);
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/* After the dmtimer is using hwmod these clocks won't be needed */
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if (IS_ERR_OR_NULL(timer->fclk))
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timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
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if (IS_ERR(timer->fclk))
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return PTR_ERR(timer->fclk);
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src = clk_get(NULL, fck_source);
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if (IS_ERR(src))
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return PTR_ERR(src);
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WARN(clk_set_parent(timer->fclk, src) < 0,
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"Cannot set timer parent clock, no PLL clock driver?");
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clk_put(src);
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omap_hwmod_enable(oh);
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__omap_dm_timer_init_regs(timer);
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if (posted)
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__omap_dm_timer_enable_posted(timer);
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/* Check that the intended posted configuration matches the actual */
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if (posted != timer->posted)
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return -EINVAL;
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timer->rate = clk_get_rate(timer->fclk);
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timer->reserved = 1;
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return r;
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}
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#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
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void tick_broadcast(const struct cpumask *mask)
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{
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}
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#endif
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static void __init omap2_gp_clockevent_init(int gptimer_id,
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const char *fck_source,
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const char *property)
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{
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int res;
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clkev.id = gptimer_id;
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clkev.errata = omap_dm_timer_get_errata();
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/*
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* For clock-event timers we never read the timer counter and
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* so we are not impacted by errata i103 and i767. Therefore,
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* we can safely ignore this errata for clock-event timers.
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*/
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__omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
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res = omap_dm_timer_init_one(&clkev, fck_source, property,
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&clockevent_gpt.name, OMAP_TIMER_POSTED);
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BUG_ON(res);
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omap2_gp_timer_irq.dev_id = &clkev;
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setup_irq(clkev.irq, &omap2_gp_timer_irq);
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__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
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clockevent_gpt.cpumask = cpu_possible_mask;
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clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
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clockevents_config_and_register(&clockevent_gpt, clkev.rate,
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3, /* Timer internal resynch latency */
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0xffffffff);
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if (soc_is_am33xx() || soc_is_am43xx()) {
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clockevent_gpt.suspend = omap_clkevt_idle;
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clockevent_gpt.resume = omap_clkevt_unidle;
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clockevent_gpt_hwmod =
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omap_hwmod_lookup(clockevent_gpt.name);
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}
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pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
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clkev.rate);
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}
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/* Clocksource code */
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static struct omap_dm_timer clksrc;
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static bool use_gptimer_clksrc __initdata;
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/*
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* clocksource
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*/
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static u64 clocksource_read_cycles(struct clocksource *cs)
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{
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return (u64)__omap_dm_timer_read_counter(&clksrc,
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OMAP_TIMER_NONPOSTED);
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}
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static struct clocksource clocksource_gpt = {
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.rating = 300,
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.read = clocksource_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static u64 notrace dmtimer_read_sched_clock(void)
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{
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if (clksrc.reserved)
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return __omap_dm_timer_read_counter(&clksrc,
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OMAP_TIMER_NONPOSTED);
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return 0;
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}
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static const struct of_device_id omap_counter_match[] __initconst = {
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{ .compatible = "ti,omap-counter32k", },
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{ }
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};
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|
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/* Setup free-running counter for clocksource */
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static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
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{
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int ret;
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struct device_node *np = NULL;
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struct omap_hwmod *oh;
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const char *oh_name = "counter_32k";
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/*
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* See if the 32kHz counter is supported.
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*/
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np = omap_get_timer_dt(omap_counter_match, NULL);
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if (!np)
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return -ENODEV;
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of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
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if (!oh_name) {
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of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
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if (!oh_name)
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return -ENODEV;
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}
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/*
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* First check hwmod data is available for sync32k counter
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*/
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oh = omap_hwmod_lookup(oh_name);
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if (!oh || oh->slaves_cnt == 0)
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return -ENODEV;
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omap_hwmod_setup_one(oh_name);
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ret = omap_hwmod_enable(oh);
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if (ret) {
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pr_warn("%s: failed to enable counter_32k module (%d)\n",
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__func__, ret);
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return ret;
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}
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return ret;
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}
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|
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static unsigned int omap2_gptimer_clksrc_load;
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|
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static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
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{
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omap2_gptimer_clksrc_load =
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__omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
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|
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omap_hwmod_idle(clocksource_gpt_hwmod);
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}
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|
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static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
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{
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omap_hwmod_enable(clocksource_gpt_hwmod);
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__omap_dm_timer_load_start(&clksrc,
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OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
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omap2_gptimer_clksrc_load,
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OMAP_TIMER_NONPOSTED);
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}
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|
|
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
|
|
const char *fck_source,
|
|
const char *property)
|
|
{
|
|
int res;
|
|
|
|
clksrc.id = gptimer_id;
|
|
clksrc.errata = omap_dm_timer_get_errata();
|
|
|
|
res = omap_dm_timer_init_one(&clksrc, fck_source, property,
|
|
&clocksource_gpt.name,
|
|
OMAP_TIMER_NONPOSTED);
|
|
|
|
if (soc_is_am43xx()) {
|
|
clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
|
|
clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
|
|
|
|
clocksource_gpt_hwmod =
|
|
omap_hwmod_lookup(clocksource_gpt.name);
|
|
}
|
|
|
|
BUG_ON(res);
|
|
|
|
__omap_dm_timer_load_start(&clksrc,
|
|
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
|
|
OMAP_TIMER_NONPOSTED);
|
|
sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
|
|
|
|
if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
|
|
pr_err("Could not register clocksource %s\n",
|
|
clocksource_gpt.name);
|
|
else
|
|
pr_info("OMAP clocksource: %s at %lu Hz\n",
|
|
clocksource_gpt.name, clksrc.rate);
|
|
}
|
|
|
|
static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
|
|
const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
|
|
const char *clksrc_prop, bool gptimer)
|
|
{
|
|
omap_clk_init();
|
|
omap_dmtimer_init();
|
|
omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
|
|
|
|
/* Enable the use of clocksource="gp_timer" kernel parameter */
|
|
if (use_gptimer_clksrc || gptimer)
|
|
omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
|
|
clksrc_prop);
|
|
else
|
|
omap2_sync32k_clocksource_init();
|
|
}
|
|
|
|
void __init omap_init_time(void)
|
|
{
|
|
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
|
|
2, "timer_sys_ck", NULL, false);
|
|
|
|
timer_probe();
|
|
}
|
|
|
|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
|
|
void __init omap3_secure_sync32k_timer_init(void)
|
|
{
|
|
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
|
|
2, "timer_sys_ck", NULL, false);
|
|
|
|
timer_probe();
|
|
}
|
|
#endif /* CONFIG_ARCH_OMAP3 */
|
|
|
|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
|
|
defined(CONFIG_SOC_AM43XX)
|
|
void __init omap3_gptimer_timer_init(void)
|
|
{
|
|
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
|
|
1, "timer_sys_ck", "ti,timer-alwon", true);
|
|
if (of_have_populated_dt())
|
|
timer_probe();
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
|
defined(CONFIG_SOC_DRA7XX)
|
|
static void __init omap4_sync32k_timer_init(void)
|
|
{
|
|
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
|
|
2, "sys_clkin_ck", NULL, false);
|
|
}
|
|
|
|
void __init omap4_local_timer_init(void)
|
|
{
|
|
omap4_sync32k_timer_init();
|
|
timer_probe();
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
|
|
|
|
/*
|
|
* The realtime counter also called master counter, is a free-running
|
|
* counter, which is related to real time. It produces the count used
|
|
* by the CPU local timer peripherals in the MPU cluster. The timer counts
|
|
* at a rate of 6.144 MHz. Because the device operates on different clocks
|
|
* in different power modes, the master counter shifts operation between
|
|
* clocks, adjusting the increment per clock in hardware accordingly to
|
|
* maintain a constant count rate.
|
|
*/
|
|
static void __init realtime_counter_init(void)
|
|
{
|
|
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
|
|
void __iomem *base;
|
|
static struct clk *sys_clk;
|
|
unsigned long rate;
|
|
unsigned int reg;
|
|
unsigned long long num, den;
|
|
|
|
base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
|
|
if (!base) {
|
|
pr_err("%s: ioremap failed\n", __func__);
|
|
return;
|
|
}
|
|
sys_clk = clk_get(NULL, "sys_clkin");
|
|
if (IS_ERR(sys_clk)) {
|
|
pr_err("%s: failed to get system clock handle\n", __func__);
|
|
iounmap(base);
|
|
return;
|
|
}
|
|
|
|
rate = clk_get_rate(sys_clk);
|
|
|
|
if (soc_is_dra7xx()) {
|
|
/*
|
|
* Errata i856 says the 32.768KHz crystal does not start at
|
|
* power on, so the CPU falls back to an emulated 32KHz clock
|
|
* based on sysclk / 610 instead. This causes the master counter
|
|
* frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
|
|
* (OR sysclk * 75 / 244)
|
|
*
|
|
* This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
|
|
* Of course any board built without a populated 32.768KHz
|
|
* crystal would also need this fix even if the CPU is fixed
|
|
* later.
|
|
*
|
|
* Either case can be detected by using the two speedselect bits
|
|
* If they are not 0, then the 32.768KHz clock driving the
|
|
* coarse counter that corrects the fine counter every time it
|
|
* ticks is actually rate/610 rather than 32.768KHz and we
|
|
* should compensate to avoid the 570ppm (at 20MHz, much worse
|
|
* at other rates) too fast system time.
|
|
*/
|
|
reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
|
|
if (reg & DRA7_SPEEDSELECT_MASK) {
|
|
num = 75;
|
|
den = 244;
|
|
goto sysclk1_based;
|
|
}
|
|
}
|
|
|
|
/* Numerator/denumerator values refer TRM Realtime Counter section */
|
|
switch (rate) {
|
|
case 12000000:
|
|
num = 64;
|
|
den = 125;
|
|
break;
|
|
case 13000000:
|
|
num = 768;
|
|
den = 1625;
|
|
break;
|
|
case 19200000:
|
|
num = 8;
|
|
den = 25;
|
|
break;
|
|
case 20000000:
|
|
num = 192;
|
|
den = 625;
|
|
break;
|
|
case 26000000:
|
|
num = 384;
|
|
den = 1625;
|
|
break;
|
|
case 27000000:
|
|
num = 256;
|
|
den = 1125;
|
|
break;
|
|
case 38400000:
|
|
default:
|
|
/* Program it for 38.4 MHz */
|
|
num = 4;
|
|
den = 25;
|
|
break;
|
|
}
|
|
|
|
sysclk1_based:
|
|
/* Program numerator and denumerator registers */
|
|
reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
|
|
NUMERATOR_DENUMERATOR_MASK;
|
|
reg |= num;
|
|
writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
|
|
|
|
reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
|
|
NUMERATOR_DENUMERATOR_MASK;
|
|
reg |= den;
|
|
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
|
|
|
|
arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
|
|
set_cntfreq();
|
|
|
|
iounmap(base);
|
|
#endif
|
|
}
|
|
|
|
void __init omap5_realtime_timer_init(void)
|
|
{
|
|
omap4_sync32k_timer_init();
|
|
realtime_counter_init();
|
|
|
|
timer_probe();
|
|
}
|
|
#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
|
|
|
|
/**
|
|
* omap2_override_clocksource - clocksource override with user configuration
|
|
*
|
|
* Allows user to override default clocksource, using kernel parameter
|
|
* clocksource="gp_timer" (For all OMAP2PLUS architectures)
|
|
*
|
|
* Note that, here we are using same standard kernel parameter "clocksource=",
|
|
* and not introducing any OMAP specific interface.
|
|
*/
|
|
static int __init omap2_override_clocksource(char *str)
|
|
{
|
|
if (!str)
|
|
return 0;
|
|
/*
|
|
* For OMAP architecture, we only have two options
|
|
* - sync_32k (default)
|
|
* - gp_timer (sys_clk based)
|
|
*/
|
|
if (!strcmp(str, "gp_timer"))
|
|
use_gptimer_clksrc = true;
|
|
|
|
return 0;
|
|
}
|
|
early_param("clocksource", omap2_override_clocksource);
|