mirror of https://gitee.com/openkylin/linux.git
579 lines
14 KiB
C
579 lines
14 KiB
C
/*
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* arch/arm/mach-orion5x/ts78xx-setup.c
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*
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* Maintainer: Alexander Clouter <alex@digriz.org.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sysfs.h>
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#include <linux/platform_device.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <linux/mtd/platnand.h>
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#include <linux/timeriomem-rng.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "mpp.h"
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#include "orion5x.h"
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#include "ts78xx-fpga.h"
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/*****************************************************************************
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* TS-78xx Info
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****************************************************************************/
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/*
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* FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
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*/
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#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
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#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
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#define TS78XX_FPGA_REGS_SIZE SZ_1M
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static struct ts78xx_fpga_data ts78xx_fpga = {
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.id = 0,
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.state = 1,
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/* .supports = ... - populated by ts78xx_fpga_supports() */
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};
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc ts78xx_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
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.length = TS78XX_FPGA_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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static void __init ts78xx_map_io(void)
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{
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orion5x_map_io();
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iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
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}
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data ts78xx_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(0),
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};
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct mv_sata_platform_data ts78xx_sata_data = {
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.n_ports = 2,
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};
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/*****************************************************************************
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* RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
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****************************************************************************/
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#define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
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#define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
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static struct resource ts78xx_ts_rtc_resources[] = {
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DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
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DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
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};
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static struct platform_device ts78xx_ts_rtc_device = {
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.name = "rtc-m48t86",
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.id = -1,
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.resource = ts78xx_ts_rtc_resources,
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.num_resources = ARRAY_SIZE(ts78xx_ts_rtc_resources),
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};
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static int ts78xx_ts_rtc_load(void)
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{
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int rc;
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if (ts78xx_fpga.supports.ts_rtc.init == 0) {
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rc = platform_device_register(&ts78xx_ts_rtc_device);
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if (!rc)
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ts78xx_fpga.supports.ts_rtc.init = 1;
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} else {
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rc = platform_device_add(&ts78xx_ts_rtc_device);
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}
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if (rc)
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pr_info("RTC could not be registered: %d\n", rc);
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return rc;
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}
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static void ts78xx_ts_rtc_unload(void)
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{
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platform_device_del(&ts78xx_ts_rtc_device);
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}
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/*****************************************************************************
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* NAND Flash
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****************************************************************************/
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#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
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#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
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/*
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* hardware specific access to control-lines
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*
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* ctrl:
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* NAND_NCE: bit 0 -> bit 2
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* NAND_CLE: bit 1 -> bit 1
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* NAND_ALE: bit 2 -> bit 0
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*/
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static void ts78xx_ts_nand_cmd_ctrl(struct nand_chip *this, int cmd,
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unsigned int ctrl)
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{
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if (ctrl & NAND_CTRL_CHANGE) {
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unsigned char bits;
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bits = (ctrl & NAND_NCE) << 2;
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bits |= ctrl & NAND_CLE;
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bits |= (ctrl & NAND_ALE) >> 2;
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writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->legacy.IO_ADDR_W);
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}
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static int ts78xx_ts_nand_dev_ready(struct nand_chip *chip)
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{
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return readb(TS_NAND_CTRL) & 0x20;
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}
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static void ts78xx_ts_nand_write_buf(struct nand_chip *chip,
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const uint8_t *buf, int len)
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{
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void __iomem *io_base = chip->legacy.IO_ADDR_W;
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unsigned long off = ((unsigned long)buf & 3);
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int sz;
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if (off) {
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sz = min_t(int, 4 - off, len);
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writesb(io_base, buf, sz);
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buf += sz;
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len -= sz;
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}
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sz = len >> 2;
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if (sz) {
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u32 *buf32 = (u32 *)buf;
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writesl(io_base, buf32, sz);
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buf += sz << 2;
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len -= sz << 2;
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}
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if (len)
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writesb(io_base, buf, len);
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}
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static void ts78xx_ts_nand_read_buf(struct nand_chip *chip,
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uint8_t *buf, int len)
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{
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void __iomem *io_base = chip->legacy.IO_ADDR_R;
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unsigned long off = ((unsigned long)buf & 3);
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int sz;
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if (off) {
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sz = min_t(int, 4 - off, len);
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readsb(io_base, buf, sz);
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buf += sz;
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len -= sz;
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}
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sz = len >> 2;
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if (sz) {
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u32 *buf32 = (u32 *)buf;
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readsl(io_base, buf32, sz);
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buf += sz << 2;
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len -= sz << 2;
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}
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if (len)
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readsb(io_base, buf, len);
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}
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static struct mtd_partition ts78xx_ts_nand_parts[] = {
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{
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.name = "mbr",
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.offset = 0,
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.size = SZ_128K,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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}, {
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.name = "initrd",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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}, {
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.name = "rootfs",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct platform_nand_data ts78xx_ts_nand_data = {
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.chip = {
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.nr_chips = 1,
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.partitions = ts78xx_ts_nand_parts,
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.nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
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.chip_delay = 15,
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.bbt_options = NAND_BBT_USE_FLASH,
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},
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.ctrl = {
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/*
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* The HW ECC offloading functions, used to give about a 9%
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* performance increase for 'dd if=/dev/mtdblockX' and 5% for
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* nanddump. This all however was changed by git commit
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* e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
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* no performance advantage to be had so we no longer bother
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*/
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.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
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.dev_ready = ts78xx_ts_nand_dev_ready,
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.write_buf = ts78xx_ts_nand_write_buf,
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.read_buf = ts78xx_ts_nand_read_buf,
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},
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};
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static struct resource ts78xx_ts_nand_resources
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= DEFINE_RES_MEM(TS_NAND_DATA, 4);
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static struct platform_device ts78xx_ts_nand_device = {
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.name = "gen_nand",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_nand_data,
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},
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.resource = &ts78xx_ts_nand_resources,
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.num_resources = 1,
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};
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static int ts78xx_ts_nand_load(void)
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{
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int rc;
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if (ts78xx_fpga.supports.ts_nand.init == 0) {
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rc = platform_device_register(&ts78xx_ts_nand_device);
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if (!rc)
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ts78xx_fpga.supports.ts_nand.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_nand_device);
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if (rc)
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pr_info("NAND could not be registered: %d\n", rc);
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return rc;
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};
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static void ts78xx_ts_nand_unload(void)
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{
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platform_device_del(&ts78xx_ts_nand_device);
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}
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/*****************************************************************************
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* HW RNG
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****************************************************************************/
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#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
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static struct resource ts78xx_ts_rng_resource
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= DEFINE_RES_MEM(TS_RNG_DATA, 4);
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static struct timeriomem_rng_data ts78xx_ts_rng_data = {
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.period = 1000000, /* one second */
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};
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static struct platform_device ts78xx_ts_rng_device = {
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.name = "timeriomem_rng",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_rng_data,
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},
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.resource = &ts78xx_ts_rng_resource,
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.num_resources = 1,
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};
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static int ts78xx_ts_rng_load(void)
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{
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int rc;
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if (ts78xx_fpga.supports.ts_rng.init == 0) {
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rc = platform_device_register(&ts78xx_ts_rng_device);
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if (!rc)
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ts78xx_fpga.supports.ts_rng.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_rng_device);
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if (rc)
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pr_info("RNG could not be registered: %d\n", rc);
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return rc;
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};
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static void ts78xx_ts_rng_unload(void)
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{
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platform_device_del(&ts78xx_ts_rng_device);
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}
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/*****************************************************************************
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* FPGA 'hotplug' support code
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****************************************************************************/
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static void ts78xx_fpga_devices_zero_init(void)
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{
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ts78xx_fpga.supports.ts_rtc.init = 0;
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ts78xx_fpga.supports.ts_nand.init = 0;
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ts78xx_fpga.supports.ts_rng.init = 0;
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}
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static void ts78xx_fpga_supports(void)
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{
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/* TODO: put this 'table' into ts78xx-fpga.h */
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switch (ts78xx_fpga.id) {
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case TS7800_REV_1:
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case TS7800_REV_2:
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case TS7800_REV_3:
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case TS7800_REV_4:
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case TS7800_REV_5:
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case TS7800_REV_6:
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case TS7800_REV_7:
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case TS7800_REV_8:
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case TS7800_REV_9:
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ts78xx_fpga.supports.ts_rtc.present = 1;
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ts78xx_fpga.supports.ts_nand.present = 1;
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ts78xx_fpga.supports.ts_rng.present = 1;
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break;
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default:
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/* enable devices if magic matches */
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switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
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case TS7800_FPGA_MAGIC:
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pr_warn("unrecognised FPGA revision 0x%.2x\n",
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ts78xx_fpga.id & 0xff);
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ts78xx_fpga.supports.ts_rtc.present = 1;
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ts78xx_fpga.supports.ts_nand.present = 1;
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ts78xx_fpga.supports.ts_rng.present = 1;
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break;
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default:
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ts78xx_fpga.supports.ts_rtc.present = 0;
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ts78xx_fpga.supports.ts_nand.present = 0;
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ts78xx_fpga.supports.ts_rng.present = 0;
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}
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}
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}
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static int ts78xx_fpga_load_devices(void)
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{
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int tmp, ret = 0;
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if (ts78xx_fpga.supports.ts_rtc.present == 1) {
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tmp = ts78xx_ts_rtc_load();
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if (tmp)
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ts78xx_fpga.supports.ts_rtc.present = 0;
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ret |= tmp;
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}
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if (ts78xx_fpga.supports.ts_nand.present == 1) {
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tmp = ts78xx_ts_nand_load();
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if (tmp)
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ts78xx_fpga.supports.ts_nand.present = 0;
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ret |= tmp;
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}
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if (ts78xx_fpga.supports.ts_rng.present == 1) {
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tmp = ts78xx_ts_rng_load();
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if (tmp)
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ts78xx_fpga.supports.ts_rng.present = 0;
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ret |= tmp;
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}
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return ret;
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}
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static int ts78xx_fpga_unload_devices(void)
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{
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int ret = 0;
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if (ts78xx_fpga.supports.ts_rtc.present == 1)
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ts78xx_ts_rtc_unload();
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if (ts78xx_fpga.supports.ts_nand.present == 1)
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ts78xx_ts_nand_unload();
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if (ts78xx_fpga.supports.ts_rng.present == 1)
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ts78xx_ts_rng_unload();
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return ret;
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}
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static int ts78xx_fpga_load(void)
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{
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ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
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pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
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(ts78xx_fpga.id >> 8) & 0xffffff,
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ts78xx_fpga.id & 0xff);
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ts78xx_fpga_supports();
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if (ts78xx_fpga_load_devices()) {
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ts78xx_fpga.state = -1;
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return -EBUSY;
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}
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return 0;
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};
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static int ts78xx_fpga_unload(void)
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{
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unsigned int fpga_id;
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fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
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/*
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* There does not seem to be a feasible way to block access to the GPIO
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* pins from userspace (/dev/mem). This if clause should hopefully warn
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* those foolish enough not to follow 'policy' :)
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*
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* UrJTAG SVN since r1381 can be used to reprogram the FPGA
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*/
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if (ts78xx_fpga.id != fpga_id) {
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pr_err("FPGA magic/rev mismatch\n"
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"TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
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(ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
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(fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
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ts78xx_fpga.state = -1;
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return -EBUSY;
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}
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if (ts78xx_fpga_unload_devices()) {
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ts78xx_fpga.state = -1;
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return -EBUSY;
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}
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return 0;
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};
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static ssize_t ts78xx_fpga_show(struct kobject *kobj,
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struct kobj_attribute *attr, char *buf)
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{
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if (ts78xx_fpga.state < 0)
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return sprintf(buf, "borked\n");
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return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
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}
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static ssize_t ts78xx_fpga_store(struct kobject *kobj,
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struct kobj_attribute *attr, const char *buf, size_t n)
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{
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int value, ret;
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if (ts78xx_fpga.state < 0) {
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pr_err("FPGA borked, you must powercycle ASAP\n");
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return -EBUSY;
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}
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if (strncmp(buf, "online", sizeof("online") - 1) == 0)
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value = 1;
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else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
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value = 0;
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else
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return -EINVAL;
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if (ts78xx_fpga.state == value)
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return n;
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ret = (ts78xx_fpga.state == 0)
|
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? ts78xx_fpga_load()
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: ts78xx_fpga_unload();
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if (!(ret < 0))
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ts78xx_fpga.state = value;
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return n;
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}
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|
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static struct kobj_attribute ts78xx_fpga_attr =
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__ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
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|
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static unsigned int ts78xx_mpp_modes[] __initdata = {
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MPP0_UNUSED,
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MPP1_GPIO, /* JTAG Clock */
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MPP2_GPIO, /* JTAG Data In */
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MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
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MPP4_GPIO, /* JTAG Data Out */
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MPP5_GPIO, /* JTAG TMS */
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MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
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MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
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MPP8_UNUSED,
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MPP9_UNUSED,
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MPP10_UNUSED,
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MPP11_UNUSED,
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MPP12_UNUSED,
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MPP13_UNUSED,
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MPP14_UNUSED,
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MPP15_UNUSED,
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MPP16_UART,
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MPP17_UART,
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MPP18_UART,
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MPP19_UART,
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/*
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* MPP[20] PCI Clock Out 1
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* MPP[21] PCI Clock Out 0
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* MPP[22] Unused
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* MPP[23] Unused
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* MPP[24] Unused
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* MPP[25] Unused
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*/
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0,
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};
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static void __init ts78xx_init(void)
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{
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int ret;
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(ts78xx_mpp_modes);
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|
|
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_ehci1_init();
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orion5x_eth_init(&ts78xx_eth_data);
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orion5x_sata_init(&ts78xx_sata_data);
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orion5x_uart0_init();
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orion5x_uart1_init();
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orion5x_xor_init();
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|
|
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/* FPGA init */
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|
ts78xx_fpga_devices_zero_init();
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|
ret = ts78xx_fpga_load();
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|
ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
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|
if (ret)
|
|
pr_err("sysfs_create_file failed: %d\n", ret);
|
|
}
|
|
|
|
MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
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|
/* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
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|
.atag_offset = 0x100,
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|
.nr_irqs = ORION5X_NR_IRQS,
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.init_machine = ts78xx_init,
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|
.map_io = ts78xx_map_io,
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|
.init_early = orion5x_init_early,
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|
.init_irq = orion5x_init_irq,
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|
.init_time = orion5x_timer_init,
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|
.restart = orion5x_restart,
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|
MACHINE_END
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