mirror of https://gitee.com/openkylin/linux.git
194 lines
5.2 KiB
C
194 lines
5.2 KiB
C
/*
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* linux/arch/arm/mach-tegra/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* Copyright (C) 2009 Palm
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk/tegra.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#include <asm/cacheflush.h>
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#include <asm/mach-types.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "common.h"
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#include "iomap.h"
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#include "reset.h"
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static cpumask_t tegra_cpu_init_mask;
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static void tegra_secondary_init(unsigned int cpu)
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{
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cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
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}
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static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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cpu = cpu_logical_map(cpu);
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/*
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* Force the CPU into reset. The CPU must remain in reset when
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* the flow controller state is cleared (which will cause the
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* flow controller to stop driving reset if the CPU has been
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* power-gated via the flow controller). This will have no
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* effect on first boot of the CPU since it should already be
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* in reset.
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*/
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tegra_put_cpu_in_reset(cpu);
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/*
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* Unhalt the CPU. If the flow controller was used to
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* power-gate the CPU this will cause the flow controller to
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* stop driving reset. The CPU will remain in reset because the
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* clock and reset block is now driving reset.
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*/
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flowctrl_write_cpu_halt(cpu, 0);
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tegra_enable_cpu_clock(cpu);
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flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
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tegra_cpu_out_of_reset(cpu);
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return 0;
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}
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static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int ret;
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unsigned long timeout;
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cpu = cpu_logical_map(cpu);
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tegra_put_cpu_in_reset(cpu);
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flowctrl_write_cpu_halt(cpu, 0);
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/*
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* The power up sequence of cold boot CPU and warm boot CPU
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* was different.
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*
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* For warm boot CPU that was resumed from CPU hotplug, the
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* power will be resumed automatically after un-halting the
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* flow controller of the warm boot CPU. We need to wait for
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* the confirmaiton that the CPU is powered then removing
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* the IO clamps.
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* For cold boot CPU, do not wait. After the cold boot CPU be
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* booted, it will run to tegra_secondary_init() and set
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* tegra_cpu_init_mask which influences what tegra30_boot_secondary()
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* next time around.
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*/
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if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
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timeout = jiffies + msecs_to_jiffies(50);
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do {
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if (tegra_pmc_cpu_is_powered(cpu))
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goto remove_clamps;
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udelay(10);
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} while (time_before(jiffies, timeout));
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}
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/*
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* The power status of the cold boot CPU is power gated as
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* default. To power up the cold boot CPU, the power should
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* be un-gated by un-toggling the power gate register
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* manually.
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*/
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ret = tegra_pmc_cpu_power_on(cpu);
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if (ret)
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return ret;
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remove_clamps:
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/* CPU partition is powered. Enable the CPU clock. */
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tegra_enable_cpu_clock(cpu);
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udelay(10);
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/* Remove I/O clamps. */
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ret = tegra_pmc_cpu_remove_clamping(cpu);
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if (ret)
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return ret;
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udelay(10);
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flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
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tegra_cpu_out_of_reset(cpu);
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return 0;
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}
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static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int ret = 0;
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cpu = cpu_logical_map(cpu);
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if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
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/*
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* Warm boot flow
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* The flow controller in charge of the power state and
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* control for each CPU.
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*/
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/* set SCLK as event trigger for flow controller */
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flowctrl_write_cpu_csr(cpu, 1);
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flowctrl_write_cpu_halt(cpu,
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FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
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} else {
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/*
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* Cold boot flow
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* The CPU is powered up by toggling PMC directly. It will
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* also initial power state in flow controller. After that,
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* the CPU's power state is maintained by flow controller.
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*/
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ret = tegra_pmc_cpu_power_on(cpu);
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}
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return ret;
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}
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static int tegra_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20)
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return tegra20_boot_secondary(cpu, idle);
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30)
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return tegra30_boot_secondary(cpu, idle);
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114)
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return tegra114_boot_secondary(cpu, idle);
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124)
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return tegra114_boot_secondary(cpu, idle);
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return -EINVAL;
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}
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static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
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{
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/* Always mark the boot CPU (CPU0) as initialized. */
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cpumask_set_cpu(0, &tegra_cpu_init_mask);
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if (scu_a9_has_base())
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scu_enable(IO_ADDRESS(scu_a9_get_base()));
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}
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const struct smp_operations tegra_smp_ops __initconst = {
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.smp_prepare_cpus = tegra_smp_prepare_cpus,
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.smp_secondary_init = tegra_secondary_init,
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.smp_boot_secondary = tegra_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = tegra_cpu_kill,
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.cpu_die = tegra_cpu_die,
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#endif
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};
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