mirror of https://gitee.com/openkylin/linux.git
121 lines
2.6 KiB
C
121 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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#include <asm/barrier.h>
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/* for L1-cache */
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#define INS_CACHE (1 << 0)
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#define DATA_CACHE (1 << 1)
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#define CACHE_INV (1 << 4)
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#define CACHE_CLR (1 << 5)
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#define CACHE_OMS (1 << 6)
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void local_icache_inv_all(void *priv)
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{
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mtcr("cr17", INS_CACHE|CACHE_INV);
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sync_is();
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}
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#ifdef CONFIG_CPU_HAS_ICACHE_INS
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("icache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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#else
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struct cache_range {
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unsigned long start;
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unsigned long end;
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};
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static DEFINE_SPINLOCK(cache_lock);
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static inline void cache_op_line(unsigned long i, unsigned int val)
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{
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mtcr("cr22", i);
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mtcr("cr17", val);
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}
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void local_icache_inv_range(void *priv)
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{
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struct cache_range *param = priv;
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unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
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unsigned long flags;
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spin_lock_irqsave(&cache_lock, flags);
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for (; i < param->end; i += L1_CACHE_BYTES)
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cache_op_line(i, INS_CACHE | CACHE_INV | CACHE_OMS);
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spin_unlock_irqrestore(&cache_lock, flags);
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sync_is();
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}
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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struct cache_range param = { start, end };
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if (irqs_disabled())
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local_icache_inv_range(¶m);
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else
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on_each_cpu(local_icache_inv_range, ¶m, 1);
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}
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#endif
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inline void dcache_wb_line(unsigned long start)
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{
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asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
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sync_is();
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}
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void dcache_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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}
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void cache_wbinv_range(unsigned long start, unsigned long end)
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{
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dcache_wb_range(start, end);
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icache_inv_range(start, end);
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}
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EXPORT_SYMBOL(cache_wbinv_range);
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void dma_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cva %0\n"::"r"(i):"memory");
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sync_is();
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}
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