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Linus Torvalds 58d4fafd0b RISC-V updates for v5.4-rc1 
Add the following new features:
 
 - Generic CPU topology description support for DT-based platforms,
   including ARM64, ARM and RISC-V.
 
 - Sparsemem support
 
 - Perf callchain support
 
 - SiFive PLIC irqchip modifications, in preparation for M-mode Linux
 
 and clean up the code base:
 
 - Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
   flushing, and the RISC-V CPU-local timer code
 
 - Kbuild cleanup from one of the Kbuild maintainers
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Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley:
 "Add the following new features:

   - Generic CPU topology description support for DT-based platforms,
     including ARM64, ARM and RISC-V.

   - Sparsemem support

   - Perf callchain support

   - SiFive PLIC irqchip modifications, in preparation for M-mode Linux

  and clean up the code base:

   - Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
     flushing, and the RISC-V CPU-local timer code

   - Kbuild cleanup from one of the Kbuild maintainers"

[ The CPU topology parts came in through the arm64 tree with a shared
  branch   - Linus ]

* tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  irqchip/sifive-plic: set max threshold for ignored handlers
  riscv: move the TLB flush logic out of line
  riscv: don't use the rdtime(h) pseudo-instructions
  riscv: cleanup riscv_cpuid_to_hartid_mask
  riscv: optimize send_ipi_single
  riscv: cleanup send_ipi_mask
  riscv: refactor the IPI code
  riscv: Add support for libdw
  riscv: Add support for perf registers sampling
  riscv: Add perf callchain support
  riscv: add arch/riscv/Kbuild
  RISC-V: Implement sparsemem
  riscv: Using CSR numbers to access CSRs
 		2019-09-16 15:29:34 -07:00
..
vdso riscv: Fix perf record without libelf support 2019-07-31 12:26:10 -07:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
Makefile riscv: Add support for perf registers sampling 2019-09-05 00:48:58 -07:00
asm-offsets.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
cacheinfo.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
cpu.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
cpufeature.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 2019-06-19 17:09:07 +02:00
entry.S riscv: Using CSR numbers to access CSRs 2019-08-30 11:04:19 -07:00
fpu.S riscv: Using CSR numbers to access CSRs 2019-08-30 11:04:19 -07:00
ftrace.c riscv: add missing newlines to printk messages 2019-02-11 15:34:56 -08:00
head.S RISC-V updates for v5.4-rc1 2019-09-16 15:29:34 -07:00
irq.c RISC-V: Add interrupt related SCAUSE defines in asm/csr.h 2019-05-16 20:42:11 -07:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S RISC-V: remove the unused return_to_handler export 2018-10-22 17:38:12 -07:00
module-sections.c RISC-V: Support MODULE_SECTIONS mechanism on RV32 2019-01-07 08:19:20 -08:00
module.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
perf_callchain.c riscv: Add perf callchain support 2019-09-04 12:43:00 -07:00
perf_event.c RISC-V: Access CSRs using CSR numbers 2019-05-16 20:42:11 -07:00
perf_regs.c riscv: Add support for perf registers sampling 2019-09-05 00:48:58 -07:00
process.c riscv: Correct the initialized flow of FP register 2019-08-14 13:11:11 -07:00
ptrace.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
reset.c RISC-V patches for v5.2-rc6 2019-06-17 10:34:03 -07:00
riscv_ksyms.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
setup.c RISC-V: Setup initial page tables in two stages 2019-07-09 09:08:04 -07:00
signal.c Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace 2019-07-08 21:48:15 -07:00
smp.c riscv: cleanup riscv_cpuid_to_hartid_mask 2019-09-05 01:51:57 -07:00
smpboot.c RISC-V: Parse cpu topology during boot. 2019-07-22 09:36:30 -07:00
stacktrace.c riscv: Add perf callchain support 2019-09-04 12:43:00 -07:00
sys_riscv.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
syscall_table.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
time.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
traps.c Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace 2019-07-08 21:48:15 -07:00
vdso.c riscv: Remove gate area stubs 2019-07-01 13:13:36 -07:00
vmlinux.lds.S treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00