mirror of https://gitee.com/openkylin/linux.git
18a8d49973
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
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Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
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| at91 | ||
| bcm | ||
| berlin | ||
| hisilicon | ||
| keystone | ||
| mmp | ||
| mvebu | ||
| mxs | ||
| pxa | ||
| qcom | ||
| rockchip | ||
| samsung | ||
| shmobile | ||
| sirf | ||
| socfpga | ||
| spear | ||
| st | ||
| sunxi | ||
| tegra | ||
| ti | ||
| ux500 | ||
| versatile | ||
| x86 | ||
| zynq | ||
| Kconfig | ||
| Makefile | ||
| clk-asm9260.c | ||
| clk-axi-clkgen.c | ||
| clk-axm5516.c | ||
| clk-bcm2835.c | ||
| clk-cdce706.c | ||
| clk-clps711x.c | ||
| clk-composite.c | ||
| clk-conf.c | ||
| clk-devres.c | ||
| clk-divider.c | ||
| clk-efm32gg.c | ||
| clk-fixed-factor.c | ||
| clk-fixed-rate.c | ||
| clk-fractional-divider.c | ||
| clk-gate.c | ||
| clk-gpio-gate.c | ||
| clk-highbank.c | ||
| clk-ls1x.c | ||
| clk-max-gen.c | ||
| clk-max-gen.h | ||
| clk-max77686.c | ||
| clk-max77802.c | ||
| clk-moxart.c | ||
| clk-mux.c | ||
| clk-nomadik.c | ||
| clk-nspire.c | ||
| clk-palmas.c | ||
| clk-qoriq.c | ||
| clk-rk808.c | ||
| clk-s2mps11.c | ||
| clk-si570.c | ||
| clk-si5351.c | ||
| clk-si5351.h | ||
| clk-twl6040.c | ||
| clk-u300.c | ||
| clk-vt8500.c | ||
| clk-wm831x.c | ||
| clk-xgene.c | ||
| clk.c | ||
| clk.h | ||
| clkdev.c | ||